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Rafal Jaworowski692519b2006-08-10 12:43:17 +02001/*
Grzegorz Bernackic9240982007-07-31 18:51:48 +02002 * (C) Copyright 2006 - 2007
Rafal Jaworowski692519b2006-08-10 12:43:17 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
Stefan Roese4dbee8a2007-10-05 07:57:20 +020023/* define DEBUG for debugging output (obviously ;-)) */
Stefan Roeseff68f662007-10-05 09:22:33 +020024#if 0
Stefan Roese4dbee8a2007-10-05 07:57:20 +020025#define DEBUG
26#endif
27
Rafal Jaworowski692519b2006-08-10 12:43:17 +020028#include <asm/processor.h>
29#include <asm-ppc/io.h>
30#include <ppc4xx.h>
31#include <common.h>
32#include <pci.h>
33
Stefan Roese97923772007-10-05 09:18:23 +020034#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \
35 defined(CONFIG_PCI)
Rafal Jaworowski692519b2006-08-10 12:43:17 +020036
Stefan Roesec7c6da22007-10-03 07:34:10 +020037#include <asm/4xx_pcie.h>
Rafal Jaworowski692519b2006-08-10 12:43:17 +020038
39enum {
40 PTYPE_ENDPOINT = 0x0,
41 PTYPE_LEGACY_ENDPOINT = 0x1,
42 PTYPE_ROOT_PORT = 0x4,
43
44 LNKW_X1 = 0x1,
45 LNKW_X4 = 0x4,
46 LNKW_X8 = 0x8
47};
48
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020049static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
50{
51 u8 *base = (u8*)hose->cfg_data;
52
53 /* use local configuration space for the first bus */
54 if (PCI_BUS(devfn) == 0) {
55 if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
56 base = (u8*)CFG_PCIE0_XCFGBASE;
57 if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
58 base = (u8*)CFG_PCIE1_XCFGBASE;
Stefan Roese97923772007-10-05 09:18:23 +020059#if CFG_PCIE_NR_PORTS > 2
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020060 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
61 base = (u8*)CFG_PCIE2_XCFGBASE;
Stefan Roese97923772007-10-05 09:18:23 +020062#endif
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020063 }
64
65 return base;
66}
67
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020068static void pcie_dmer_disable(void)
Grzegorz Bernackic9240982007-07-31 18:51:48 +020069{
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020070 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
71 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
72 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
73 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
Stefan Roese97923772007-10-05 09:18:23 +020074#if CFG_PCIE_NR_PORTS > 2
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020075 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
76 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
Stefan Roese97923772007-10-05 09:18:23 +020077#endif
Grzegorz Bernackic9240982007-07-31 18:51:48 +020078}
79
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020080static void pcie_dmer_enable(void)
Grzegorz Bernackic9240982007-07-31 18:51:48 +020081{
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020082 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
83 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
84 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
85 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
Stefan Roese97923772007-10-05 09:18:23 +020086#if CFG_PCIE_NR_PORTS > 2
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020087 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
88 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
Stefan Roese97923772007-10-05 09:18:23 +020089#endif
Grzegorz Bernackic9240982007-07-31 18:51:48 +020090}
91
Rafal Jaworowski692519b2006-08-10 12:43:17 +020092static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
93 int offset, int len, u32 *val) {
94
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020095 u8 *address;
Rafal Jaworowski692519b2006-08-10 12:43:17 +020096 *val = 0;
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020097
Rafal Jaworowski692519b2006-08-10 12:43:17 +020098 /*
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020099 * Bus numbers are relative to hose->first_busno
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200100 */
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200101 devfn -= PCI_BDF(hose->first_busno, 0, 0);
102
103 /*
104 * NOTICE: configuration space ranges are currenlty mapped only for
105 * the first 16 buses, so such limit must be imposed. In case more
106 * buses are required the TLB settings in board/amcc/<board>/init.S
107 * need to be altered accordingly (one bus takes 1 MB of memory space).
108 */
109 if (PCI_BUS(devfn) >= 16)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200110 return 0;
111
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200112 /*
113 * Only single device/single function is supported for the primary and
114 * secondary buses of the 440SPe host bridge.
115 */
116 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
117 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
118 return 0;
Stefan Roese738815c2007-10-02 11:44:46 +0200119
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200120 address = pcie_get_base(hose, devfn);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200121 offset += devfn << 4;
122
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200123 /*
124 * Reading from configuration space of non-existing device can
125 * generate transaction errors. For the read duration we suppress
126 * assertion of machine check exceptions to avoid those.
127 */
128 pcie_dmer_disable ();
129
Stefan Roese97923772007-10-05 09:18:23 +0200130 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200131 switch (len) {
132 case 1:
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200133 *val = in_8(hose->cfg_data + offset);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200134 break;
135 case 2:
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200136 *val = in_le16((u16 *)(hose->cfg_data + offset));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200137 break;
138 default:
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200139 *val = in_le32((u32*)(hose->cfg_data + offset));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200140 break;
141 }
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200142
143 pcie_dmer_enable ();
144
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200145 return 0;
146}
147
148static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
149 int offset, int len, u32 val) {
150
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200151 u8 *address;
Stefan Roese738815c2007-10-02 11:44:46 +0200152
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200153 /*
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200154 * Bus numbers are relative to hose->first_busno
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200155 */
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200156 devfn -= PCI_BDF(hose->first_busno, 0, 0);
Stefan Roese738815c2007-10-02 11:44:46 +0200157
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200158 /*
159 * Same constraints as in pcie_read_config().
160 */
161 if (PCI_BUS(devfn) >= 16)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200162 return 0;
163
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200164 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
165 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
166 return 0;
Stefan Roese738815c2007-10-02 11:44:46 +0200167
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200168 address = pcie_get_base(hose, devfn);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200169 offset += devfn << 4;
170
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200171 /*
172 * Suppress MCK exceptions, similar to pcie_read_config()
173 */
174 pcie_dmer_disable ();
175
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200176 switch (len) {
177 case 1:
178 out_8(hose->cfg_data + offset, val);
179 break;
180 case 2:
181 out_le16((u16 *)(hose->cfg_data + offset), val);
182 break;
183 default:
184 out_le32((u32 *)(hose->cfg_data + offset), val);
185 break;
186 }
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200187
188 pcie_dmer_enable ();
189
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200190 return 0;
191}
192
193int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
194{
195 u32 v;
196 int rv;
197
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200198 rv = pcie_read_config(hose, dev, offset, 1, &v);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200199 *val = (u8)v;
200 return rv;
201}
202
203int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
204{
205 u32 v;
206 int rv;
207
208 rv = pcie_read_config(hose, dev, offset, 2, &v);
209 *val = (u16)v;
210 return rv;
211}
212
213int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
214{
215 u32 v;
216 int rv;
217
218 rv = pcie_read_config(hose, dev, offset, 3, &v);
219 *val = (u32)v;
220 return rv;
221}
222
223int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
224{
225 return pcie_write_config(hose,(u32)dev,offset,1,val);
226}
227
228int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
229{
230 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
231}
232
233int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
234{
235 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
236}
237
Stefan Roese97923772007-10-05 09:18:23 +0200238#if defined(CONFIG_440SPE)
Stefan Roese026f7112007-10-03 07:48:09 +0200239static void ppc4xx_setup_utl(u32 port) {
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200240
241 volatile void *utl_base = NULL;
242
243 /*
244 * Map UTL registers
245 */
246 switch (port) {
247 case 0:
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200248 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
249 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
250 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200251 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200252 break;
253
254 case 1:
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200255 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
256 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
257 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200258 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200259 break;
260
261 case 2:
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200262 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
263 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
264 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200265 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200266 break;
267 }
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200268 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
Wolfgang Denk16850912006-08-27 18:10:01 +0200269
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200270 /*
271 * Set buffer allocations and then assert VRB and TXE.
272 */
273 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
274 out_be32(utl_base + PEUTL_INTR, 0x02000000);
275 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
276 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
277 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
278 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
279 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200280 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200281}
282
283static int check_error(void)
284{
285 u32 valPE0, valPE1, valPE2;
286 int err = 0;
287
288 /* SDR0_PEGPLLLCT1 reset */
289 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
290 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
291 }
292
293 valPE0 = SDR_READ(PESDR0_RCSSET);
294 valPE1 = SDR_READ(PESDR1_RCSSET);
295 valPE2 = SDR_READ(PESDR2_RCSSET);
296
297 /* SDR0_PExRCSSET rstgu */
298 if (!(valPE0 & 0x01000000) ||
299 !(valPE1 & 0x01000000) ||
300 !(valPE2 & 0x01000000)) {
301 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
302 err = -1;
303 }
304
305 /* SDR0_PExRCSSET rstdl */
306 if (!(valPE0 & 0x00010000) ||
307 !(valPE1 & 0x00010000) ||
308 !(valPE2 & 0x00010000)) {
309 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
310 err = -1;
311 }
312
313 /* SDR0_PExRCSSET rstpyn */
314 if ((valPE0 & 0x00001000) ||
315 (valPE1 & 0x00001000) ||
316 (valPE2 & 0x00001000)) {
317 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
318 err = -1;
319 }
320
321 /* SDR0_PExRCSSET hldplb */
322 if ((valPE0 & 0x10000000) ||
323 (valPE1 & 0x10000000) ||
324 (valPE2 & 0x10000000)) {
325 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
326 err = -1;
327 }
328
329 /* SDR0_PExRCSSET rdy */
330 if ((valPE0 & 0x00100000) ||
331 (valPE1 & 0x00100000) ||
332 (valPE2 & 0x00100000)) {
333 printf("PCIE: SDR0_PExRCSSET rdy error\n");
334 err = -1;
335 }
336
337 /* SDR0_PExRCSSET shutdown */
338 if ((valPE0 & 0x00000100) ||
339 (valPE1 & 0x00000100) ||
340 (valPE2 & 0x00000100)) {
341 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
342 err = -1;
343 }
344 return err;
345}
346
347/*
348 * Initialize PCI Express core
349 */
Stefan Roese026f7112007-10-03 07:48:09 +0200350int ppc4xx_init_pcie(void)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200351{
352 int time_out = 20;
353
354 /* Set PLL clock receiver to LVPECL */
355 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
356
357 if (check_error())
358 return -1;
359
360 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
361 {
362 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
363 SDR_READ(PESDR0_PLLLCT2));
364 return -1;
365 }
366 /* De-assert reset of PCIe PLL, wait for lock */
367 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
368 udelay(3);
369
Stefan Roese2b393b02006-08-29 08:05:15 +0200370 while (time_out) {
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200371 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
372 time_out--;
373 udelay(1);
374 } else
375 break;
376 }
377 if (!time_out) {
378 printf("PCIE: VCO output not locked\n");
379 return -1;
380 }
381 return 0;
382}
Stefan Roese97923772007-10-05 09:18:23 +0200383#else
384int ppc4xx_init_pcie(void)
385{
386 /*
387 * Nothing to do on 405EX
388 */
389 return 0;
390}
391#endif
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200392
Stefan Roese2b393b02006-08-29 08:05:15 +0200393/*
Stefan Roese03d344b2007-10-03 10:38:09 +0200394 * Board-specific pcie initialization
395 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
396 */
397
398/*
399 * Initialize various parts of the PCI Express core for our port:
400 *
401 * - Set as a root port and enable max width
402 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
403 * - Set up UTL configuration.
404 * - Increase SERDES drive strength to levels suggested by AMCC.
405 * - De-assert RSTPYN, RSTDL and RSTGU.
406 *
407 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
408 * with default setting 0x11310000. The register has new fields,
409 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
410 * hang.
411 */
412#if defined(CONFIG_440SPE)
413int __ppc4xx_init_pcie_port_hw(int port, int rootport)
414{
415 u32 val = 1 << 24;
416 u32 utlset1;
417
418 if (rootport) {
419 val = PTYPE_ROOT_PORT << 20;
420 utlset1 = 0x21222222;
421 } else {
422 val = PTYPE_LEGACY_ENDPOINT << 20;
423 utlset1 = 0x20222222;
424 }
425
426 if (port == 0)
427 val |= LNKW_X8 << 12;
428 else
429 val |= LNKW_X4 << 12;
430
431 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
432 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
433 if (!ppc440spe_revB())
434 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
435 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
436 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
437 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
438 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
439 if (port == 0) {
440 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
441 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
442 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
443 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
444 }
445 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
446 ~(1 << 24 | 1 << 16)) | 1 << 12);
447
448 return 0;
449}
450#endif /* CONFIG_440SPE */
451
452#if defined(CONFIG_405EX)
453int __ppc4xx_init_pcie_port_hw(int port, int rootport)
454{
455 u32 val;
456
Stefan Roese94276eb2007-10-03 14:14:58 +0200457 /*
458 * test-only:
459 * This needs some testing and perhaps changes for
460 * endpoint configuration. Probably no PHY reset at all, etc.
461 * sr, 2007-10-03
462 */
Stefan Roese03d344b2007-10-03 10:38:09 +0200463 if (rootport)
464 val = 0x00401000;
465 else
466 val = 0x00101000;
467
468 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
469 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
470 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
471 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
472 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
473
474 /* Assert the PE0_PHY reset */
475 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
476 udelay(1000);
477
478 /* deassert the PE0_hotreset */
479 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
480
481 /* poll for phy !reset */
482 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
483 ;
484
485 /* deassert the PE0_gpl_utl_reset */
486 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
487
488 if (port == 0)
489 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
490 else
491 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
492
493 return 0;
494}
495#endif /* CONFIG_405EX */
496
497int ppc4xx_init_pcie_port_hw(int port, int rootport)
498 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
499
500/*
501 * We map PCI Express configuration access into the 512MB regions
502 *
503 * NOTICE: revB is very strict about PLB real addressess and ranges to
504 * be mapped for config space; it seems to only work with d_nnnn_nnnn
505 * range (hangs the core upon config transaction attempts when set
506 * otherwise) while revA uses c_nnnn_nnnn.
507 *
508 * For revA:
509 * PCIE0: 0xc_4000_0000
510 * PCIE1: 0xc_8000_0000
511 * PCIE2: 0xc_c000_0000
512 *
513 * For revB:
514 * PCIE0: 0xd_0000_0000
515 * PCIE1: 0xd_2000_0000
516 * PCIE2: 0xd_4000_0000
517 *
518 * For 405EX:
519 * PCIE0: 0xa000_0000
520 * PCIE1: 0xc000_0000
521 */
522static inline u64 ppc4xx_get_cfgaddr(int port)
523{
524#if defined(CONFIG_405EX)
525 if (port == 0)
526 return (u64)CFG_PCIE0_CFGBASE;
527 else
528 return (u64)CFG_PCIE1_CFGBASE;
529#endif
530#if defined(CONFIG_440SPE)
531 if (ppc440spe_revB()) {
532 switch (port) {
533 default: /* to satisfy compiler */
534 case 0:
535 return 0x0000000d00000000ULL;
536 case 1:
537 return 0x0000000d20000000ULL;
538 case 2:
539 return 0x0000000d40000000ULL;
540 }
541 } else {
542 switch (port) {
543 default: /* to satisfy compiler */
544 case 0:
545 return 0x0000000c40000000ULL;
546 case 1:
547 return 0x0000000c80000000ULL;
548 case 2:
549 return 0x0000000cc0000000ULL;
550 }
551 }
552#endif
553}
554
555/*
556 * 4xx boards as end point and root point setup
Stefan Roese2b393b02006-08-29 08:05:15 +0200557 * and
558 * testing inbound and out bound windows
559 *
Stefan Roese03d344b2007-10-03 10:38:09 +0200560 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
Stefan Roese2b393b02006-08-29 08:05:15 +0200561 * cable which can be used to setup loop back from one port to another port.
562 * Please rememeber that unless there is a endpoint plugged in to root port it
563 * will not initialize. It is the same in case of endpoint , unless there is
564 * root port attached it will not initialize.
565 *
566 * In this release of software all the PCI-E ports are configured as either
567 * endpoint or rootpoint.In future we will have support for selective ports
568 * setup as endpoint and root point in single board.
569 *
570 * Once your board came up as root point , you can verify by reading
571 * /proc/bus/pci/devices. Where you can see the configuration registers
572 * of end point device attached to the port.
573 *
Stefan Roese03d344b2007-10-03 10:38:09 +0200574 * Enpoint cofiguration can be verified by connecting 4xx board to any
575 * host or another 4xx board. Then try to scan the device. In case of
Stefan Roese2b393b02006-08-29 08:05:15 +0200576 * linux use "lspci" or appripriate os command.
577 *
Stefan Roese03d344b2007-10-03 10:38:09 +0200578 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
Stefan Roese2b393b02006-08-29 08:05:15 +0200579 * in this configuration inbound and outbound windows are setup to access
580 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
581 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
582 * This is waere your POM(PLB out bound memory window) mapped. then
Stefan Roese03d344b2007-10-03 10:38:09 +0200583 * read the data from other 4xx board's u-boot prompt at address
Stefan Roese2b393b02006-08-29 08:05:15 +0200584 * 0x9000 0000(SRAM). Data should match.
585 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
586 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
587 * data at 0x9000 0000(SRAM).Data should match.
588 */
Stefan Roese03d344b2007-10-03 10:38:09 +0200589int ppc4xx_init_pcie_port(int port, int rootport)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200590{
591 static int core_init;
592 volatile u32 val = 0;
593 int attempts;
Stefan Roese03d344b2007-10-03 10:38:09 +0200594 u64 addr;
595 u32 low, high;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200596
597 if (!core_init) {
598 ++core_init;
Stefan Roese026f7112007-10-03 07:48:09 +0200599 if (ppc4xx_init_pcie())
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200600 return -1;
601 }
602
603 /*
Stefan Roese03d344b2007-10-03 10:38:09 +0200604 * Initialize various parts of the PCI Express core for our port
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200605 */
Stefan Roese03d344b2007-10-03 10:38:09 +0200606 ppc4xx_init_pcie_port_hw(port, rootport);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200607
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200608 /*
609 * Notice: the following delay has critical impact on device
610 * initialization - if too short (<50ms) the link doesn't get up.
611 */
612 mdelay(100);
613
Stefan Roese6d952892007-10-03 21:16:32 +0200614 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200615 if (val & (1 << 20)) {
616 printf("PCIE%d: PGRST failed %08x\n", port, val);
617 return -1;
618 }
619
620 /*
621 * Verify link is up
622 */
Stefan Roese6d952892007-10-03 21:16:32 +0200623 val = SDR_READ(SDRN_PESDR_LOOP(port));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200624 if (!(val & 0x00001000)) {
625 printf("PCIE%d: link is not up.\n", port);
626 return -1;
627 }
628
Stefan Roese97923772007-10-05 09:18:23 +0200629#if defined(CONFIG_440SPE)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200630 /*
631 * Setup UTL registers - but only on revA!
632 * We use default settings for revB chip.
633 */
634 if (!ppc440spe_revB())
Stefan Roese026f7112007-10-03 07:48:09 +0200635 ppc4xx_setup_utl(port);
Stefan Roese97923772007-10-05 09:18:23 +0200636#endif
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200637
638 /*
639 * We map PCI Express configuration access into the 512MB regions
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200640 */
Stefan Roese03d344b2007-10-03 10:38:09 +0200641 addr = ppc4xx_get_cfgaddr(port);
Stefan Roese97923772007-10-05 09:18:23 +0200642 low = U64_TO_U32_LOW(addr);
643 high = U64_TO_U32_HIGH(addr);
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200644
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200645 switch (port) {
646 case 0:
Stefan Roese03d344b2007-10-03 10:38:09 +0200647 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
648 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200649 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
650 break;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200651 case 1:
Stefan Roese03d344b2007-10-03 10:38:09 +0200652 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
653 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200654 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
655 break;
Stefan Roese97923772007-10-05 09:18:23 +0200656#if CFG_PCIE_NR_PORTS > 2
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200657 case 2:
Stefan Roese03d344b2007-10-03 10:38:09 +0200658 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
659 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200660 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
661 break;
Stefan Roese97923772007-10-05 09:18:23 +0200662#endif
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200663 }
664
665 /*
666 * Check for VC0 active and assert RDY.
667 */
668 attempts = 10;
Stefan Roese6d952892007-10-03 21:16:32 +0200669 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
Stefan Roese03d344b2007-10-03 10:38:09 +0200670 if (!(attempts--)) {
671 printf("PCIE%d: VC0 not active\n", port);
672 return -1;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200673 }
Stefan Roese03d344b2007-10-03 10:38:09 +0200674 mdelay(1000);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200675 }
Stefan Roese6d952892007-10-03 21:16:32 +0200676 SDR_WRITE(SDRN_PESDR_RCSSET(port),
677 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200678 mdelay(100);
679
680 return 0;
681}
682
Stefan Roese03d344b2007-10-03 10:38:09 +0200683int ppc4xx_init_pcie_rootport(int port)
684{
685 return ppc4xx_init_pcie_port(port, 1);
686}
687
Stefan Roese026f7112007-10-03 07:48:09 +0200688int ppc4xx_init_pcie_endport(int port)
Stefan Roese2b393b02006-08-29 08:05:15 +0200689{
Stefan Roese03d344b2007-10-03 10:38:09 +0200690 return ppc4xx_init_pcie_port(port, 0);
Stefan Roese2b393b02006-08-29 08:05:15 +0200691}
692
Stefan Roese026f7112007-10-03 07:48:09 +0200693void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200694{
695 volatile void *mbase = NULL;
Stefan Roese2b393b02006-08-29 08:05:15 +0200696 volatile void *rmbase = NULL;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200697
698 pci_set_ops(hose,
Stefan Roese03d344b2007-10-03 10:38:09 +0200699 pcie_read_config_byte,
700 pcie_read_config_word,
701 pcie_read_config_dword,
702 pcie_write_config_byte,
703 pcie_write_config_word,
704 pcie_write_config_dword);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200705
Stefan Roese2b393b02006-08-29 08:05:15 +0200706 switch (port) {
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200707 case 0:
708 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
Stefan Roese2b393b02006-08-29 08:05:15 +0200709 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200710 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
711 break;
712 case 1:
713 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
Stefan Roese2b393b02006-08-29 08:05:15 +0200714 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200715 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
716 break;
Stefan Roese97923772007-10-05 09:18:23 +0200717#if CFG_PCIE_NR_PORTS > 2
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200718 case 2:
719 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
Stefan Roese2b393b02006-08-29 08:05:15 +0200720 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200721 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
722 break;
Stefan Roese97923772007-10-05 09:18:23 +0200723#endif
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200724 }
725
726 /*
727 * Set bus numbers on our root port
728 */
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200729 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
730 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
731 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200732
733 /*
734 * Set up outbound translation to hose->mem_space from PLB
735 * addresses at an offset of 0xd_0000_0000. We set the low
736 * bits of the mask to 11 to turn off splitting into 8
737 * subregions and to enable the outbound translation.
738 */
739 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
Stefan Roese4dbee8a2007-10-05 07:57:20 +0200740 out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
741 port * CFG_PCIE_MEMSIZE);
742 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
743 in_le32(mbase + PECFG_POM0LAL));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200744
745 switch (port) {
746 case 0:
Stefan Roese97923772007-10-05 09:18:23 +0200747 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
748 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200749 port * CFG_PCIE_MEMSIZE);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200750 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
751 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
Stefan Roese03d344b2007-10-03 10:38:09 +0200752 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese4dbee8a2007-10-05 07:57:20 +0200753 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
754 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
755 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
756 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
757 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200758 break;
759 case 1:
Stefan Roese97923772007-10-05 09:18:23 +0200760 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
761 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200762 port * CFG_PCIE_MEMSIZE);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200763 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
764 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
Stefan Roese03d344b2007-10-03 10:38:09 +0200765 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese4dbee8a2007-10-05 07:57:20 +0200766 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
767 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
768 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
769 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
770 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200771 break;
Stefan Roese97923772007-10-05 09:18:23 +0200772#if CFG_PCIE_NR_PORTS > 2
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200773 case 2:
Stefan Roese97923772007-10-05 09:18:23 +0200774 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
775 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200776 port * CFG_PCIE_MEMSIZE);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200777 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
778 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
Stefan Roese03d344b2007-10-03 10:38:09 +0200779 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese4dbee8a2007-10-05 07:57:20 +0200780 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
781 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
782 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
783 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
784 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200785 break;
Stefan Roese97923772007-10-05 09:18:23 +0200786#endif
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200787 }
788
789 /* Set up 16GB inbound memory window at 0 */
790 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
791 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
792 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
793 out_le32(mbase + PECFG_BAR0LMPA, 0);
Stefan Roese2b393b02006-08-29 08:05:15 +0200794
795 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
796 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200797 out_le32(mbase + PECFG_PIM0LAL, 0);
798 out_le32(mbase + PECFG_PIM0LAH, 0);
Stefan Roese97923772007-10-05 09:18:23 +0200799 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
800 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200801 out_le32(mbase + PECFG_PIMEN, 0x1);
802
803 /* Enable I/O, Mem, and Busmaster cycles */
804 out_le16((u16 *)(mbase + PCI_COMMAND),
805 in_le16((u16 *)(mbase + PCI_COMMAND)) |
806 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
Stefan Roese738815c2007-10-02 11:44:46 +0200807
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200808 /* Set Device and Vendor Id */
Stefan Roese97923772007-10-05 09:18:23 +0200809 out_le16(mbase + 0x200, 0xaaa0 + port);
810 out_le16(mbase + 0x202, 0xbed0 + port);
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200811
812 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
813 out_le32(mbase + 0x208, 0x06040001);
814
Stefan Roese19e93b12007-10-05 14:23:43 +0200815 printf("PCIE%d: successfully set as root-complex\n", port);
Stefan Roese2b393b02006-08-29 08:05:15 +0200816}
817
Stefan Roese026f7112007-10-03 07:48:09 +0200818int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
Stefan Roese2b393b02006-08-29 08:05:15 +0200819{
820 volatile void *mbase = NULL;
821 int attempts = 0;
822
823 pci_set_ops(hose,
824 pcie_read_config_byte,
825 pcie_read_config_word,
826 pcie_read_config_dword,
827 pcie_write_config_byte,
828 pcie_write_config_word,
829 pcie_write_config_dword);
830
831 switch (port) {
832 case 0:
833 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
834 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
835 break;
836 case 1:
837 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
838 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
839 break;
Stefan Roese97923772007-10-05 09:18:23 +0200840#if defined(CFG_PCIE2_CFGBASE)
Stefan Roese2b393b02006-08-29 08:05:15 +0200841 case 2:
842 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
843 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
844 break;
Stefan Roese97923772007-10-05 09:18:23 +0200845#endif
Stefan Roese2b393b02006-08-29 08:05:15 +0200846 }
847
848 /*
849 * Set up outbound translation to hose->mem_space from PLB
850 * addresses at an offset of 0xd_0000_0000. We set the low
851 * bits of the mask to 11 to turn off splitting into 8
852 * subregions and to enable the outbound translation.
853 */
854 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
855 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
856
857 switch (port) {
858 case 0:
Stefan Roese97923772007-10-05 09:18:23 +0200859 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
860 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200861 port * CFG_PCIE_MEMSIZE);
Stefan Roese2b393b02006-08-29 08:05:15 +0200862 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
863 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
Stefan Roese03d344b2007-10-03 10:38:09 +0200864 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese2b393b02006-08-29 08:05:15 +0200865 break;
866 case 1:
Stefan Roese97923772007-10-05 09:18:23 +0200867 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
868 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200869 port * CFG_PCIE_MEMSIZE);
Stefan Roese2b393b02006-08-29 08:05:15 +0200870 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
871 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
Stefan Roese03d344b2007-10-03 10:38:09 +0200872 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese2b393b02006-08-29 08:05:15 +0200873 break;
Stefan Roese97923772007-10-05 09:18:23 +0200874#if CFG_PCIE_NR_PORTS > 2
Stefan Roese2b393b02006-08-29 08:05:15 +0200875 case 2:
Stefan Roese97923772007-10-05 09:18:23 +0200876 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
877 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
Stefan Roese03d344b2007-10-03 10:38:09 +0200878 port * CFG_PCIE_MEMSIZE);
Stefan Roese2b393b02006-08-29 08:05:15 +0200879 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
880 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
Stefan Roese03d344b2007-10-03 10:38:09 +0200881 ~(CFG_PCIE_MEMSIZE - 1) | 3);
Stefan Roese2b393b02006-08-29 08:05:15 +0200882 break;
Stefan Roese97923772007-10-05 09:18:23 +0200883#endif
Stefan Roese2b393b02006-08-29 08:05:15 +0200884 }
885
886 /* Set up 16GB inbound memory window at 0 */
887 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
888 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
889 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
890 out_le32(mbase + PECFG_BAR0LMPA, 0);
Stefan Roese97923772007-10-05 09:18:23 +0200891 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
892 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
Stefan Roese2b393b02006-08-29 08:05:15 +0200893 out_le32(mbase + PECFG_PIMEN, 0x1);
894
895 /* Enable I/O, Mem, and Busmaster cycles */
896 out_le16((u16 *)(mbase + PCI_COMMAND),
Stefan Roese03d344b2007-10-03 10:38:09 +0200897 in_le16((u16 *)(mbase + PCI_COMMAND)) |
898 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
Stefan Roese97923772007-10-05 09:18:23 +0200899 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
900 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
Stefan Roese03d344b2007-10-03 10:38:09 +0200901
Stefan Roese2b393b02006-08-29 08:05:15 +0200902 attempts = 10;
Stefan Roese6d952892007-10-03 21:16:32 +0200903 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
Stefan Roese03d344b2007-10-03 10:38:09 +0200904 if (!(attempts--)) {
905 printf("PCIE%d: BME not active\n", port);
906 return -1;
Stefan Roese2b393b02006-08-29 08:05:15 +0200907 }
Stefan Roese03d344b2007-10-03 10:38:09 +0200908 mdelay(1000);
Stefan Roese2b393b02006-08-29 08:05:15 +0200909 }
Stefan Roese03d344b2007-10-03 10:38:09 +0200910
Stefan Roese19e93b12007-10-05 14:23:43 +0200911 printf("PCIE%d: successfully set as endpoint\n", port);
Stefan Roese2b393b02006-08-29 08:05:15 +0200912
913 return 0;
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200914}
Stefan Roese5fb692c2007-01-18 10:25:34 +0100915#endif /* CONFIG_440SPE && CONFIG_PCI */