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Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08003 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08007 *
8 * with the reference on libata and ahci drvier in kernel
Simon Glass7cf1afc2017-06-14 21:28:37 -06009 *
10 * This driver provides a SCSI interface to SATA.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080011 */
12#include <common.h>
13
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080014#include <command.h>
Simon Glassff758cc2015-11-29 13:18:06 -070015#include <dm.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080016#include <pci.h>
17#include <asm/processor.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090018#include <linux/errno.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080019#include <asm/io.h>
20#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060021#include <memalign.h>
Simon Glass681357f2017-06-14 21:28:46 -060022#include <pci.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080023#include <scsi.h>
Rob Herring344ca0b2013-08-24 10:10:54 -050024#include <libata.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080025#include <linux/ctype.h>
26#include <ahci.h>
Simon Glass681357f2017-06-14 21:28:46 -060027#include <dm/device-internal.h>
28#include <dm/lists.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080029
Simon Glass225b1da2017-06-14 21:28:34 -060030static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
Marc Jones766b16f2012-10-29 05:24:02 +000031
Simon Glass4682c8a2017-06-14 21:28:40 -060032#ifndef CONFIG_DM_SCSI
Simon Glass2c9f9ef2017-06-14 21:28:32 -060033struct ahci_uc_priv *probe_ent = NULL;
Simon Glass4682c8a2017-06-14 21:28:40 -060034#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080035
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050036#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
37
Vadim Bendebury284231e2012-10-29 05:23:44 +000038/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +000039 * Some controllers limit number of blocks they can read/write at once.
40 * Contemporary SSD devices work much faster if the read/write size is aligned
41 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
42 * needed.
Vadim Bendebury284231e2012-10-29 05:23:44 +000043 */
Hung-Te Linb7a21b72012-10-29 05:23:53 +000044#ifndef MAX_SATA_BLOCKS_READ_WRITE
45#define MAX_SATA_BLOCKS_READ_WRITE 0x80
Vadim Bendebury284231e2012-10-29 05:23:44 +000046#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080047
Walter Murphy57847662012-10-29 05:24:00 +000048/* Maximum timeouts for each event */
Rob Herring7610b412013-08-24 10:10:53 -050049#define WAIT_MS_SPINUP 20000
Mark Langsdorff8b009e2015-06-05 00:58:46 +010050#define WAIT_MS_DATAIO 10000
Marc Jones766b16f2012-10-29 05:24:02 +000051#define WAIT_MS_FLUSH 5000
Ian Campbelle0ddcf92014-07-18 20:38:39 +010052#define WAIT_MS_LINKUP 200
Walter Murphy57847662012-10-29 05:24:00 +000053
Stefan Roese22f5de62016-08-31 10:02:15 +020054__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080055{
56 return base + 0x100 + (port * 0x80);
57}
58
59
Tang Yuantianfa313772015-07-09 14:37:30 +080060static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080061 unsigned int port_idx)
62{
63 base = ahci_port_base(base, port_idx);
64
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050065 port->cmd_addr = base;
66 port->scr_addr = base + PORT_SCR;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080067}
68
69
70#define msleep(a) udelay(a * 1000)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050071
Tang Yuantianfa313772015-07-09 14:37:30 +080072static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
Taylor Hutt90b276f2012-10-29 05:23:59 +000073{
74 const unsigned long start = begin;
75 const unsigned long end = start + len;
76
77 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
78 flush_dcache_range(start, end);
79}
80
81/*
82 * SATA controller DMAs to physical RAM. Ensure data from the
83 * controller is invalidated from dcache; next access comes from
84 * physical RAM.
85 */
Tang Yuantianfa313772015-07-09 14:37:30 +080086static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
Taylor Hutt90b276f2012-10-29 05:23:59 +000087{
88 const unsigned long start = begin;
89 const unsigned long end = start + len;
90
91 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
92 invalidate_dcache_range(start, end);
93}
94
95/*
96 * Ensure data for SATA controller is flushed out of dcache and
97 * written to physical memory.
98 */
99static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
100{
101 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
102 AHCI_PORT_PRIV_DMA_SZ);
103}
104
Tang Yuantianfa313772015-07-09 14:37:30 +0800105static int waiting_for_cmd_completed(void __iomem *offset,
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500106 int timeout_msec,
107 u32 sign)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800108{
109 int i;
110 u32 status;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500111
112 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800113 msleep(1);
114
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500115 return (i < timeout_msec) ? 0 : -1;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800116}
117
Simon Glass4b62b2f2017-06-14 21:28:33 -0600118int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
Rob Herring124e9fa2013-08-24 10:10:51 -0500119{
120 u32 tmp;
121 int j = 0;
Simon Glass4b62b2f2017-06-14 21:28:33 -0600122 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
Rob Herring124e9fa2013-08-24 10:10:51 -0500123
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200124 /*
Rob Herring124e9fa2013-08-24 10:10:51 -0500125 * Bring up SATA link.
126 * SATA link bringup time is usually less than 1 ms; only very
127 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
128 */
129 while (j < WAIT_MS_LINKUP) {
130 tmp = readl(port_mmio + PORT_SCR_STAT);
131 tmp &= PORT_SCR_STAT_DET_MASK;
132 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
133 return 0;
134 udelay(1000);
135 j++;
136 }
137 return 1;
138}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800139
Ian Campbella6e50a82014-07-18 20:38:41 +0100140#ifdef CONFIG_SUNXI_AHCI
141/* The sunxi AHCI controller requires this undocumented setup */
Tang Yuantianfa313772015-07-09 14:37:30 +0800142static void sunxi_dma_init(void __iomem *port_mmio)
Ian Campbella6e50a82014-07-18 20:38:41 +0100143{
144 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
145}
146#endif
147
Scott Wood9efaca32015-04-17 09:19:01 -0500148int ahci_reset(void __iomem *base)
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200149{
150 int i = 1000;
Scott Wood9efaca32015-04-17 09:19:01 -0500151 u32 __iomem *host_ctl_reg = base + HOST_CTL;
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200152 u32 tmp = readl(host_ctl_reg); /* global controller reset */
153
154 if ((tmp & HOST_RESET) == 0)
155 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
156
157 /*
158 * reset must complete within 1 second, or
159 * the hardware should be considered fried.
160 */
161 do {
162 udelay(1000);
163 tmp = readl(host_ctl_reg);
164 i--;
165 } while ((i > 0) && (tmp & HOST_RESET));
166
167 if (i == 0) {
168 printf("controller reset failed (0x%x)\n", tmp);
169 return -1;
170 }
171
172 return 0;
173}
174
Simon Glass225b1da2017-06-14 21:28:34 -0600175static int ahci_host_init(struct ahci_uc_priv *uc_priv)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800176{
Michal Simeke8a016b2016-09-08 15:06:45 +0200177#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
Simon Glassff758cc2015-11-29 13:18:06 -0700178# ifdef CONFIG_DM_PCI
Simon Glass225b1da2017-06-14 21:28:34 -0600179 struct udevice *dev = uc_priv->dev;
Simon Glassff758cc2015-11-29 13:18:06 -0700180 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
181# else
Simon Glass225b1da2017-06-14 21:28:34 -0600182 pci_dev_t pdev = uc_priv->dev;
Rob Herring942e3142011-07-06 16:13:36 +0000183 unsigned short vendor;
Simon Glassff758cc2015-11-29 13:18:06 -0700184# endif
185 u16 tmp16;
Rob Herring942e3142011-07-06 16:13:36 +0000186#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600187 void __iomem *mmio = uc_priv->mmio_base;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000188 u32 tmp, cap_save, cmd;
Rob Herring124e9fa2013-08-24 10:10:51 -0500189 int i, j, ret;
Tang Yuantianfa313772015-07-09 14:37:30 +0800190 void __iomem *port_mmio;
Richard Gibbs2915a022013-08-24 10:10:47 -0500191 u32 port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800192
Vadim Bendebury284231e2012-10-29 05:23:44 +0000193 debug("ahci_host_init: start\n");
194
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800195 cap_save = readl(mmio + HOST_CAP);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500196 cap_save &= ((1 << 28) | (1 << 17));
Marc Jones2a0c61d2012-10-29 05:24:01 +0000197 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800198
Simon Glass225b1da2017-06-14 21:28:34 -0600199 ret = ahci_reset(uc_priv->mmio_base);
Dmitry Lifshitz6b688882014-12-15 16:02:55 +0200200 if (ret)
201 return ret;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800202
203 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
204 writel(cap_save, mmio + HOST_CAP);
205 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
206
Michal Simeke8a016b2016-09-08 15:06:45 +0200207#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
Simon Glassff758cc2015-11-29 13:18:06 -0700208# ifdef CONFIG_DM_PCI
209 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
210 u16 tmp16;
211
212 dm_pci_read_config16(dev, 0x92, &tmp16);
213 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
214 }
215# else
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800216 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
217
218 if (vendor == PCI_VENDOR_ID_INTEL) {
219 u16 tmp16;
220 pci_read_config_word(pdev, 0x92, &tmp16);
221 tmp16 |= 0xf;
222 pci_write_config_word(pdev, 0x92, tmp16);
223 }
Simon Glassff758cc2015-11-29 13:18:06 -0700224# endif
Rob Herring942e3142011-07-06 16:13:36 +0000225#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600226 uc_priv->cap = readl(mmio + HOST_CAP);
227 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
228 port_map = uc_priv->port_map;
229 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800230
231 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glass225b1da2017-06-14 21:28:34 -0600232 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800233
Simon Glass225b1da2017-06-14 21:28:34 -0600234 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
235 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000236
Simon Glass225b1da2017-06-14 21:28:34 -0600237 for (i = 0; i < uc_priv->n_ports; i++) {
Richard Gibbs2915a022013-08-24 10:10:47 -0500238 if (!(port_map & (1 << i)))
239 continue;
Simon Glass225b1da2017-06-14 21:28:34 -0600240 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
241 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
242 ahci_setup_port(&uc_priv->port[i], mmio, i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800243
244 /* make sure port is not active */
245 tmp = readl(port_mmio + PORT_CMD);
246 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
247 PORT_CMD_FIS_RX | PORT_CMD_START)) {
Stefan Reinauer7ba79172012-10-29 05:23:50 +0000248 debug("Port %d is active. Deactivating.\n", i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800249 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
250 PORT_CMD_FIS_RX | PORT_CMD_START);
251 writel_with_flush(tmp, port_mmio + PORT_CMD);
252
253 /* spec says 500 msecs for each bit, so
254 * this is slightly incorrect.
255 */
256 msleep(500);
257 }
258
Ian Campbella6e50a82014-07-18 20:38:41 +0100259#ifdef CONFIG_SUNXI_AHCI
260 sunxi_dma_init(port_mmio);
261#endif
262
Marc Jones2a0c61d2012-10-29 05:24:01 +0000263 /* Add the spinup command to whatever mode bits may
264 * already be on in the command register.
265 */
266 cmd = readl(port_mmio + PORT_CMD);
Marc Jones2a0c61d2012-10-29 05:24:01 +0000267 cmd |= PORT_CMD_SPIN_UP;
268 writel_with_flush(cmd, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800269
Rob Herring124e9fa2013-08-24 10:10:51 -0500270 /* Bring up SATA link. */
Simon Glass225b1da2017-06-14 21:28:34 -0600271 ret = ahci_link_up(uc_priv, i);
Rob Herring124e9fa2013-08-24 10:10:51 -0500272 if (ret) {
Marc Jones2a0c61d2012-10-29 05:24:01 +0000273 printf("SATA link %d timeout.\n", i);
274 continue;
275 } else {
276 debug("SATA link ok.\n");
277 }
278
279 /* Clear error status */
280 tmp = readl(port_mmio + PORT_SCR_ERR);
281 if (tmp)
282 writel(tmp, port_mmio + PORT_SCR_ERR);
283
284 debug("Spinning up device on SATA port %d... ", i);
285
286 j = 0;
287 while (j < WAIT_MS_SPINUP) {
288 tmp = readl(port_mmio + PORT_TFDATA);
Rob Herring344ca0b2013-08-24 10:10:54 -0500289 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
Marc Jones2a0c61d2012-10-29 05:24:01 +0000290 break;
291 udelay(1000);
Rob Herring17821082013-08-24 10:10:52 -0500292 tmp = readl(port_mmio + PORT_SCR_STAT);
293 tmp &= PORT_SCR_STAT_DET_MASK;
294 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
295 break;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000296 j++;
297 }
Rob Herring17821082013-08-24 10:10:52 -0500298
299 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
300 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
301 debug("SATA link %d down (COMINIT received), retrying...\n", i);
302 i--;
303 continue;
304 }
305
Marc Jones2a0c61d2012-10-29 05:24:01 +0000306 printf("Target spinup took %d ms.\n", j);
307 if (j == WAIT_MS_SPINUP)
Stefan Reinauer9a65b872012-10-29 05:23:49 +0000308 debug("timeout.\n");
309 else
310 debug("ok.\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800311
312 tmp = readl(port_mmio + PORT_SCR_ERR);
313 debug("PORT_SCR_ERR 0x%x\n", tmp);
314 writel(tmp, port_mmio + PORT_SCR_ERR);
315
316 /* ack any pending irq events for this port */
317 tmp = readl(port_mmio + PORT_IRQ_STAT);
318 debug("PORT_IRQ_STAT 0x%x\n", tmp);
319 if (tmp)
320 writel(tmp, port_mmio + PORT_IRQ_STAT);
321
322 writel(1 << i, mmio + HOST_IRQ_STAT);
323
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000324 /* register linkup ports */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800325 tmp = readl(port_mmio + PORT_SCR_STAT);
Marc Jones766b16f2012-10-29 05:24:02 +0000326 debug("SATA port %d status: 0x%x\n", i, tmp);
Rob Herring2bdb10d2013-08-24 10:10:50 -0500327 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
Simon Glass225b1da2017-06-14 21:28:34 -0600328 uc_priv->link_port_map |= (0x01 << i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800329 }
330
331 tmp = readl(mmio + HOST_CTL);
332 debug("HOST_CTL 0x%x\n", tmp);
333 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
334 tmp = readl(mmio + HOST_CTL);
335 debug("HOST_CTL 0x%x\n", tmp);
Michal Simeke8a016b2016-09-08 15:06:45 +0200336#if !defined(CONFIG_DM_SCSI)
Rob Herring942e3142011-07-06 16:13:36 +0000337#ifndef CONFIG_SCSI_AHCI_PLAT
Simon Glassff758cc2015-11-29 13:18:06 -0700338# ifdef CONFIG_DM_PCI
339 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
340 tmp |= PCI_COMMAND_MASTER;
341 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
342# else
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800343 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
344 tmp |= PCI_COMMAND_MASTER;
345 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
Simon Glassff758cc2015-11-29 13:18:06 -0700346# endif
Rob Herring942e3142011-07-06 16:13:36 +0000347#endif
Michal Simeke8a016b2016-09-08 15:06:45 +0200348#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800349 return 0;
350}
351
352
Simon Glass225b1da2017-06-14 21:28:34 -0600353static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800354{
Michal Simeke8a016b2016-09-08 15:06:45 +0200355#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
356# if defined(CONFIG_DM_PCI)
Simon Glass225b1da2017-06-14 21:28:34 -0600357 struct udevice *dev = uc_priv->dev;
Simon Glassff758cc2015-11-29 13:18:06 -0700358# else
Simon Glass225b1da2017-06-14 21:28:34 -0600359 pci_dev_t pdev = uc_priv->dev;
Simon Glassff758cc2015-11-29 13:18:06 -0700360# endif
Rob Herring942e3142011-07-06 16:13:36 +0000361 u16 cc;
362#endif
Simon Glass225b1da2017-06-14 21:28:34 -0600363 void __iomem *mmio = uc_priv->mmio_base;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000364 u32 vers, cap, cap2, impl, speed;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800365 const char *speed_s;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800366 const char *scc_s;
367
368 vers = readl(mmio + HOST_VERSION);
Simon Glass225b1da2017-06-14 21:28:34 -0600369 cap = uc_priv->cap;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000370 cap2 = readl(mmio + HOST_CAP2);
Simon Glass225b1da2017-06-14 21:28:34 -0600371 impl = uc_priv->port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800372
373 speed = (cap >> 20) & 0xf;
374 if (speed == 1)
375 speed_s = "1.5";
376 else if (speed == 2)
377 speed_s = "3";
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000378 else if (speed == 3)
379 speed_s = "6";
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800380 else
381 speed_s = "?";
382
Michal Simeke8a016b2016-09-08 15:06:45 +0200383#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
Rob Herring942e3142011-07-06 16:13:36 +0000384 scc_s = "SATA";
385#else
Simon Glassff758cc2015-11-29 13:18:06 -0700386# ifdef CONFIG_DM_PCI
387 dm_pci_read_config16(dev, 0x0a, &cc);
388# else
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800389 pci_read_config_word(pdev, 0x0a, &cc);
Simon Glassff758cc2015-11-29 13:18:06 -0700390# endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800391 if (cc == 0x0101)
392 scc_s = "IDE";
393 else if (cc == 0x0106)
394 scc_s = "SATA";
395 else if (cc == 0x0104)
396 scc_s = "RAID";
397 else
398 scc_s = "unknown";
Rob Herring942e3142011-07-06 16:13:36 +0000399#endif
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500400 printf("AHCI %02x%02x.%02x%02x "
401 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
402 (vers >> 24) & 0xff,
403 (vers >> 16) & 0xff,
404 (vers >> 8) & 0xff,
405 vers & 0xff,
406 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800407
408 printf("flags: "
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000409 "%s%s%s%s%s%s%s"
410 "%s%s%s%s%s%s%s"
411 "%s%s%s%s%s%s\n",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500412 cap & (1 << 31) ? "64bit " : "",
413 cap & (1 << 30) ? "ncq " : "",
414 cap & (1 << 28) ? "ilck " : "",
415 cap & (1 << 27) ? "stag " : "",
416 cap & (1 << 26) ? "pm " : "",
417 cap & (1 << 25) ? "led " : "",
418 cap & (1 << 24) ? "clo " : "",
419 cap & (1 << 19) ? "nz " : "",
420 cap & (1 << 18) ? "only " : "",
421 cap & (1 << 17) ? "pmp " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000422 cap & (1 << 16) ? "fbss " : "",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500423 cap & (1 << 15) ? "pio " : "",
424 cap & (1 << 14) ? "slum " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000425 cap & (1 << 13) ? "part " : "",
426 cap & (1 << 7) ? "ccc " : "",
427 cap & (1 << 6) ? "ems " : "",
428 cap & (1 << 5) ? "sxs " : "",
429 cap2 & (1 << 2) ? "apst " : "",
430 cap2 & (1 << 1) ? "nvmp " : "",
431 cap2 & (1 << 0) ? "boh " : "");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800432}
433
Simon Glass745a94f2017-07-04 13:31:18 -0600434#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
Michal Simeke8a016b2016-09-08 15:06:45 +0200435# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
Simon Glass4279efc2017-06-14 21:28:38 -0600436static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
Simon Glassff758cc2015-11-29 13:18:06 -0700437# else
Simon Glass4279efc2017-06-14 21:28:38 -0600438static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
Simon Glassff758cc2015-11-29 13:18:06 -0700439# endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800440{
Michal Simeke8a016b2016-09-08 15:06:45 +0200441#if !defined(CONFIG_DM_SCSI)
Ed Swarthout63cec582007-08-02 14:09:49 -0500442 u16 vendor;
Michal Simeke8a016b2016-09-08 15:06:45 +0200443#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800444 int rc;
445
Simon Glass225b1da2017-06-14 21:28:34 -0600446 uc_priv->dev = dev;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800447
Simon Glass225b1da2017-06-14 21:28:34 -0600448 uc_priv->host_flags = ATA_FLAG_SATA
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500449 | ATA_FLAG_NO_LEGACY
450 | ATA_FLAG_MMIO
451 | ATA_FLAG_PIO_DMA
452 | ATA_FLAG_NO_ATAPI;
Simon Glass225b1da2017-06-14 21:28:34 -0600453 uc_priv->pio_mask = 0x1f;
454 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800455
Michal Simeke8a016b2016-09-08 15:06:45 +0200456#if !defined(CONFIG_DM_SCSI)
Simon Glassff758cc2015-11-29 13:18:06 -0700457#ifdef CONFIG_DM_PCI
Simon Glass225b1da2017-06-14 21:28:34 -0600458 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
Simon Glassff758cc2015-11-29 13:18:06 -0700459 PCI_REGION_MEM);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800460
461 /* Take from kernel:
462 * JMicron-specific fixup:
463 * make sure we're in AHCI mode
464 */
Simon Glassff758cc2015-11-29 13:18:06 -0700465 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500466 if (vendor == 0x197b)
Simon Glassff758cc2015-11-29 13:18:06 -0700467 dm_pci_write_config8(dev, 0x41, 0xa1);
468#else
Simon Glass225b1da2017-06-14 21:28:34 -0600469 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
Simon Glassff758cc2015-11-29 13:18:06 -0700470 PCI_REGION_MEM);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800471
Simon Glassff758cc2015-11-29 13:18:06 -0700472 /* Take from kernel:
473 * JMicron-specific fixup:
474 * make sure we're in AHCI mode
475 */
476 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
477 if (vendor == 0x197b)
478 pci_write_config_byte(dev, 0x41, 0xa1);
479#endif
Michal Simeke8a016b2016-09-08 15:06:45 +0200480#else
Simon Glass1dc64f62017-06-14 21:28:31 -0600481 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
Simon Glass225b1da2017-06-14 21:28:34 -0600482 uc_priv->mmio_base = (void *)plat->base;
Michal Simeke8a016b2016-09-08 15:06:45 +0200483#endif
Simon Glassff758cc2015-11-29 13:18:06 -0700484
Simon Glass225b1da2017-06-14 21:28:34 -0600485 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800486 /* initialize adapter */
Simon Glass225b1da2017-06-14 21:28:34 -0600487 rc = ahci_host_init(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800488 if (rc)
489 goto err_out;
490
Simon Glass225b1da2017-06-14 21:28:34 -0600491 ahci_print_info(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800492
493 return 0;
494
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500495 err_out:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800496 return rc;
497}
Rob Herring942e3142011-07-06 16:13:36 +0000498#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800499
500#define MAX_DATA_BYTE_COUNT (4*1024*1024)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500501
Simon Glass225b1da2017-06-14 21:28:34 -0600502static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
503 unsigned char *buf, int buf_len)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800504{
Simon Glass225b1da2017-06-14 21:28:34 -0600505 struct ahci_ioports *pp = &(uc_priv->port[port]);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800506 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
507 u32 sg_count;
508 int i;
509
510 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500511 if (sg_count > AHCI_MAX_SG) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800512 printf("Error:Too much sg!\n");
513 return -1;
514 }
515
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500516 for (i = 0; i < sg_count; i++) {
517 ahci_sg->addr =
Tang Yuantianfa313772015-07-09 14:37:30 +0800518 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800519 ahci_sg->addr_hi = 0;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500520 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
521 (buf_len < MAX_DATA_BYTE_COUNT
522 ? (buf_len - 1)
523 : (MAX_DATA_BYTE_COUNT - 1)));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800524 ahci_sg++;
525 buf_len -= MAX_DATA_BYTE_COUNT;
526 }
527
528 return sg_count;
529}
530
531
532static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
533{
534 pp->cmd_slot->opts = cpu_to_le32(opts);
535 pp->cmd_slot->status = 0;
Tang Yuantianfa313772015-07-09 14:37:30 +0800536 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
537#ifdef CONFIG_PHYS_64BIT
538 pp->cmd_slot->tbl_addr_hi =
539 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
540#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800541}
542
Tang Yuantianfa313772015-07-09 14:37:30 +0800543static int wait_spinup(void __iomem *port_mmio)
Bin Meng4df2b482014-12-31 17:18:39 +0800544{
545 ulong start;
546 u32 tf_data;
547
548 start = get_timer(0);
549 do {
550 tf_data = readl(port_mmio + PORT_TFDATA);
551 if (!(tf_data & ATA_BUSY))
552 return 0;
553 } while (get_timer(start) < WAIT_MS_SPINUP);
554
555 return -ETIMEDOUT;
556}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800557
Simon Glass225b1da2017-06-14 21:28:34 -0600558static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800559{
Simon Glass225b1da2017-06-14 21:28:34 -0600560 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +0800561 void __iomem *port_mmio = pp->port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800562 u32 port_status;
Tang Yuantianfa313772015-07-09 14:37:30 +0800563 void __iomem *mem;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800564
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500565 debug("Enter start port: %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800566 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500567 debug("Port %d status: %x\n", port, port_status);
568 if ((port_status & 0xf) != 0x03) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800569 printf("No Link on this port!\n");
570 return -1;
571 }
572
Tang Yuantianfa313772015-07-09 14:37:30 +0800573 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800574 if (!mem) {
575 free(pp);
Roger Quadrosd73763a2013-11-11 16:56:37 +0200576 printf("%s: No mem for table!\n", __func__);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800577 return -ENOMEM;
578 }
579
Tang Yuantianfa313772015-07-09 14:37:30 +0800580 /* Aligned to 2048-bytes */
581 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
582 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800583
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800584 /*
585 * First item in chunk of DMA memory: 32-slot command table,
586 * 32 bytes each in size
587 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000588 pp->cmd_slot =
589 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
Tang Yuantianfa313772015-07-09 14:37:30 +0800590 debug("cmd_slot = %p\n", pp->cmd_slot);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800591 mem += (AHCI_CMD_SLOT_SZ + 224);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500592
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800593 /*
594 * Second item: Received-FIS area
595 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000596 pp->rx_fis = virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800597 mem += AHCI_RX_FIS_SZ;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500598
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800599 /*
600 * Third item: data area for storing a single command
601 * and its scatter-gather table
602 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000603 pp->cmd_tbl = virt_to_phys((void *)mem);
Tang Yuantianfa313772015-07-09 14:37:30 +0800604 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800605
606 mem += AHCI_CMD_TBL_HDR;
Taylor Hutt64738e82012-10-29 05:23:58 +0000607 pp->cmd_tbl_sg =
608 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800609
Tang Yuantianfa313772015-07-09 14:37:30 +0800610 writel_with_flush((unsigned long)pp->cmd_slot,
611 port_mmio + PORT_LST_ADDR);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800612
613 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
614
Ian Campbella6e50a82014-07-18 20:38:41 +0100615#ifdef CONFIG_SUNXI_AHCI
616 sunxi_dma_init(port_mmio);
617#endif
618
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800619 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500620 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
621 PORT_CMD_START, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800622
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500623 debug("Exit start port %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800624
Bin Meng4df2b482014-12-31 17:18:39 +0800625 /*
626 * Make sure interface is not busy based on error and status
627 * information from task file data register before proceeding
628 */
629 return wait_spinup(port_mmio);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800630}
631
632
Simon Glass225b1da2017-06-14 21:28:34 -0600633static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
634 int fis_len, u8 *buf, int buf_len, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800635{
636
Simon Glass225b1da2017-06-14 21:28:34 -0600637 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +0800638 void __iomem *port_mmio = pp->port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800639 u32 opts;
640 u32 port_status;
641 int sg_count;
642
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000643 debug("Enter %s: for port %d\n", __func__, port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800644
Simon Glass225b1da2017-06-14 21:28:34 -0600645 if (port > uc_priv->n_ports) {
Taylor Hutt5a2b77f2012-10-29 05:23:56 +0000646 printf("Invalid port number %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800647 return -1;
648 }
649
650 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500651 if ((port_status & 0xf) != 0x03) {
652 debug("No Link on port %d!\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800653 return -1;
654 }
655
656 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
657
Simon Glass225b1da2017-06-14 21:28:34 -0600658 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000659 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800660 ahci_fill_cmd_slot(pp, opts);
661
Taylor Hutt90b276f2012-10-29 05:23:59 +0000662 ahci_dcache_flush_sata_cmd(pp);
Tang Yuantianfa313772015-07-09 14:37:30 +0800663 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
Taylor Hutt90b276f2012-10-29 05:23:59 +0000664
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800665 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
666
Walter Murphy57847662012-10-29 05:24:00 +0000667 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
668 WAIT_MS_DATAIO, 0x1)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800669 printf("timeout exit!\n");
670 return -1;
671 }
Taylor Hutt90b276f2012-10-29 05:23:59 +0000672
Tang Yuantianfa313772015-07-09 14:37:30 +0800673 ahci_dcache_invalidate_range((unsigned long)buf,
674 (unsigned long)buf_len);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000675 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800676
677 return 0;
678}
679
680
681static char *ata_id_strcpy(u16 *target, u16 *src, int len)
682{
683 int i;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500684 for (i = 0; i < len / 2; i++)
Rob Herringe5a6c792011-06-01 09:10:26 +0000685 target[i] = swab16(src[i]);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800686 return (char *)target;
687}
688
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800689/*
690 * SCSI INQUIRY command operation.
691 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600692static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
693 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800694{
Rob Herring48c3a872013-08-24 10:10:48 -0500695 static const u8 hdr[] = {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800696 0,
697 0,
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500698 0x5, /* claim SPC-3 version compatibility */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800699 2,
700 95 - 4,
701 };
702 u8 fis[20];
Roger Quadros3f629712014-04-01 17:26:40 +0300703 u16 *idbuf;
Roger Quadros2faf5fb2013-11-11 16:56:38 +0200704 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800705 u8 port;
706
707 /* Clean ccb data buffer */
708 memset(pccb->pdata, 0, pccb->datalen);
709
710 memcpy(pccb->pdata, hdr, sizeof(hdr));
711
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500712 if (pccb->datalen <= 35)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800713 return 0;
714
Taylor Huttc8731112012-10-29 05:23:55 +0000715 memset(fis, 0, sizeof(fis));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800716 /* Construct the FIS */
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500717 fis[0] = 0x27; /* Host to device FIS. */
718 fis[1] = 1 << 7; /* Command FIS. */
Rob Herring344ca0b2013-08-24 10:10:54 -0500719 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800720
721 /* Read id from sata */
722 port = pccb->target;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800723
Simon Glass225b1da2017-06-14 21:28:34 -0600724 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
725 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800726 debug("scsi_ahci: SCSI inquiry command failure.\n");
727 return -EIO;
728 }
729
Simon Glass4b62b2f2017-06-14 21:28:33 -0600730 if (!uc_priv->ataid[port]) {
731 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
732 if (!uc_priv->ataid[port]) {
Roger Quadros3f629712014-04-01 17:26:40 +0300733 printf("%s: No memory for ataid[port]\n", __func__);
734 return -ENOMEM;
735 }
736 }
737
Simon Glass4b62b2f2017-06-14 21:28:33 -0600738 idbuf = uc_priv->ataid[port];
Roger Quadros3f629712014-04-01 17:26:40 +0300739
740 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
741 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800742
743 memcpy(&pccb->pdata[8], "ATA ", 8);
Roger Quadros3f629712014-04-01 17:26:40 +0300744 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
745 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800746
Rob Herring344ca0b2013-08-24 10:10:54 -0500747#ifdef DEBUG
Roger Quadros3f629712014-04-01 17:26:40 +0300748 ata_dump_id(idbuf);
Rob Herring344ca0b2013-08-24 10:10:54 -0500749#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800750 return 0;
751}
752
753
754/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000755 * SCSI READ10/WRITE10 command operation.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800756 */
Simon Glass225b1da2017-06-14 21:28:34 -0600757static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
758 struct scsi_cmd *pccb, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800759{
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100760 lbaint_t lba = 0;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000761 u16 blocks = 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800762 u8 fis[20];
Vadim Bendebury284231e2012-10-29 05:23:44 +0000763 u8 *user_buffer = pccb->pdata;
764 u32 user_buffer_size = pccb->datalen;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800765
Vadim Bendebury284231e2012-10-29 05:23:44 +0000766 /* Retrieve the base LBA number from the ccb structure. */
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100767 if (pccb->cmd[0] == SCSI_READ16) {
768 memcpy(&lba, pccb->cmd + 2, 8);
769 lba = be64_to_cpu(lba);
770 } else {
771 u32 temp;
772 memcpy(&temp, pccb->cmd + 2, 4);
773 lba = be32_to_cpu(temp);
774 }
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800775
Vadim Bendebury284231e2012-10-29 05:23:44 +0000776 /*
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100777 * Retrieve the base LBA number and the block count from
778 * the ccb structure.
Vadim Bendebury284231e2012-10-29 05:23:44 +0000779 *
780 * For 10-byte and 16-byte SCSI R/W commands, transfer
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800781 * length 0 means transfer 0 block of data.
782 * However, for ATA R/W commands, sector count 0 means
783 * 256 or 65536 sectors, not 0 sectors as in SCSI.
784 *
785 * WARNING: one or two older ATA drives treat 0 as 0...
786 */
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100787 if (pccb->cmd[0] == SCSI_READ16)
788 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
789 else
790 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000791
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100792 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
793 is_write ? "write" : "read", blocks, lba);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000794
795 /* Preset the FIS */
Taylor Huttc8731112012-10-29 05:23:55 +0000796 memset(fis, 0, sizeof(fis));
Vadim Bendebury284231e2012-10-29 05:23:44 +0000797 fis[0] = 0x27; /* Host to device FIS. */
798 fis[1] = 1 << 7; /* Command FIS. */
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000799 /* Command byte (read/write). */
Walter Murphyfe1f8082012-10-29 05:24:03 +0000800 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800801
Vadim Bendebury284231e2012-10-29 05:23:44 +0000802 while (blocks) {
803 u16 now_blocks; /* number of blocks per iteration */
804 u32 transfer_size; /* number of bytes per iteration */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800805
Masahiro Yamadab4141192014-11-07 03:03:31 +0900806 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800807
Rob Herring344ca0b2013-08-24 10:10:54 -0500808 transfer_size = ATA_SECT_SIZE * now_blocks;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000809 if (transfer_size > user_buffer_size) {
810 printf("scsi_ahci: Error: buffer too small.\n");
811 return -EIO;
812 }
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800813
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100814 /*
815 * LBA48 SATA command but only use 32bit address range within
816 * that (unless we've enabled 64bit LBA support). The next
817 * smaller command range (28bit) is too small.
Walter Murphyfe1f8082012-10-29 05:24:03 +0000818 */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000819 fis[4] = (lba >> 0) & 0xff;
820 fis[5] = (lba >> 8) & 0xff;
821 fis[6] = (lba >> 16) & 0xff;
Walter Murphyfe1f8082012-10-29 05:24:03 +0000822 fis[7] = 1 << 6; /* device reg: set LBA mode */
823 fis[8] = ((lba >> 24) & 0xff);
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100824#ifdef CONFIG_SYS_64BIT_LBA
825 if (pccb->cmd[0] == SCSI_READ16) {
826 fis[9] = ((lba >> 32) & 0xff);
827 fis[10] = ((lba >> 40) & 0xff);
828 }
829#endif
830
Walter Murphyfe1f8082012-10-29 05:24:03 +0000831 fis[3] = 0xe0; /* features */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000832
833 /* Block (sector) count */
834 fis[12] = (now_blocks >> 0) & 0xff;
835 fis[13] = (now_blocks >> 8) & 0xff;
836
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000837 /* Read/Write from ahci */
Simon Glass225b1da2017-06-14 21:28:34 -0600838 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
839 sizeof(fis), user_buffer, transfer_size,
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000840 is_write)) {
841 debug("scsi_ahci: SCSI %s10 command failure.\n",
842 is_write ? "WRITE" : "READ");
Vadim Bendebury284231e2012-10-29 05:23:44 +0000843 return -EIO;
844 }
Marc Jones766b16f2012-10-29 05:24:02 +0000845
846 /* If this transaction is a write, do a following flush.
847 * Writes in u-boot are so rare, and the logic to know when is
848 * the last write and do a flush only there is sufficiently
849 * difficult. Just do a flush after every write. This incurs,
850 * usually, one extra flush when the rare writes do happen.
851 */
852 if (is_write) {
Simon Glass225b1da2017-06-14 21:28:34 -0600853 if (-EIO == ata_io_flush(uc_priv, pccb->target))
Marc Jones766b16f2012-10-29 05:24:02 +0000854 return -EIO;
855 }
Vadim Bendebury284231e2012-10-29 05:23:44 +0000856 user_buffer += transfer_size;
857 user_buffer_size -= transfer_size;
858 blocks -= now_blocks;
859 lba += now_blocks;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800860 }
861
862 return 0;
863}
864
865
866/*
867 * SCSI READ CAPACITY10 command operation.
868 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600869static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
870 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800871{
Kumar Galacb6d0b72009-07-13 09:24:00 -0500872 u32 cap;
Rob Herring344ca0b2013-08-24 10:10:54 -0500873 u64 cap64;
Gabe Black19d1d412012-10-29 05:23:54 +0000874 u32 block_size;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800875
Simon Glass4b62b2f2017-06-14 21:28:33 -0600876 if (!uc_priv->ataid[pccb->target]) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800877 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500878 "\tNo ATA info!\n"
Vagrant Cascadian1b25e582015-11-24 14:46:24 -0800879 "\tPlease run SCSI command INQUIRY first!\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800880 return -EPERM;
881 }
882
Simon Glass4b62b2f2017-06-14 21:28:33 -0600883 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Rob Herring344ca0b2013-08-24 10:10:54 -0500884 if (cap64 > 0x100000000ULL)
885 cap64 = 0xffffffff;
Gabe Black19d1d412012-10-29 05:23:54 +0000886
Rob Herring344ca0b2013-08-24 10:10:54 -0500887 cap = cpu_to_be32(cap64);
Kumar Galacb6d0b72009-07-13 09:24:00 -0500888 memcpy(pccb->pdata, &cap, sizeof(cap));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800889
Gabe Black19d1d412012-10-29 05:23:54 +0000890 block_size = cpu_to_be32((u32)512);
891 memcpy(&pccb->pdata[4], &block_size, 4);
892
893 return 0;
894}
895
896
897/*
898 * SCSI READ CAPACITY16 command operation.
899 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600900static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
901 struct scsi_cmd *pccb)
Gabe Black19d1d412012-10-29 05:23:54 +0000902{
903 u64 cap;
904 u64 block_size;
905
Simon Glass4b62b2f2017-06-14 21:28:33 -0600906 if (!uc_priv->ataid[pccb->target]) {
Gabe Black19d1d412012-10-29 05:23:54 +0000907 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
908 "\tNo ATA info!\n"
Vagrant Cascadian1b25e582015-11-24 14:46:24 -0800909 "\tPlease run SCSI command INQUIRY first!\n");
Gabe Black19d1d412012-10-29 05:23:54 +0000910 return -EPERM;
911 }
912
Simon Glass4b62b2f2017-06-14 21:28:33 -0600913 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Gabe Black19d1d412012-10-29 05:23:54 +0000914 cap = cpu_to_be64(cap);
915 memcpy(pccb->pdata, &cap, sizeof(cap));
916
917 block_size = cpu_to_be64((u64)512);
918 memcpy(&pccb->pdata[8], &block_size, 8);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800919
920 return 0;
921}
922
923
924/*
925 * SCSI TEST UNIT READY command operation.
926 */
Simon Glass4b62b2f2017-06-14 21:28:33 -0600927static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
928 struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800929{
Simon Glass4b62b2f2017-06-14 21:28:33 -0600930 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800931}
932
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500933
Simon Glass4e749012017-06-14 21:28:42 -0600934static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800935{
Simon Glass4682c8a2017-06-14 21:28:40 -0600936 struct ahci_uc_priv *uc_priv;
937#ifdef CONFIG_DM_SCSI
Simon Glassbfc1c6b2017-07-04 13:31:22 -0600938 uc_priv = dev_get_uclass_priv(dev->parent);
Simon Glass4682c8a2017-06-14 21:28:40 -0600939#else
940 uc_priv = probe_ent;
941#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800942 int ret;
943
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500944 switch (pccb->cmd[0]) {
Mark Langsdorf2b42c932015-06-05 00:58:45 +0100945 case SCSI_READ16:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800946 case SCSI_READ10:
Simon Glass225b1da2017-06-14 21:28:34 -0600947 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000948 break;
949 case SCSI_WRITE10:
Simon Glass225b1da2017-06-14 21:28:34 -0600950 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800951 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000952 case SCSI_RD_CAPAC10:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600953 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800954 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000955 case SCSI_RD_CAPAC16:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600956 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
Gabe Black19d1d412012-10-29 05:23:54 +0000957 break;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800958 case SCSI_TST_U_RDY:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600959 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800960 break;
961 case SCSI_INQUIRY:
Simon Glass4b62b2f2017-06-14 21:28:33 -0600962 ret = ata_scsiop_inquiry(uc_priv, pccb);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800963 break;
964 default:
965 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
Simon Glassf6580ef2017-06-14 21:28:44 -0600966 return -ENOTSUPP;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800967 }
968
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500969 if (ret) {
970 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
Simon Glassf6580ef2017-06-14 21:28:44 -0600971 return ret;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800972 }
Simon Glassf6580ef2017-06-14 21:28:44 -0600973 return 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800974
975}
976
Simon Glass62b4ec82017-06-14 21:28:36 -0600977static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
978{
979 u32 linkmap;
980 int i;
981
982 linkmap = uc_priv->link_port_map;
983
984 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
985 if (((linkmap >> i) & 0x01)) {
986 if (ahci_port_start(uc_priv, (u8) i)) {
987 printf("Can not start port %d\n", i);
988 continue;
989 }
990 }
991 }
992
993 return 0;
994}
995
Simon Glass7cf1afc2017-06-14 21:28:37 -0600996#ifndef CONFIG_DM_SCSI
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800997void scsi_low_level_init(int busdevfunc)
998{
Simon Glass225b1da2017-06-14 21:28:34 -0600999 struct ahci_uc_priv *uc_priv;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001000
Rob Herring942e3142011-07-06 16:13:36 +00001001#ifndef CONFIG_SCSI_AHCI_PLAT
Simon Glass4279efc2017-06-14 21:28:38 -06001002 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1003 if (!probe_ent) {
1004 printf("%s: No memory for uc_priv\n", __func__);
1005 return;
1006 }
1007 uc_priv = probe_ent;
Michal Simeke8a016b2016-09-08 15:06:45 +02001008# if defined(CONFIG_DM_PCI)
Simon Glassff758cc2015-11-29 13:18:06 -07001009 struct udevice *dev;
1010 int ret;
1011
1012 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1013 if (ret)
1014 return;
Simon Glass4279efc2017-06-14 21:28:38 -06001015 ahci_init_one(uc_priv, dev);
Simon Glassff758cc2015-11-29 13:18:06 -07001016# else
Simon Glass4279efc2017-06-14 21:28:38 -06001017 ahci_init_one(uc_priv, busdevfunc);
Simon Glassff758cc2015-11-29 13:18:06 -07001018# endif
Simon Glass4279efc2017-06-14 21:28:38 -06001019#else
Simon Glass225b1da2017-06-14 21:28:34 -06001020 uc_priv = probe_ent;
Simon Glass4279efc2017-06-14 21:28:38 -06001021#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001022
Simon Glass62b4ec82017-06-14 21:28:36 -06001023 ahci_start_ports(uc_priv);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001024}
Simon Glass7cf1afc2017-06-14 21:28:37 -06001025#endif
1026
1027#ifndef CONFIG_SCSI_AHCI_PLAT
1028# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
Michal Simeke81589e2017-11-02 15:53:56 +01001029int ahci_init_one_dm(struct udevice *dev)
Simon Glass7cf1afc2017-06-14 21:28:37 -06001030{
Simon Glass4279efc2017-06-14 21:28:38 -06001031 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1032
1033 return ahci_init_one(uc_priv, dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -06001034}
1035#endif
1036#endif
1037
Michal Simeke81589e2017-11-02 15:53:56 +01001038int ahci_start_ports_dm(struct udevice *dev)
Simon Glass7cf1afc2017-06-14 21:28:37 -06001039{
Simon Glass4279efc2017-06-14 21:28:38 -06001040 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -06001041
1042 return ahci_start_ports(uc_priv);
1043}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001044
Rob Herring942e3142011-07-06 16:13:36 +00001045#ifdef CONFIG_SCSI_AHCI_PLAT
Simon Glass4279efc2017-06-14 21:28:38 -06001046static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
Rob Herring942e3142011-07-06 16:13:36 +00001047{
Simon Glass4279efc2017-06-14 21:28:38 -06001048 int rc;
Rob Herring942e3142011-07-06 16:13:36 +00001049
Simon Glass225b1da2017-06-14 21:28:34 -06001050 uc_priv->host_flags = ATA_FLAG_SATA
Rob Herring942e3142011-07-06 16:13:36 +00001051 | ATA_FLAG_NO_LEGACY
1052 | ATA_FLAG_MMIO
1053 | ATA_FLAG_PIO_DMA
1054 | ATA_FLAG_NO_ATAPI;
Simon Glass225b1da2017-06-14 21:28:34 -06001055 uc_priv->pio_mask = 0x1f;
1056 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Rob Herring942e3142011-07-06 16:13:36 +00001057
Simon Glass225b1da2017-06-14 21:28:34 -06001058 uc_priv->mmio_base = base;
Rob Herring942e3142011-07-06 16:13:36 +00001059
1060 /* initialize adapter */
Simon Glass225b1da2017-06-14 21:28:34 -06001061 rc = ahci_host_init(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001062 if (rc)
1063 goto err_out;
1064
Simon Glass225b1da2017-06-14 21:28:34 -06001065 ahci_print_info(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001066
Simon Glass62b4ec82017-06-14 21:28:36 -06001067 rc = ahci_start_ports(uc_priv);
Rob Herring942e3142011-07-06 16:13:36 +00001068
Rob Herring942e3142011-07-06 16:13:36 +00001069err_out:
1070 return rc;
1071}
Ian Campbellc6f3d502014-03-07 01:20:56 +00001072
Simon Glass4279efc2017-06-14 21:28:38 -06001073#ifndef CONFIG_DM_SCSI
1074int ahci_init(void __iomem *base)
1075{
1076 struct ahci_uc_priv *uc_priv;
1077
1078 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1079 if (!probe_ent) {
1080 printf("%s: No memory for uc_priv\n", __func__);
1081 return -ENOMEM;
1082 }
1083
1084 uc_priv = probe_ent;
1085 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1086
1087 return ahci_init_common(uc_priv, base);
1088}
1089#endif
1090
1091int ahci_init_dm(struct udevice *dev, void __iomem *base)
1092{
1093 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1094
1095 return ahci_init_common(uc_priv, base);
1096}
1097
Ian Campbellc6f3d502014-03-07 01:20:56 +00001098void __weak scsi_init(void)
1099{
1100}
1101
Simon Glass4279efc2017-06-14 21:28:38 -06001102#endif /* CONFIG_SCSI_AHCI_PLAT */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001103
Marc Jones766b16f2012-10-29 05:24:02 +00001104/*
1105 * In the general case of generic rotating media it makes sense to have a
1106 * flush capability. It probably even makes sense in the case of SSDs because
1107 * one cannot always know for sure what kind of internal cache/flush mechanism
1108 * is embodied therein. At first it was planned to invoke this after the last
1109 * write to disk and before rebooting. In practice, knowing, a priori, which
1110 * is the last write is difficult. Because writing to the disk in u-boot is
1111 * very rare, this flush command will be invoked after every block write.
1112 */
Simon Glass225b1da2017-06-14 21:28:34 -06001113static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
Marc Jones766b16f2012-10-29 05:24:02 +00001114{
1115 u8 fis[20];
Simon Glass225b1da2017-06-14 21:28:34 -06001116 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantianfa313772015-07-09 14:37:30 +08001117 void __iomem *port_mmio = pp->port_mmio;
Marc Jones766b16f2012-10-29 05:24:02 +00001118 u32 cmd_fis_len = 5; /* five dwords */
1119
1120 /* Preset the FIS */
1121 memset(fis, 0, 20);
1122 fis[0] = 0x27; /* Host to device FIS. */
1123 fis[1] = 1 << 7; /* Command FIS. */
Walter Murphyfe1f8082012-10-29 05:24:03 +00001124 fis[2] = ATA_CMD_FLUSH_EXT;
Marc Jones766b16f2012-10-29 05:24:02 +00001125
1126 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1127 ahci_fill_cmd_slot(pp, cmd_fis_len);
Tang Yuantian75e14b12016-04-14 16:21:00 +08001128 ahci_dcache_flush_sata_cmd(pp);
Marc Jones766b16f2012-10-29 05:24:02 +00001129 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1130
1131 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1132 WAIT_MS_FLUSH, 0x1)) {
1133 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1134 return -EIO;
1135 }
1136
1137 return 0;
1138}
1139
Simon Glass4e749012017-06-14 21:28:42 -06001140static int ahci_scsi_bus_reset(struct udevice *dev)
1141{
1142 /* Not implemented */
1143
1144 return 0;
1145}
1146
Simon Glassf6ab5a92017-06-14 21:28:43 -06001147#ifdef CONFIG_DM_SCSI
Simon Glass681357f2017-06-14 21:28:46 -06001148int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1149{
1150 struct udevice *dev;
1151 int ret;
1152
1153 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1154 if (ret)
1155 return ret;
1156 *devp = dev;
1157
1158 return 0;
1159}
1160
Simon Glass745a94f2017-07-04 13:31:18 -06001161int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
Simon Glass681357f2017-06-14 21:28:46 -06001162{
Simon Glass681357f2017-06-14 21:28:46 -06001163 struct ahci_uc_priv *uc_priv;
1164 struct scsi_platdata *uc_plat;
1165 struct udevice *dev;
1166 int ret;
1167
1168 device_find_first_child(ahci_dev, &dev);
1169 if (!dev)
1170 return -ENODEV;
1171 uc_plat = dev_get_uclass_platdata(dev);
Simon Glass745a94f2017-07-04 13:31:18 -06001172 uc_plat->base = base;
Simon Glass681357f2017-06-14 21:28:46 -06001173 uc_plat->max_lun = 1;
1174 uc_plat->max_id = 2;
Simon Glass745a94f2017-07-04 13:31:18 -06001175
1176 uc_priv = dev_get_uclass_priv(ahci_dev);
Simon Glass681357f2017-06-14 21:28:46 -06001177 ret = ahci_init_one(uc_priv, dev);
1178 if (ret)
1179 return ret;
1180 ret = ahci_start_ports(uc_priv);
1181 if (ret)
1182 return ret;
Simon Glass681357f2017-06-14 21:28:46 -06001183
1184 return 0;
1185}
1186
Simon Glass745a94f2017-07-04 13:31:18 -06001187#ifdef CONFIG_DM_PCI
1188int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1189{
1190 ulong base;
1191
1192 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1193 PCI_REGION_MEM);
1194
1195 return ahci_probe_scsi(ahci_dev, base);
1196}
1197#endif
1198
Simon Glassf6ab5a92017-06-14 21:28:43 -06001199struct scsi_ops scsi_ops = {
1200 .exec = ahci_scsi_exec,
1201 .bus_reset = ahci_scsi_bus_reset,
1202};
Simon Glass681357f2017-06-14 21:28:46 -06001203
1204U_BOOT_DRIVER(ahci_scsi) = {
1205 .name = "ahci_scsi",
1206 .id = UCLASS_SCSI,
1207 .ops = &scsi_ops,
1208};
Simon Glassf6ab5a92017-06-14 21:28:43 -06001209#else
Simon Glass4e749012017-06-14 21:28:42 -06001210int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1211{
1212 return ahci_scsi_exec(dev, pccb);
1213}
Marc Jones766b16f2012-10-29 05:24:02 +00001214
Simon Glass4682c8a2017-06-14 21:28:40 -06001215__weak int scsi_bus_reset(struct udevice *dev)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001216{
Simon Glass4e749012017-06-14 21:28:42 -06001217 return ahci_scsi_bus_reset(dev);
Simon Glass4682c8a2017-06-14 21:28:40 -06001218
1219 return 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001220}
Simon Glassf6ab5a92017-06-14 21:28:43 -06001221#endif