Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
| 3 | * Author: Jason Jin<Jason.jin@freescale.com> |
| 4 | * Zhang Wei<wei.zhang@freescale.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | * |
| 24 | * with the reference on libata and ahci drvier in kernel |
| 25 | * |
| 26 | */ |
| 27 | #include <common.h> |
| 28 | |
| 29 | #ifdef CONFIG_SCSI_AHCI |
| 30 | |
| 31 | #include <command.h> |
| 32 | #include <pci.h> |
| 33 | #include <asm/processor.h> |
| 34 | #include <asm/errno.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <malloc.h> |
| 37 | #include <scsi.h> |
| 38 | #include <ata.h> |
| 39 | #include <linux/ctype.h> |
| 40 | #include <ahci.h> |
| 41 | |
| 42 | struct ahci_probe_ent *probe_ent = NULL; |
| 43 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; |
| 44 | |
| 45 | #define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) |
| 46 | |
| 47 | static inline u32 ahci_port_base(u32 base, u32 port) |
| 48 | { |
| 49 | return base + 0x100 + (port * 0x80); |
| 50 | } |
| 51 | |
| 52 | |
| 53 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, |
| 54 | unsigned int port_idx) |
| 55 | { |
| 56 | base = ahci_port_base(base, port_idx); |
| 57 | |
| 58 | port->cmd_addr = base; |
| 59 | port->scr_addr = base + PORT_SCR; |
| 60 | } |
| 61 | |
| 62 | |
| 63 | #define msleep(a) udelay(a * 1000) |
| 64 | #define ssleep(a) msleep(a * 1000) |
| 65 | static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) |
| 66 | { |
| 67 | int i; |
| 68 | u32 status; |
| 69 | for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) |
| 70 | msleep(1); |
| 71 | |
| 72 | return (i < timeout_msec)? 0 : -1; |
| 73 | } |
| 74 | |
| 75 | |
| 76 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) |
| 77 | { |
| 78 | pci_dev_t pdev = probe_ent->dev; |
| 79 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
| 80 | u32 tmp, cap_save; |
| 81 | u16 tmp16; |
| 82 | int i, j; |
| 83 | volatile u8* port_mmio; |
| 84 | unsigned short vendor; |
| 85 | |
| 86 | cap_save = readl(mmio + HOST_CAP); |
| 87 | cap_save &= ( (1<<28) | (1<<17) ); |
| 88 | cap_save |= (1 << 27); |
| 89 | |
| 90 | /* global controller reset */ |
| 91 | tmp = readl(mmio + HOST_CTL); |
| 92 | if ((tmp & HOST_RESET) == 0) |
| 93 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); |
| 94 | |
| 95 | /* reset must complete within 1 second, or |
| 96 | * the hardware should be considered fried. |
| 97 | */ |
| 98 | ssleep(1); |
| 99 | |
| 100 | tmp = readl(mmio + HOST_CTL); |
| 101 | if (tmp & HOST_RESET) { |
| 102 | debug("controller reset failed (0x%x)\n", tmp); |
| 103 | return -1; |
| 104 | } |
| 105 | |
| 106 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); |
| 107 | writel(cap_save, mmio + HOST_CAP); |
| 108 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); |
| 109 | |
| 110 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
| 111 | |
| 112 | if (vendor == PCI_VENDOR_ID_INTEL) { |
| 113 | u16 tmp16; |
| 114 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 115 | tmp16 |= 0xf; |
| 116 | pci_write_config_word(pdev, 0x92, tmp16); |
| 117 | } |
| 118 | |
| 119 | probe_ent->cap = readl(mmio + HOST_CAP); |
| 120 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); |
| 121 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; |
| 122 | |
| 123 | debug("cap 0x%x port_map 0x%x n_ports %d\n", |
| 124 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
| 125 | |
| 126 | for (i = 0; i < probe_ent->n_ports; i++) { |
| 127 | probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); |
| 128 | port_mmio = (u8 *)probe_ent->port[i].port_mmio; |
| 129 | ahci_setup_port(&probe_ent->port[i], |
| 130 | (unsigned long) mmio, i); |
| 131 | |
| 132 | /* make sure port is not active */ |
| 133 | tmp = readl(port_mmio + PORT_CMD); |
| 134 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 135 | PORT_CMD_FIS_RX | PORT_CMD_START)) { |
| 136 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 137 | PORT_CMD_FIS_RX | PORT_CMD_START); |
| 138 | writel_with_flush(tmp, port_mmio + PORT_CMD); |
| 139 | |
| 140 | /* spec says 500 msecs for each bit, so |
| 141 | * this is slightly incorrect. |
| 142 | */ |
| 143 | msleep(500); |
| 144 | } |
| 145 | |
| 146 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); |
| 147 | |
| 148 | j = 0; |
| 149 | while (j < 100) { |
| 150 | msleep(10); |
| 151 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 152 | if ((tmp & 0xf) == 0x3) |
| 153 | break; |
| 154 | j++; |
| 155 | } |
| 156 | |
| 157 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 158 | debug("PORT_SCR_ERR 0x%x\n", tmp); |
| 159 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 160 | |
| 161 | /* ack any pending irq events for this port */ |
| 162 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 163 | debug("PORT_IRQ_STAT 0x%x\n", tmp); |
| 164 | if (tmp) |
| 165 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 166 | |
| 167 | writel(1 << i, mmio + HOST_IRQ_STAT); |
| 168 | |
| 169 | /* set irq mask (enables interrupts) */ |
| 170 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 171 | |
| 172 | /*register linkup ports*/ |
| 173 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 174 | debug("Port %d status: 0x%x\n",i,tmp); |
| 175 | if((tmp & 0xf) == 0x03) |
| 176 | probe_ent->link_port_map |= (0x01<< i); |
| 177 | } |
| 178 | |
| 179 | tmp = readl(mmio + HOST_CTL); |
| 180 | debug("HOST_CTL 0x%x\n", tmp); |
| 181 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 182 | tmp = readl(mmio + HOST_CTL); |
| 183 | debug("HOST_CTL 0x%x\n", tmp); |
| 184 | |
| 185 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
| 186 | tmp |= PCI_COMMAND_MASTER; |
| 187 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | |
| 193 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) |
| 194 | { |
| 195 | pci_dev_t pdev = probe_ent->dev; |
| 196 | volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; |
| 197 | u32 vers, cap, impl, speed; |
| 198 | const char *speed_s; |
| 199 | u16 cc; |
| 200 | const char *scc_s; |
| 201 | |
| 202 | vers = readl(mmio + HOST_VERSION); |
| 203 | cap = probe_ent->cap; |
| 204 | impl = probe_ent->port_map; |
| 205 | |
| 206 | speed = (cap >> 20) & 0xf; |
| 207 | if (speed == 1) |
| 208 | speed_s = "1.5"; |
| 209 | else if (speed == 2) |
| 210 | speed_s = "3"; |
| 211 | else |
| 212 | speed_s = "?"; |
| 213 | |
| 214 | pci_read_config_word(pdev, 0x0a, &cc); |
| 215 | if (cc == 0x0101) |
| 216 | scc_s = "IDE"; |
| 217 | else if (cc == 0x0106) |
| 218 | scc_s = "SATA"; |
| 219 | else if (cc == 0x0104) |
| 220 | scc_s = "RAID"; |
| 221 | else |
| 222 | scc_s = "unknown"; |
| 223 | |
| 224 | printf( "AHCI %02x%02x.%02x%02x " |
| 225 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 226 | , |
| 227 | |
| 228 | (vers >> 24) & 0xff, |
| 229 | (vers >> 16) & 0xff, |
| 230 | (vers >> 8) & 0xff, |
| 231 | vers & 0xff, |
| 232 | |
| 233 | ((cap >> 8) & 0x1f) + 1, |
| 234 | (cap & 0x1f) + 1, |
| 235 | speed_s, |
| 236 | impl, |
| 237 | scc_s); |
| 238 | |
| 239 | printf("flags: " |
| 240 | "%s%s%s%s%s%s" |
| 241 | "%s%s%s%s%s%s%s\n" |
| 242 | , |
| 243 | |
| 244 | cap & (1 << 31) ? "64bit " : "", |
| 245 | cap & (1 << 30) ? "ncq " : "", |
| 246 | cap & (1 << 28) ? "ilck " : "", |
| 247 | cap & (1 << 27) ? "stag " : "", |
| 248 | cap & (1 << 26) ? "pm " : "", |
| 249 | cap & (1 << 25) ? "led " : "", |
| 250 | |
| 251 | cap & (1 << 24) ? "clo " : "", |
| 252 | cap & (1 << 19) ? "nz " : "", |
| 253 | cap & (1 << 18) ? "only " : "", |
| 254 | cap & (1 << 17) ? "pmp " : "", |
| 255 | cap & (1 << 15) ? "pio " : "", |
| 256 | cap & (1 << 14) ? "slum " : "", |
| 257 | cap & (1 << 13) ? "part " : "" |
| 258 | ); |
| 259 | } |
| 260 | |
| 261 | |
| 262 | static int ahci_init_one (pci_dev_t pdev) |
| 263 | { |
| 264 | u32 iobase, vendor; |
| 265 | int rc; |
| 266 | |
| 267 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
| 268 | |
| 269 | probe_ent = malloc(sizeof(probe_ent)); |
| 270 | memset(probe_ent, 0, sizeof(probe_ent)); |
| 271 | probe_ent->dev = pdev; |
| 272 | |
| 273 | pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); |
| 274 | iobase &= ~0xf; |
| 275 | |
| 276 | probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
| 277 | | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
| 278 | | ATA_FLAG_NO_ATAPI; |
| 279 | probe_ent->pio_mask = 0x1f; |
| 280 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ |
| 281 | |
| 282 | probe_ent->mmio_base = iobase; |
| 283 | |
| 284 | /* Take from kernel: |
| 285 | * JMicron-specific fixup: |
| 286 | * make sure we're in AHCI mode |
| 287 | */ |
| 288 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
| 289 | if(vendor == 0x197b) |
| 290 | pci_write_config_byte(pdev, 0x41, 0xa1); |
| 291 | |
| 292 | /* initialize adapter */ |
| 293 | rc = ahci_host_init(probe_ent); |
| 294 | if (rc) |
| 295 | goto err_out; |
| 296 | |
| 297 | ahci_print_info(probe_ent); |
| 298 | |
| 299 | return 0; |
| 300 | |
| 301 | err_out: |
| 302 | return rc; |
| 303 | } |
| 304 | |
| 305 | |
| 306 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) |
| 307 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
| 308 | { |
| 309 | |
| 310 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 311 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; |
| 312 | u32 sg_count; |
| 313 | int i; |
| 314 | |
| 315 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; |
| 316 | if(sg_count > AHCI_MAX_SG){ |
| 317 | printf("Error:Too much sg!\n"); |
| 318 | return -1; |
| 319 | } |
| 320 | |
| 321 | for(i = 0;i < sg_count; i++) |
| 322 | { |
| 323 | ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); |
| 324 | ahci_sg->addr_hi = 0; |
| 325 | ahci_sg->flags_size = cpu_to_le32( 0x3fffff & |
| 326 | (buf_len < MAX_DATA_BYTE_COUNT |
| 327 | ? (buf_len - 1) |
| 328 | : (MAX_DATA_BYTE_COUNT - 1))); |
| 329 | ahci_sg++; |
| 330 | buf_len -= MAX_DATA_BYTE_COUNT; |
| 331 | } |
| 332 | |
| 333 | return sg_count; |
| 334 | } |
| 335 | |
| 336 | |
| 337 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) |
| 338 | { |
| 339 | pp->cmd_slot->opts = cpu_to_le32(opts); |
| 340 | pp->cmd_slot->status = 0; |
| 341 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); |
| 342 | pp->cmd_slot->tbl_addr_hi = 0; |
| 343 | } |
| 344 | |
| 345 | |
| 346 | static void ahci_set_feature(u8 port) |
| 347 | { |
| 348 | |
| 349 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 350 | volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; |
| 351 | u32 cmd_fis_len = 5; /* five dwords */ |
| 352 | u8 fis[20]; |
| 353 | |
| 354 | /*set feature*/ |
| 355 | memset(fis,0,20); |
| 356 | fis[0] = 0x27; |
| 357 | fis[1] = 1 << 7; |
| 358 | fis[2] = ATA_CMD_SETF; |
| 359 | fis[3] = SETFEATURES_XFER; |
| 360 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; |
| 361 | |
| 362 | memcpy((unsigned char *)pp->cmd_tbl,fis,20); |
| 363 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
| 364 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 365 | readl(port_mmio + PORT_CMD_ISSUE); |
| 366 | |
| 367 | if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
| 368 | printf("set feature error!\n"); |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | |
| 373 | static int ahci_port_start(u8 port) |
| 374 | { |
| 375 | |
| 376 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 377 | volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; |
| 378 | u32 port_status; |
| 379 | u32 mem; |
| 380 | |
| 381 | debug("Enter start port: %d\n",port); |
| 382 | port_status = readl(port_mmio + PORT_SCR_STAT); |
| 383 | debug("Port %d status: %x\n",port,port_status); |
| 384 | if((port_status & 0xf) != 0x03){ |
| 385 | printf("No Link on this port!\n"); |
| 386 | return -1; |
| 387 | } |
| 388 | |
| 389 | mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
| 390 | if (!mem) { |
| 391 | free(pp); |
| 392 | printf("No mem for table!\n"); |
| 393 | return -ENOMEM; |
| 394 | } |
| 395 | |
| 396 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
| 397 | |
| 398 | memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 399 | /* |
| 400 | * First item in chunk of DMA memory: 32-slot command table, |
| 401 | * 32 bytes each in size |
| 402 | */ |
| 403 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; |
| 404 | debug("cmd_slot = 0x%x\n",pp->cmd_slot); |
| 405 | |
| 406 | mem += (AHCI_CMD_SLOT_SZ + 224); |
| 407 | /* |
| 408 | * Second item: Received-FIS area |
| 409 | */ |
| 410 | pp->rx_fis = mem; |
| 411 | |
| 412 | mem += AHCI_RX_FIS_SZ; |
| 413 | /* |
| 414 | * Third item: data area for storing a single command |
| 415 | * and its scatter-gather table |
| 416 | */ |
| 417 | pp->cmd_tbl = mem; |
| 418 | debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); |
| 419 | |
| 420 | mem += AHCI_CMD_TBL_HDR; |
| 421 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; |
| 422 | |
| 423 | writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
| 424 | |
| 425 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); |
| 426 | |
| 427 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 428 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
| 429 | PORT_CMD_START, port_mmio + PORT_CMD); |
| 430 | |
| 431 | debug("Exit start port %d\n",port); |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | |
| 437 | static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) |
| 438 | { |
| 439 | |
| 440 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 441 | volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; |
| 442 | u32 opts; |
| 443 | u32 port_status; |
| 444 | int sg_count; |
| 445 | |
| 446 | debug("Enter get_ahci_device_data: for port %d\n",port); |
| 447 | |
| 448 | if(port > probe_ent->n_ports){ |
| 449 | printf("Invaild port number %d\n", port); |
| 450 | return -1; |
| 451 | } |
| 452 | |
| 453 | port_status = readl(port_mmio + PORT_SCR_STAT); |
| 454 | if((port_status & 0xf) != 0x03){ |
| 455 | debug("No Link on port %d!\n",port); |
| 456 | return -1; |
| 457 | } |
| 458 | |
| 459 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); |
| 460 | |
| 461 | sg_count = ahci_fill_sg(port,buf,buf_len); |
| 462 | opts = (fis_len >> 2) | (sg_count << 16) ; |
| 463 | ahci_fill_cmd_slot(pp, opts); |
| 464 | |
| 465 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
| 466 | |
| 467 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
| 468 | printf("timeout exit!\n"); |
| 469 | return -1; |
| 470 | } |
| 471 | debug("get_ahci_device_data: %d byte transferred.\n", |
| 472 | pp->cmd_slot->status); |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | |
| 478 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) |
| 479 | { |
| 480 | int i; |
| 481 | for(i = 0; i < len / 2; i++) |
| 482 | target[i] = le16_to_cpu(src[i]); |
| 483 | return (char *)target; |
| 484 | } |
| 485 | |
| 486 | |
| 487 | static void dump_ataid(hd_driveid_t *ataid) |
| 488 | { |
| 489 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); |
| 490 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); |
| 491 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); |
| 492 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); |
| 493 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); |
| 494 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); |
| 495 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); |
| 496 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); |
| 497 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); |
| 498 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); |
| 499 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); |
| 500 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); |
| 501 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); |
| 502 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); |
| 503 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); |
| 504 | } |
| 505 | |
| 506 | /* |
| 507 | * SCSI INQUIRY command operation. |
| 508 | */ |
| 509 | static int ata_scsiop_inquiry(ccb *pccb) |
| 510 | { |
| 511 | u8 hdr[] = { |
| 512 | 0, |
| 513 | 0, |
| 514 | 0x5, /* claim SPC-3 version compatibility */ |
| 515 | 2, |
| 516 | 95 - 4, |
| 517 | }; |
| 518 | u8 fis[20]; |
| 519 | u8 *tmpid; |
| 520 | u8 port; |
| 521 | |
| 522 | /* Clean ccb data buffer */ |
| 523 | memset(pccb->pdata, 0, pccb->datalen); |
| 524 | |
| 525 | memcpy(pccb->pdata, hdr, sizeof(hdr)); |
| 526 | |
| 527 | if(pccb->datalen <= 35) |
| 528 | return 0; |
| 529 | |
| 530 | memset(fis, 0, 20); |
| 531 | /* Construct the FIS */ |
| 532 | fis[0] = 0x27; /* Host to device FIS. */ |
| 533 | fis[1] = 1 << 7; /* Command FIS. */ |
| 534 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ |
| 535 | |
| 536 | /* Read id from sata */ |
| 537 | port = pccb->target; |
| 538 | if(!(tmpid = malloc(sizeof(hd_driveid_t)))) |
| 539 | return -ENOMEM; |
| 540 | |
| 541 | if(get_ahci_device_data(port, (u8 *)&fis, 20, |
| 542 | tmpid, sizeof(hd_driveid_t))){ |
| 543 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
| 544 | return -EIO; |
| 545 | } |
| 546 | |
| 547 | if(ataid[port]) |
| 548 | free(ataid[port]); |
| 549 | ataid[port] = (hd_driveid_t *)tmpid; |
| 550 | |
| 551 | memcpy(&pccb->pdata[8], "ATA ", 8); |
| 552 | ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
| 553 | ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); |
| 554 | |
| 555 | dump_ataid(ataid[port]); |
| 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | |
| 560 | /* |
| 561 | * SCSI READ10 command operation. |
| 562 | */ |
| 563 | static int ata_scsiop_read10(ccb *pccb) |
| 564 | { |
| 565 | u64 lba = 0; |
| 566 | u32 len = 0; |
| 567 | u8 fis[20]; |
| 568 | |
| 569 | lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) |
| 570 | | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); |
| 571 | len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); |
| 572 | |
| 573 | /* For 10-byte and 16-byte SCSI R/W commands, transfer |
| 574 | * length 0 means transfer 0 block of data. |
| 575 | * However, for ATA R/W commands, sector count 0 means |
| 576 | * 256 or 65536 sectors, not 0 sectors as in SCSI. |
| 577 | * |
| 578 | * WARNING: one or two older ATA drives treat 0 as 0... |
| 579 | */ |
| 580 | if(!len) return 0; |
| 581 | memset(fis, 0, 20); |
| 582 | |
| 583 | /* Construct the FIS */ |
| 584 | fis[0] = 0x27; /* Host to device FIS. */ |
| 585 | fis[1] = 1 << 7; /* Command FIS. */ |
| 586 | fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ |
| 587 | |
| 588 | /* LBA address, only support LBA28 in this driver*/ |
| 589 | fis[4] = pccb->cmd[5]; |
| 590 | fis[5] = pccb->cmd[4]; |
| 591 | fis[6] = pccb->cmd[3]; |
| 592 | fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; |
| 593 | |
| 594 | /* Sector Count */ |
| 595 | fis[12] = pccb->cmd[8]; |
| 596 | fis[13] = pccb->cmd[7]; |
| 597 | |
| 598 | /* Read from ahci */ |
| 599 | if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, |
| 600 | pccb->pdata, pccb->datalen)){ |
| 601 | debug("scsi_ahci: SCSI READ10 command failure.\n"); |
| 602 | return -EIO; |
| 603 | } |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | |
| 609 | /* |
| 610 | * SCSI READ CAPACITY10 command operation. |
| 611 | */ |
| 612 | static int ata_scsiop_read_capacity10(ccb *pccb) |
| 613 | { |
| 614 | u8 buf[8]; |
| 615 | |
| 616 | if(!ataid[pccb->target]) { |
| 617 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
| 618 | "\tNo ATA info!\n" |
| 619 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); |
| 620 | return -EPERM; |
| 621 | } |
| 622 | |
| 623 | memset(buf, 0, 8); |
| 624 | |
| 625 | *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); |
| 626 | |
| 627 | buf[6] = 512 >> 8; |
| 628 | buf[7] = 512 & 0xff; |
| 629 | |
| 630 | memcpy(pccb->pdata, buf, 8); |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | |
| 636 | /* |
| 637 | * SCSI TEST UNIT READY command operation. |
| 638 | */ |
| 639 | static int ata_scsiop_test_unit_ready(ccb *pccb) |
| 640 | { |
| 641 | return (ataid[pccb->target]) ? 0 : -EPERM; |
| 642 | } |
| 643 | |
| 644 | int scsi_exec(ccb *pccb) |
| 645 | { |
| 646 | int ret; |
| 647 | |
| 648 | switch(pccb->cmd[0]) { |
| 649 | case SCSI_READ10: |
| 650 | ret = ata_scsiop_read10(pccb); |
| 651 | break; |
| 652 | case SCSI_RD_CAPAC: |
| 653 | ret = ata_scsiop_read_capacity10(pccb); |
| 654 | break; |
| 655 | case SCSI_TST_U_RDY: |
| 656 | ret = ata_scsiop_test_unit_ready(pccb); |
| 657 | break; |
| 658 | case SCSI_INQUIRY: |
| 659 | ret = ata_scsiop_inquiry(pccb); |
| 660 | break; |
| 661 | default: |
| 662 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); |
| 663 | return FALSE; |
| 664 | } |
| 665 | |
| 666 | if(ret) { |
| 667 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); |
| 668 | return FALSE; |
| 669 | } |
| 670 | return TRUE; |
| 671 | |
| 672 | } |
| 673 | |
| 674 | |
| 675 | void scsi_low_level_init(int busdevfunc) |
| 676 | { |
| 677 | int i; |
| 678 | u32 linkmap; |
| 679 | |
| 680 | ahci_init_one(busdevfunc); |
| 681 | |
| 682 | linkmap = probe_ent->link_port_map; |
| 683 | |
| 684 | for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ |
| 685 | if( ((linkmap >> i) & 0x01) ){ |
| 686 | if(ahci_port_start((u8)i)){ |
| 687 | printf("Can not start port %d\n",i); |
| 688 | continue; |
| 689 | } |
| 690 | ahci_set_feature((u8)i); |
| 691 | } |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | |
| 696 | void scsi_bus_reset(void) |
| 697 | { |
| 698 | /*Not implement*/ |
| 699 | } |
| 700 | |
| 701 | |
| 702 | void scsi_print_error(ccb *pccb) |
| 703 | { |
| 704 | /*The ahci error info can be read in the ahci driver*/ |
| 705 | } |
| 706 | #endif |