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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
wdenk7a8e9bed2003-05-31 18:35:21 +000030 * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
31 */
32
33/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020034 !! !!
wdenk7a8e9bed2003-05-31 18:35:21 +000035 !! This configuration requires JP3 to be in position 1-2 to work !!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020036 !! To make it work for the default, the TEXT_BASE define in !!
wdenk7a8e9bed2003-05-31 18:35:21 +000037 !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
38 !! 0xfff00000 !!
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020040 !! !!
wdenk8bde7f72003-06-27 21:31:46 +000041 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
wdenkdb2f721f2003-03-06 00:58:30 +000042 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
47/*
48 * High Level Configuration Options
49 * (easy to change)
50 */
51
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
53#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050054#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkdb2f721f2003-03-06 00:58:30 +000055
wdenkc837dcb2004-01-20 23:12:12 +000056#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenkdb2f721f2003-03-06 00:58:30 +000057
58/* allow serial and ethaddr to be overwritten */
59#define CONFIG_ENV_OVERWRITE
60
61/*
62 * select serial console configuration
63 *
64 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
65 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
66 * for SCC).
67 *
68 * if CONFIG_CONS_NONE is defined, then the serial console routines must
69 * defined elsewhere (for example, on the cogent platform, there are serial
70 * ports on the motherboard which are used for the serial console - see
71 * cogent/cma101/serial.[ch]).
72 */
73#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
74#define CONFIG_CONS_ON_SCC /* define if console on SCC */
75#undef CONFIG_CONS_NONE /* define if console on something else */
76#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
77
78/*
79 * select ethernet configuration
80 *
81 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
82 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
83 * for FCC)
84 *
85 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050086 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkdb2f721f2003-03-06 00:58:30 +000087 */
88#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
89#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
90#undef CONFIG_ETHER_NONE /* define if ether on something else */
91#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk5d232d02003-05-22 22:52:13 +000092#define CONFIG_MII /* MII PHY management */
93#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
94/*
95 * Port pins used for bit-banged MII communictions (if applicable).
96 */
97#define MDIO_PORT 2 /* Port C */
98#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
99#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
100#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
101
102#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
103 else iop->pdat &= ~0x00400000
104
105#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
106 else iop->pdat &= ~0x00200000
107
108#define MIIDELAY udelay(1)
wdenkdb2f721f2003-03-06 00:58:30 +0000109
110#if (CONFIG_ETHER_INDEX == 2)
111
112/*
113 * - Rx-CLK is CLK13
114 * - Tx-CLK is CLK14
115 * - Select bus for bd/buffers (see 28-13)
116 * - Half duplex
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
119# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
120# define CONFIG_SYS_CPMFCR_RAMTYPE 0
121# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkdb2f721f2003-03-06 00:58:30 +0000122
123#endif /* CONFIG_ETHER_INDEX */
124
125/* other options */
126#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
128#define CONFIG_SYS_I2C_SLAVE 0x7F
129#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkdb2f721f2003-03-06 00:58:30 +0000130
wdenk5d232d02003-05-22 22:52:13 +0000131/* PCI */
132#define CONFIG_PCI
133#define CONFIG_PCI_PNP
134#define CONFIG_PCI_BOOTDELAY 0
135#undef CONFIG_PCI_SCAN_SHOW
136
wdenkdb2f721f2003-03-06 00:58:30 +0000137/*-----------------------------------------------------------------------
138 * Definitions for Serial Presence Detect EEPROM address
139 * (to get SDRAM settings)
140 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200141#define SPD_EEPROM_ADDRESS 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000142
wdenk5d232d02003-05-22 22:52:13 +0000143#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000144#define CONFIG_BAUDRATE 115200
145
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500146/*
147 * Command line configuration.
148 */
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500149#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500150
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500151/* Commands we want, that are not part of default set */
152#define CONFIG_CMD_ASKENV /* ask for env variable */
153#define CONFIG_CMD_CACHE /* icache, dcache */
154#define CONFIG_CMD_DHCP /* DHCP Support */
155#define CONFIG_CMD_DIAG /* Diagnostics */
156#define CONFIG_CMD_IMMAP /* IMMR dump support */
157#define CONFIG_CMD_IRQ /* irqinfo */
158#define CONFIG_CMD_MII /* MII support */
159#define CONFIG_CMD_PCI /* pciinfo */
160#define CONFIG_CMD_PING /* ping support */
161#define CONFIG_CMD_PORTIO /* Port I/O */
162#define CONFIG_CMD_REGINFO /* Register dump */
163#define CONFIG_CMD_SAVES /* save S record dump */
164#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
165
166/* Commands from default set we don't need */
167#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
168#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
wdenkdb2f721f2003-03-06 00:58:30 +0000169
wdenk5d232d02003-05-22 22:52:13 +0000170/* Define a command string that is automatically executed when no character
171 * is read on the console interface withing "Boot Delay" after reset.
172 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200173#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
174#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk5d232d02003-05-22 22:52:13 +0000175
wdenk42dfe7a2004-03-14 22:25:36 +0000176#ifdef CONFIG_BOOT_ROOT_INITRD
wdenk5d232d02003-05-22 22:52:13 +0000177#define CONFIG_BOOTCOMMAND \
178 "version;" \
179 "echo;" \
180 "bootp;" \
181 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100182 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000183 "bootm"
184#endif /* CONFIG_BOOT_ROOT_INITRD */
185
wdenk42dfe7a2004-03-14 22:25:36 +0000186#ifdef CONFIG_BOOT_ROOT_NFS
wdenk5d232d02003-05-22 22:52:13 +0000187#define CONFIG_BOOTCOMMAND \
188 "version;" \
189 "echo;" \
190 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100191 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
192 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000193 "bootm"
194#endif /* CONFIG_BOOT_ROOT_NFS */
195
Jon Loeliger7be044e2007-07-09 21:24:19 -0500196/*
197 * BOOTP options
wdenk5d232d02003-05-22 22:52:13 +0000198 */
Jon Loeliger7be044e2007-07-09 21:24:19 -0500199#define CONFIG_BOOTP_SUBNETMASK
200#define CONFIG_BOOTP_GATEWAY
201#define CONFIG_BOOTP_HOSTNAME
202#define CONFIG_BOOTP_BOOTPATH
203#define CONFIG_BOOTP_BOOTFILESIZE
204#define CONFIG_BOOTP_DNS
wdenk5d232d02003-05-22 22:52:13 +0000205
wdenkdb2f721f2003-03-06 00:58:30 +0000206#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkdb2f721f2003-03-06 00:58:30 +0000207
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500208#if defined(CONFIG_CMD_KGDB)
wdenkdb2f721f2003-03-06 00:58:30 +0000209#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
210#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
211#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
212#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
213#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
214#endif
215
216#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
217
218/*
219 * Miscellaneous configurable options
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_LONGHELP /* undef to save memory */
222#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500223#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000227#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
229#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
230#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
233#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkdb2f721f2003-03-06 00:58:30 +0000234
wdenk5d232d02003-05-22 22:52:13 +0000235#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
wdenkdb2f721f2003-03-06 00:58:30 +0000236 /* for versions < 2.4.5-pre5 */
237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkdb2f721f2003-03-06 00:58:30 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdb2f721f2003-03-06 00:58:30 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_BASE 0xFE000000
wdenk5d232d02003-05-22 22:52:13 +0000245#define FLASH_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
247#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
248#define CONFIG_SYS_FLASH_SIZE 8
249#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
250#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
wdenkdb2f721f2003-03-06 00:58:30 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#undef CONFIG_SYS_FLASH_CHECKSUM
wdenkdb2f721f2003-03-06 00:58:30 +0000253
254/* this is stuff came out of the Motorola docs */
255/* Only change this if you also change the Hardware configuration Word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenkdb2f721f2003-03-06 00:58:30 +0000257
wdenkdb2f721f2003-03-06 00:58:30 +0000258/* Set IMMR to 0xF0000000 or above to boot Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_IMMR 0xF0000000
260#define CONFIG_SYS_BCSR 0xF8000000
261#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
wdenkdb2f721f2003-03-06 00:58:30 +0000262
263/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
264 */
265/*#define CONFIG_VERY_BIG_RAM 1*/
266
267/* What should be the base address of SDRAM DIMM and how big is
268 * it (in Mbytes)? This will normally auto-configure via the SPD.
269*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SDRAM_BASE 0x00000000
271#define CONFIG_SYS_SDRAM_SIZE 16
wdenkdb2f721f2003-03-06 00:58:30 +0000272
273#define SDRAM_SPD_ADDR 0x50
274
wdenkdb2f721f2003-03-06 00:58:30 +0000275/*-----------------------------------------------------------------------
276 * BR2,BR3 - Base Register
277 * Ref: Section 10.3.1 on page 10-14
278 * OR2,OR3 - Option Register
279 * Ref: Section 10.3.2 on page 10-16
280 *-----------------------------------------------------------------------
281 */
282
283/* Bank 2,3 - SDRAM DIMM
284 */
285
286/* The BR2 is configured as follows:
287 *
288 * - Base address of 0x00000000
289 * - 64 bit port size (60x bus only)
290 * - Data errors checking is disabled
291 * - Read and write access
292 * - SDRAM 60x bus
293 * - Access are handled by the memory controller according to MSEL
294 * - Not used for atomic operations
295 * - No data pipelining is done
296 * - Valid
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000299 BRx_PS_64 |\
300 BRx_MS_SDRAM_P |\
301 BRx_V)
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000304 BRx_PS_64 |\
305 BRx_MS_SDRAM_P |\
306 BRx_V)
307
308/* With a 64 MB DIMM, the OR2 is configured as follows:
309 *
310 * - 64 MB
311 * - 4 internal banks per device
312 * - Row start address bit is A8 with PSDMR[PBI] = 0
313 * - 12 row address lines
314 * - Back-to-back page mode
315 * - Internal bank interleaving within save device enabled
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#if (CONFIG_SYS_SDRAM_SIZE == 64)
318#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000319 ORxS_BPD_4 |\
320 ORxS_ROWST_PBI0_A8 |\
321 ORxS_NUMR_12)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#elif (CONFIG_SYS_SDRAM_SIZE == 16)
323#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
wdenkdb2f721f2003-03-06 00:58:30 +0000324#else
325#error "INVALID SDRAM CONFIGURATION"
326#endif
327
328/*-----------------------------------------------------------------------
329 * PSDMR - 60x Bus SDRAM Mode Register
330 * Ref: Section 10.3.3 on page 10-21
331 *-----------------------------------------------------------------------
332 */
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#if (CONFIG_SYS_SDRAM_SIZE == 64)
wdenkdb2f721f2003-03-06 00:58:30 +0000335/* With a 64 MB DIMM, the PSDMR is configured as follows:
336 *
337 * - Bank Based Interleaving,
338 * - Refresh Enable,
339 * - Address Multiplexing where A5 is output on A14 pin
340 * (A6 on A15, and so on),
341 * - use address pins A14-A16 as bank select,
342 * - A9 is output on SDA10 during an ACTIVATE command,
343 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
344 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
345 * is 3 clocks,
346 * - earliest timing for READ/WRITE command after ACTIVATE command is
347 * 2 clocks,
348 * - earliest timing for PRECHARGE after last data was read is 1 clock,
349 * - earliest timing for PRECHARGE after last data was written is 1 clock,
350 * - CAS Latency is 2.
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkdb2f721f2003-03-06 00:58:30 +0000353 PSDMR_SDAM_A14_IS_A5 |\
354 PSDMR_BSMA_A14_A16 |\
355 PSDMR_SDA10_PBI0_A9 |\
356 PSDMR_RFRC_7_CLK |\
357 PSDMR_PRETOACT_3W |\
358 PSDMR_ACTTORW_2W |\
359 PSDMR_LDOTOPRE_1C |\
360 PSDMR_WRC_1C |\
361 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#elif (CONFIG_SYS_SDRAM_SIZE == 16)
wdenkdb2f721f2003-03-06 00:58:30 +0000363/* With a 16 MB DIMM, the PSDMR is configured as follows:
364 *
365 * configuration parameters found in Motorola documentation
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PSDMR (0x016EB452)
wdenkdb2f721f2003-03-06 00:58:30 +0000368#else
369#error "INVALID SDRAM CONFIGURATION"
370#endif
371
wdenkdb2f721f2003-03-06 00:58:30 +0000372#define RS232EN_1 0x02000002
373#define RS232EN_2 0x01000001
374#define FETHIEN 0x08000008
375#define FETH_RST 0x04000004
376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
378#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
379#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
380#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
381#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdb2f721f2003-03-06 00:58:30 +0000382
wdenk7a8e9bed2003-05-31 18:35:21 +0000383/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
wdenk5d232d02003-05-22 22:52:13 +0000384/* 0x0EB2B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
wdenk5d232d02003-05-22 22:52:13 +0000386 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
387 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
388 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
wdenkdb2f721f2003-03-06 00:58:30 +0000389 )
wdenk5d232d02003-05-22 22:52:13 +0000390
wdenk7a8e9bed2003-05-31 18:35:21 +0000391/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
wdenkdb2f721f2003-03-06 00:58:30 +0000393
wdenk8bde7f72003-06-27 21:31:46 +0000394/* This value should actually be situated in the first 256 bytes of the FLASH
wdenkdb2f721f2003-03-06 00:58:30 +0000395 which on the standard MPC8266ADS board is at address 0xFF800000
396 The linker script places it at 0xFFF00000 instead.
397
wdenk8bde7f72003-06-27 21:31:46 +0000398 It still works, however, as long as the ADS board jumper JP3 is set to
399 position 2-3 so the board is using the BCSR as Hardware Configuration Word
wdenkdb2f721f2003-03-06 00:58:30 +0000400
wdenk8bde7f72003-06-27 21:31:46 +0000401 If you want to use the one defined here instead, ust copy the first 256 bytes from
402 0xfff00000 to 0xff800000 (for 8MB flash)
wdenkdb2f721f2003-03-06 00:58:30 +0000403
404 - Rune
405
wdenk7a8e9bed2003-05-31 18:35:21 +0000406*/
wdenkdb2f721f2003-03-06 00:58:30 +0000407
408/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_HRCW_SLAVE1 0
410#define CONFIG_SYS_HRCW_SLAVE2 0
411#define CONFIG_SYS_HRCW_SLAVE3 0
412#define CONFIG_SYS_HRCW_SLAVE4 0
413#define CONFIG_SYS_HRCW_SLAVE5 0
414#define CONFIG_SYS_HRCW_SLAVE6 0
415#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkdb2f721f2003-03-06 00:58:30 +0000416
417#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
418#define BOOTFLAG_WARM 0x02 /* Software reboot */
419
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
421#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
422# define CONFIG_SYS_RAMBOOT
wdenkdb2f721f2003-03-06 00:58:30 +0000423#endif
424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
426#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
427#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200430# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200432# define CONFIG_ENV_SECT_SIZE 0x40000
wdenkdb2f721f2003-03-06 00:58:30 +0000433#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200434# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200436# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#endif /* CONFIG_SYS_RAMBOOT */
wdenkdb2f721f2003-03-06 00:58:30 +0000438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500440#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000442#endif
443
wdenk7a8e9bed2003-05-31 18:35:21 +0000444/*-----------------------------------------------------------------------
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200445 * HIDx - Hardware Implementation-dependent Registers 2-11
wdenk7a8e9bed2003-05-31 18:35:21 +0000446 *-----------------------------------------------------------------------
447 * HID0 also contains cache control - initially enable both caches and
448 * invalidate contents, then the final state leaves only the instruction
449 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
450 * but Soft reset does not.
451 *
452 * HID1 has only read-only information - nothing to set.
453 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454/*#define CONFIG_SYS_HID0_INIT 0 */
455#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk7a8e9bed2003-05-31 18:35:21 +0000456 HID0_DCE |\
457 HID0_ICFI |\
458 HID0_DCI |\
459 HID0_IFEM |\
460 HID0_ABE)
461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenkdb2f721f2003-03-06 00:58:30 +0000463
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_HID2 0
wdenkdb2f721f2003-03-06 00:58:30 +0000465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_SYPCR 0xFFFFFFC3
467#define CONFIG_SYS_BCR 0x004C0000
468#define CONFIG_SYS_SIUMCR 0x4E64C000
469#define CONFIG_SYS_SCCR 0x00000000
wdenkdb2f721f2003-03-06 00:58:30 +0000470
wdenk5d232d02003-05-22 22:52:13 +0000471/* local bus memory map
472 *
473 * 0x00000000-0x03FFFFFF 64MB SDRAM
474 * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
475 * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
476 * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200477 * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
wdenk5d232d02003-05-22 22:52:13 +0000478 * 0xF8000000-0xF8007FFF 32KB BCSR
479 * 0xF8100000-0xF8107FFF 32KB ATM UNI
480 * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
481 * 0xF8300000-0xF8307FFF 32KB EEPROM
482 * 0xFE000000-0xFFFFFFFF 32MB flash
483 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
485#define CONFIG_SYS_OR0_PRELIM 0xFE000836
486#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
487#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
488#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
489#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
490#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
491#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
492#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
493#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
wdenk5d232d02003-05-22 22:52:13 +0000494
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_RMR 0x0001
496#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
497#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
498#define CONFIG_SYS_RCCR 0
499#define CONFIG_SYS_MPTPR 0x00001900
500#define CONFIG_SYS_PSRT 0x00000021
wdenkdb2f721f2003-03-06 00:58:30 +0000501
wdenk65bd0e22003-09-18 10:45:21 +0000502/* This address must not exist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
wdenkdb2f721f2003-03-06 00:58:30 +0000504
wdenk5d232d02003-05-22 22:52:13 +0000505/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
507#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
508#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +0000509 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000510
wdenk8bde7f72003-06-27 21:31:46 +0000511/*
wdenk5d232d02003-05-22 22:52:13 +0000512 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +0000513 * All three PCI master windows, which allow the CPU to access PCI
514 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +0000515 * these windows.
516 */
517
518/* PCIBR0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
520#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000521/* PCIBR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
523#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000524
wdenk8bde7f72003-06-27 21:31:46 +0000525/*
wdenk5d232d02003-05-22 22:52:13 +0000526 * Master window that allows the CPU to access PCI Memory (prefetch).
527 * This window will be setup with the first set of Outbound ATU registers
528 * in the bridge.
529 */
530
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
532#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
533#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
534#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
535#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000536
wdenk8bde7f72003-06-27 21:31:46 +0000537/*
wdenk5d232d02003-05-22 22:52:13 +0000538 * Master window that allows the CPU to access PCI Memory (non-prefetch).
539 * This window will be setup with the second set of Outbound ATU registers
540 * in the bridge.
541 */
542
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
544#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
545#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
546#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
547#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000548
wdenk8bde7f72003-06-27 21:31:46 +0000549/*
wdenk5d232d02003-05-22 22:52:13 +0000550 * Master window that allows the CPU to access PCI IO space.
551 * This window will be setup with the third set of Outbound ATU registers
552 * in the bridge.
553 */
554
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
556#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
557#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
558#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
559#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000560
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200561/*
562 * JFFS2 partitions
563 *
564 */
565/* No command line, one static partition, whole device */
566#undef CONFIG_JFFS2_CMDLINE
567#define CONFIG_JFFS2_DEV "nor0"
568#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
569#define CONFIG_JFFS2_PART_OFFSET 0x00000000
570
571/* mtdparts command line support */
572/*
573#define CONFIG_JFFS2_CMDLINE
574#define MTDIDS_DEFAULT ""
575#define MTDPARTS_DEFAULT ""
576*/
wdenk5d232d02003-05-22 22:52:13 +0000577
wdenkdb2f721f2003-03-06 00:58:30 +0000578#endif /* __CONFIG_H */