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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00002/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
Lei Wenaf62a552011-06-28 21:50:06 +00006 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10#include <common.h>
Simon Glass2a809092016-06-12 23:30:27 -060011#include <errno.h>
Lei Wenaf62a552011-06-28 21:50:06 +000012#include <malloc.h>
13#include <mmc.h>
14#include <sdhci.h>
15
Stefan Roese492d3222015-06-29 14:58:09 +020016#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
17void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
18#else
Lei Wenaf62a552011-06-28 21:50:06 +000019void *aligned_buffer;
Stefan Roese492d3222015-06-29 14:58:09 +020020#endif
Lei Wenaf62a552011-06-28 21:50:06 +000021
22static void sdhci_reset(struct sdhci_host *host, u8 mask)
23{
24 unsigned long timeout;
25
26 /* Wait max 100 ms */
27 timeout = 100;
28 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
29 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
30 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -080031 printf("%s: Reset 0x%x never completed.\n",
32 __func__, (int)mask);
Lei Wenaf62a552011-06-28 21:50:06 +000033 return;
34 }
35 timeout--;
36 udelay(1000);
37 }
38}
39
40static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
41{
42 int i;
43 if (cmd->resp_type & MMC_RSP_136) {
44 /* CRC is stripped so we need to do some shifting. */
45 for (i = 0; i < 4; i++) {
46 cmd->response[i] = sdhci_readl(host,
47 SDHCI_RESPONSE + (3-i)*4) << 8;
48 if (i != 3)
49 cmd->response[i] |= sdhci_readb(host,
50 SDHCI_RESPONSE + (3-i)*4-1);
51 }
52 } else {
53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
54 }
55}
56
57static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
58{
59 int i;
60 char *offs;
61 for (i = 0; i < data->blocksize; i += 4) {
62 offs = data->dest + i;
63 if (data->flags == MMC_DATA_READ)
64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
65 else
66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
67 }
68}
69
70static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
71 unsigned int start_addr)
72{
Lei Wena004abd2011-10-08 04:14:57 +000073 unsigned int stat, rdy, mask, timeout, block = 0;
Alex Deymo7dde50d2017-04-02 01:24:34 -070074 bool transfer_done = false;
Masahiro Yamada45a68fe2016-12-07 22:10:29 +090075#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chung804c7f42012-09-20 20:31:55 +000076 unsigned char ctrl;
Juhyun \(Justin\) Oh2c011842013-09-13 18:06:00 +000077 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Jaehoon Chung804c7f42012-09-20 20:31:55 +000078 ctrl &= ~SDHCI_CTRL_DMA_MASK;
Juhyun \(Justin\) Oh2c011842013-09-13 18:06:00 +000079 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung804c7f42012-09-20 20:31:55 +000080#endif
Lei Wenaf62a552011-06-28 21:50:06 +000081
Jaehoon Chung5d48e422012-09-20 20:31:54 +000082 timeout = 1000000;
Lei Wenaf62a552011-06-28 21:50:06 +000083 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
85 do {
86 stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 if (stat & SDHCI_INT_ERROR) {
Masahiro Yamada61f2e5e2017-12-30 02:00:12 +090088 pr_debug("%s: Error detected in status(0x%X)!\n",
89 __func__, stat);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +090090 return -EIO;
Lei Wenaf62a552011-06-28 21:50:06 +000091 }
Alex Deymo7dde50d2017-04-02 01:24:34 -070092 if (!transfer_done && (stat & rdy)) {
Lei Wenaf62a552011-06-28 21:50:06 +000093 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
94 continue;
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 sdhci_transfer_pio(host, data);
97 data->dest += data->blocksize;
Alex Deymo7dde50d2017-04-02 01:24:34 -070098 if (++block >= data->blocks) {
99 /* Keep looping until the SDHCI_INT_DATA_END is
100 * cleared, even if we finished sending all the
101 * blocks.
102 */
103 transfer_done = true;
104 continue;
105 }
Lei Wenaf62a552011-06-28 21:50:06 +0000106 }
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900107#ifdef CONFIG_MMC_SDHCI_SDMA
Alex Deymo7dde50d2017-04-02 01:24:34 -0700108 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000109 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Lei Wen3e81c772011-10-08 04:14:58 +0000110 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
Lei Wenaf62a552011-06-28 21:50:06 +0000111 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
112 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
113 }
114#endif
Lei Wena004abd2011-10-08 04:14:57 +0000115 if (timeout-- > 0)
116 udelay(10);
117 else {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800118 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900119 return -ETIMEDOUT;
Lei Wena004abd2011-10-08 04:14:57 +0000120 }
Lei Wenaf62a552011-06-28 21:50:06 +0000121 } while (!(stat & SDHCI_INT_DATA_END));
122 return 0;
123}
124
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200125/*
126 * No command will be sent by driver if card is busy, so driver must wait
127 * for card ready state.
128 * Every time when card is busy after timeout then (last) timeout value will be
129 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900130 * Each function call will use last timeout value.
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200131 */
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900132#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900133#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed90bb432016-06-29 13:42:01 -0700134#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200135
Simon Glasse7881d82017-07-29 11:35:31 -0600136#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600137static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
138 struct mmc_data *data)
Lei Wenaf62a552011-06-28 21:50:06 +0000139{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600140 struct mmc *mmc = mmc_get_mmc_dev(dev);
141
142#else
143static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
144 struct mmc_data *data)
145{
146#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200147 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000148 unsigned int stat = 0;
149 int ret = 0;
150 int trans_bytes = 0, is_aligned = 1;
151 u32 mask, flags, mode;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200152 unsigned int time = 0, start_addr = 0;
Simon Glass19d2e342016-05-14 14:03:04 -0600153 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Vipul Kumar36332b62018-05-03 12:20:54 +0530154 ulong start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000155
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200156 /* Timeout unit - ms */
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900157 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000158
Lei Wenaf62a552011-06-28 21:50:06 +0000159 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
160
161 /* We shouldn't wait for data inihibit for stop commands, even
162 though they might use busy signaling */
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530163 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
164 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
Lei Wenaf62a552011-06-28 21:50:06 +0000165 mask &= ~SDHCI_DATA_INHIBIT;
166
167 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200168 if (time >= cmd_timeout) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800169 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900170 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200171 cmd_timeout += cmd_timeout;
172 printf("timeout increasing to: %u ms.\n",
173 cmd_timeout);
174 } else {
175 puts("timeout.\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900176 return -ECOMM;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200177 }
Lei Wenaf62a552011-06-28 21:50:06 +0000178 }
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200179 time++;
Lei Wenaf62a552011-06-28 21:50:06 +0000180 udelay(1000);
181 }
182
Jorge Ramirez-Ortiz713e6812017-11-02 15:10:21 +0100183 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
184
Lei Wenaf62a552011-06-28 21:50:06 +0000185 mask = SDHCI_INT_RESPONSE;
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530186 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
187 mask = SDHCI_INT_DATA_AVAIL;
188
Lei Wenaf62a552011-06-28 21:50:06 +0000189 if (!(cmd->resp_type & MMC_RSP_PRESENT))
190 flags = SDHCI_CMD_RESP_NONE;
191 else if (cmd->resp_type & MMC_RSP_136)
192 flags = SDHCI_CMD_RESP_LONG;
193 else if (cmd->resp_type & MMC_RSP_BUSY) {
194 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chung17ea3c82016-07-12 21:18:46 +0900195 if (data)
196 mask |= SDHCI_INT_DATA_END;
Lei Wenaf62a552011-06-28 21:50:06 +0000197 } else
198 flags = SDHCI_CMD_RESP_SHORT;
199
200 if (cmd->resp_type & MMC_RSP_CRC)
201 flags |= SDHCI_CMD_CRC;
202 if (cmd->resp_type & MMC_RSP_OPCODE)
203 flags |= SDHCI_CMD_INDEX;
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530204 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
Lei Wenaf62a552011-06-28 21:50:06 +0000205 flags |= SDHCI_CMD_DATA;
206
Darwin Rambo30e6d972013-12-19 15:13:25 -0800207 /* Set Transfer mode regarding to data flag */
Heinrich Schuchardtbb7b4ef2017-11-10 21:13:34 +0100208 if (data) {
Lei Wenaf62a552011-06-28 21:50:06 +0000209 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
210 mode = SDHCI_TRNS_BLK_CNT_EN;
211 trans_bytes = data->blocks * data->blocksize;
212 if (data->blocks > 1)
213 mode |= SDHCI_TRNS_MULTI;
214
215 if (data->flags == MMC_DATA_READ)
216 mode |= SDHCI_TRNS_READ;
217
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900218#ifdef CONFIG_MMC_SDHCI_SDMA
Lei Wenaf62a552011-06-28 21:50:06 +0000219 if (data->flags == MMC_DATA_READ)
Rob Herring3c1fcb72015-03-17 15:46:38 -0500220 start_addr = (unsigned long)data->dest;
Lei Wenaf62a552011-06-28 21:50:06 +0000221 else
Rob Herring3c1fcb72015-03-17 15:46:38 -0500222 start_addr = (unsigned long)data->src;
Lei Wenaf62a552011-06-28 21:50:06 +0000223 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
224 (start_addr & 0x7) != 0x0) {
225 is_aligned = 0;
Rob Herring3c1fcb72015-03-17 15:46:38 -0500226 start_addr = (unsigned long)aligned_buffer;
Lei Wenaf62a552011-06-28 21:50:06 +0000227 if (data->flags != MMC_DATA_READ)
228 memcpy(aligned_buffer, data->src, trans_bytes);
229 }
230
Stefan Roese492d3222015-06-29 14:58:09 +0200231#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
232 /*
233 * Always use this bounce-buffer when
234 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
235 */
236 is_aligned = 0;
237 start_addr = (unsigned long)aligned_buffer;
238 if (data->flags != MMC_DATA_READ)
239 memcpy(aligned_buffer, data->src, trans_bytes);
240#endif
241
Lei Wenaf62a552011-06-28 21:50:06 +0000242 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
243 mode |= SDHCI_TRNS_DMA;
244#endif
245 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
246 data->blocksize),
247 SDHCI_BLOCK_SIZE);
248 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
249 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu5e1c23c2015-03-23 17:57:00 -0500250 } else if (cmd->resp_type & MMC_RSP_BUSY) {
251 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000252 }
253
254 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900255#ifdef CONFIG_MMC_SDHCI_SDMA
Heinrich Schuchardtbb7b4ef2017-11-10 21:13:34 +0100256 if (data) {
Kevin Liufa7720b2017-03-08 15:16:44 +0800257 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
258 flush_cache(start_addr, trans_bytes);
259 }
Lei Wenaf62a552011-06-28 21:50:06 +0000260#endif
261 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese29905a42015-06-29 14:58:08 +0200262 start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000263 do {
264 stat = sdhci_readl(host, SDHCI_INT_STATUS);
265 if (stat & SDHCI_INT_ERROR)
266 break;
Lei Wenaf62a552011-06-28 21:50:06 +0000267
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900268 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
269 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
270 return 0;
271 } else {
272 printf("%s: Timeout for status update!\n",
273 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900274 return -ETIMEDOUT;
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900275 }
Jaehoon Chung3a638322012-04-23 02:36:25 +0000276 }
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900277 } while ((stat & mask) != mask);
Jaehoon Chung3a638322012-04-23 02:36:25 +0000278
Lei Wenaf62a552011-06-28 21:50:06 +0000279 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
280 sdhci_cmd_done(host, cmd);
281 sdhci_writel(host, mask, SDHCI_INT_STATUS);
282 } else
283 ret = -1;
284
285 if (!ret && data)
286 ret = sdhci_transfer_data(host, data, start_addr);
287
Tushar Behera13243f22012-09-20 20:31:57 +0000288 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
289 udelay(1000);
290
Lei Wenaf62a552011-06-28 21:50:06 +0000291 stat = sdhci_readl(host, SDHCI_INT_STATUS);
292 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
293 if (!ret) {
294 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
295 !is_aligned && (data->flags == MMC_DATA_READ))
296 memcpy(data->dest, aligned_buffer, trans_bytes);
297 return 0;
298 }
299
300 sdhci_reset(host, SDHCI_RESET_CMD);
301 sdhci_reset(host, SDHCI_RESET_DATA);
302 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900303 return -ETIMEDOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000304 else
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900305 return -ECOMM;
Lei Wenaf62a552011-06-28 21:50:06 +0000306}
307
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530308#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
309static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
310{
311 int err;
312 struct mmc *mmc = mmc_get_mmc_dev(dev);
313 struct sdhci_host *host = mmc->priv;
314
315 debug("%s\n", __func__);
316
Ramon Friedb70fe962018-05-14 15:02:30 +0300317 if (host->ops && host->ops->platform_execute_tuning) {
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530318 err = host->ops->platform_execute_tuning(mmc, opcode);
319 if (err)
320 return err;
321 return 0;
322 }
323 return 0;
324}
325#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000326static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
327{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200328 struct sdhci_host *host = mmc->priv;
Stefan Roese899fb9e2016-12-12 08:34:42 +0100329 unsigned int div, clk = 0, timeout;
Lei Wenaf62a552011-06-28 21:50:06 +0000330
Wenyou Yang79667b72015-09-22 14:59:25 +0800331 /* Wait max 20 ms */
332 timeout = 200;
333 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
334 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
335 if (timeout == 0) {
336 printf("%s: Timeout to wait cmd & data inhibit\n",
337 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900338 return -EBUSY;
Wenyou Yang79667b72015-09-22 14:59:25 +0800339 }
340
341 timeout--;
342 udelay(100);
343 }
344
Stefan Roese899fb9e2016-12-12 08:34:42 +0100345 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000346
347 if (clock == 0)
348 return 0;
349
Ramon Friedb70fe962018-05-14 15:02:30 +0300350 if (host->ops && host->ops->set_delay)
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530351 host->ops->set_delay(host);
352
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900353 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800354 /*
355 * Check if the Host Controller supports Programmable Clock
356 * Mode.
357 */
358 if (host->clk_mul) {
359 for (div = 1; div <= 1024; div++) {
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800360 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000361 break;
362 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800363
364 /*
365 * Set Programmable Clock Mode in the Clock
366 * Control register.
367 */
368 clk = SDHCI_PROG_CLOCK_MODE;
369 div--;
370 } else {
371 /* Version 3.00 divisors must be a multiple of 2. */
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100372 if (host->max_clk <= clock) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800373 div = 1;
374 } else {
375 for (div = 2;
376 div < SDHCI_MAX_DIV_SPEC_300;
377 div += 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100378 if ((host->max_clk / div) <= clock)
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800379 break;
380 }
381 }
382 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000383 }
384 } else {
385 /* Version 2.00 divisors must be a power of 2. */
386 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100387 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000388 break;
389 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800390 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000391 }
Lei Wenaf62a552011-06-28 21:50:06 +0000392
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900393 if (host->ops && host->ops->set_clock)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900394 host->ops->set_clock(host, div);
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000395
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800396 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wenaf62a552011-06-28 21:50:06 +0000397 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
398 << SDHCI_DIVIDER_HI_SHIFT;
399 clk |= SDHCI_CLOCK_INT_EN;
400 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
401
402 /* Wait max 20 ms */
403 timeout = 20;
404 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
405 & SDHCI_CLOCK_INT_STABLE)) {
406 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800407 printf("%s: Internal clock never stabilised.\n",
408 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900409 return -EBUSY;
Lei Wenaf62a552011-06-28 21:50:06 +0000410 }
411 timeout--;
412 udelay(1000);
413 }
414
415 clk |= SDHCI_CLOCK_CARD_EN;
416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
417 return 0;
418}
419
420static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
421{
422 u8 pwr = 0;
423
424 if (power != (unsigned short)-1) {
425 switch (1 << power) {
426 case MMC_VDD_165_195:
427 pwr = SDHCI_POWER_180;
428 break;
429 case MMC_VDD_29_30:
430 case MMC_VDD_30_31:
431 pwr = SDHCI_POWER_300;
432 break;
433 case MMC_VDD_32_33:
434 case MMC_VDD_33_34:
435 pwr = SDHCI_POWER_330;
436 break;
437 }
438 }
439
440 if (pwr == 0) {
441 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
442 return;
443 }
444
445 pwr |= SDHCI_POWER_ON;
446
447 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
448}
449
Simon Glasse7881d82017-07-29 11:35:31 -0600450#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600451static int sdhci_set_ios(struct udevice *dev)
452{
453 struct mmc *mmc = mmc_get_mmc_dev(dev);
454#else
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900455static int sdhci_set_ios(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000456{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600457#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000458 u32 ctrl;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200459 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000460
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900461 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900462 host->ops->set_control_reg(host);
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000463
Lei Wenaf62a552011-06-28 21:50:06 +0000464 if (mmc->clock != host->clock)
465 sdhci_set_clock(mmc, mmc->clock);
466
Siva Durga Prasad Paladugu2a2d7ef2018-04-19 12:37:04 +0530467 if (mmc->clk_disable)
468 sdhci_set_clock(mmc, 0);
469
Lei Wenaf62a552011-06-28 21:50:06 +0000470 /* Set bus width */
471 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
472 if (mmc->bus_width == 8) {
473 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900474 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
475 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000476 ctrl |= SDHCI_CTRL_8BITBUS;
477 } else {
Matt Reimerf88a4292015-02-19 11:22:53 -0700478 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
479 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000480 ctrl &= ~SDHCI_CTRL_8BITBUS;
481 if (mmc->bus_width == 4)
482 ctrl |= SDHCI_CTRL_4BITBUS;
483 else
484 ctrl &= ~SDHCI_CTRL_4BITBUS;
485 }
486
487 if (mmc->clock > 26000000)
488 ctrl |= SDHCI_CTRL_HISPD;
489 else
490 ctrl &= ~SDHCI_CTRL_HISPD;
491
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100492 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
493 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000494 ctrl &= ~SDHCI_CTRL_HISPD;
495
Lei Wenaf62a552011-06-28 21:50:06 +0000496 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900497
Stefan Roese210841c2016-12-12 08:24:56 +0100498 /* If available, call the driver specific "post" set_ios() function */
499 if (host->ops && host->ops->set_ios_post)
500 host->ops->set_ios_post(host);
501
Simon Glassef1e4ed2016-06-12 23:30:28 -0600502 return 0;
Lei Wenaf62a552011-06-28 21:50:06 +0000503}
504
Jeroen Hofstee6588c782014-10-08 22:57:43 +0200505static int sdhci_init(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000506{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200507 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000508
Masahiro Yamada8d549b62016-08-25 16:07:34 +0900509 sdhci_reset(host, SDHCI_RESET_ALL);
510
Lei Wenaf62a552011-06-28 21:50:06 +0000511 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
512 aligned_buffer = memalign(8, 512*1024);
513 if (!aligned_buffer) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800514 printf("%s: Aligned buffer alloc failed!!!\n",
515 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900516 return -ENOMEM;
Lei Wenaf62a552011-06-28 21:50:06 +0000517 }
518 }
519
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200520 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000521
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900522 if (host->ops && host->ops->get_cd)
Jaehoon Chung6f88a3a2016-12-30 15:30:15 +0900523 host->ops->get_cd(host);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000524
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000525 /* Enable only interrupts served by the SD controller */
Darwin Rambo30e6d972013-12-19 15:13:25 -0800526 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
527 SDHCI_INT_ENABLE);
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000528 /* Mask all sdhci interrupt sources */
529 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wenaf62a552011-06-28 21:50:06 +0000530
Lei Wenaf62a552011-06-28 21:50:06 +0000531 return 0;
532}
533
Simon Glasse7881d82017-07-29 11:35:31 -0600534#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600535int sdhci_probe(struct udevice *dev)
536{
537 struct mmc *mmc = mmc_get_mmc_dev(dev);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200538
Simon Glassef1e4ed2016-06-12 23:30:28 -0600539 return sdhci_init(mmc);
540}
541
542const struct dm_mmc_ops sdhci_ops = {
543 .send_cmd = sdhci_send_command,
544 .set_ios = sdhci_set_ios,
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530545#ifdef MMC_SUPPORTS_TUNING
546 .execute_tuning = sdhci_execute_tuning,
547#endif
Simon Glassef1e4ed2016-06-12 23:30:28 -0600548};
549#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200550static const struct mmc_ops sdhci_ops = {
551 .send_cmd = sdhci_send_command,
552 .set_ios = sdhci_set_ios,
553 .init = sdhci_init,
554};
Simon Glassef1e4ed2016-06-12 23:30:28 -0600555#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200556
Jaehoon Chung14bed522016-07-26 19:06:24 +0900557int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100558 u32 f_max, u32 f_min)
Simon Glass2a809092016-06-12 23:30:27 -0600559{
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530560 u32 caps, caps_1 = 0;
Jaehoon Chung14bed522016-07-26 19:06:24 +0900561
562 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900563
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900564#ifdef CONFIG_MMC_SDHCI_SDMA
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900565 if (!(caps & SDHCI_CAN_DO_SDMA)) {
566 printf("%s: Your controller doesn't support SDMA!!\n",
567 __func__);
568 return -EINVAL;
569 }
570#endif
Jaehoon Chung895549a2016-09-26 08:10:01 +0900571 if (host->quirks & SDHCI_QUIRK_REG32_RW)
572 host->version =
573 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
574 else
575 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung14bed522016-07-26 19:06:24 +0900576
577 cfg->name = host->name;
Simon Glasse7881d82017-07-29 11:35:31 -0600578#ifndef CONFIG_DM_MMC
Simon Glass2a809092016-06-12 23:30:27 -0600579 cfg->ops = &sdhci_ops;
580#endif
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800581
582 /* Check whether the clock multiplier is supported or not */
583 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
584 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
585 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
586 SDHCI_CLOCK_MUL_SHIFT;
587 }
588
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100589 if (host->max_clk == 0) {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900590 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100591 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600592 SDHCI_CLOCK_BASE_SHIFT;
593 else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100594 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600595 SDHCI_CLOCK_BASE_SHIFT;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100596 host->max_clk *= 1000000;
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800597 if (host->clk_mul)
598 host->max_clk *= host->clk_mul;
Simon Glass2a809092016-06-12 23:30:27 -0600599 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100600 if (host->max_clk == 0) {
Masahiro Yamada6c679542016-08-25 16:07:35 +0900601 printf("%s: Hardware doesn't specify base clock frequency\n",
602 __func__);
Simon Glass2a809092016-06-12 23:30:27 -0600603 return -EINVAL;
Masahiro Yamada6c679542016-08-25 16:07:35 +0900604 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100605 if (f_max && (f_max < host->max_clk))
606 cfg->f_max = f_max;
607 else
608 cfg->f_max = host->max_clk;
609 if (f_min)
610 cfg->f_min = f_min;
Simon Glass2a809092016-06-12 23:30:27 -0600611 else {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900612 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glass2a809092016-06-12 23:30:27 -0600613 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
614 else
615 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
616 }
617 cfg->voltages = 0;
618 if (caps & SDHCI_CAN_VDD_330)
619 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
620 if (caps & SDHCI_CAN_VDD_300)
621 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
622 if (caps & SDHCI_CAN_VDD_180)
623 cfg->voltages |= MMC_VDD_165_195;
624
Masahiro Yamada3137e642016-08-25 16:07:36 +0900625 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
626 cfg->voltages |= host->voltages;
627
Masahiro Yamadabe165fb2017-12-30 02:00:08 +0900628 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
Jaehoon Chung3fd0a9b2016-12-30 15:30:21 +0900629
630 /* Since Host Controller Version3.0 */
Jaehoon Chung14bed522016-07-26 19:06:24 +0900631 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chungecd7b242016-12-30 15:30:11 +0900632 if (!(caps & SDHCI_CAN_DO_8BIT))
633 cfg->host_caps &= ~MMC_MODE_8BIT;
Simon Glass2a809092016-06-12 23:30:27 -0600634 }
635
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100636 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
637 cfg->host_caps &= ~MMC_MODE_HS;
638 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
639 }
640
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530641 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
642 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
643
644 if (!(cfg->voltages & MMC_VDD_165_195) ||
645 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
646 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
647 SDHCI_SUPPORT_DDR50);
648
649 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
650 SDHCI_SUPPORT_DDR50))
651 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
652
653 if (caps_1 & SDHCI_SUPPORT_SDR104) {
654 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
655 /*
656 * SD3.0: SDR104 is supported so (for eMMC) the caps2
657 * field can be promoted to support HS200.
658 */
659 cfg->host_caps |= MMC_CAP(MMC_HS_200);
660 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
661 cfg->host_caps |= MMC_CAP(UHS_SDR50);
662 }
663
664 if (caps_1 & SDHCI_SUPPORT_DDR50)
665 cfg->host_caps |= MMC_CAP(UHS_DDR50);
666
Jaehoon Chung14bed522016-07-26 19:06:24 +0900667 if (host->host_caps)
668 cfg->host_caps |= host->host_caps;
Simon Glass2a809092016-06-12 23:30:27 -0600669
670 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
671
672 return 0;
673}
674
Simon Glassef1e4ed2016-06-12 23:30:28 -0600675#ifdef CONFIG_BLK
676int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
677{
678 return mmc_bind(dev, mmc, cfg);
679}
680#else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100681int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
Lei Wenaf62a552011-06-28 21:50:06 +0000682{
Masahiro Yamada6c679542016-08-25 16:07:35 +0900683 int ret;
684
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100685 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
Masahiro Yamada6c679542016-08-25 16:07:35 +0900686 if (ret)
687 return ret;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000688
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200689 host->mmc = mmc_create(&host->cfg, host);
690 if (host->mmc == NULL) {
691 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900692 return -ENOMEM;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200693 }
Lei Wenaf62a552011-06-28 21:50:06 +0000694
695 return 0;
696}
Simon Glassef1e4ed2016-06-12 23:30:28 -0600697#endif