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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Eran Libertyf046ccd2005-07-28 10:08:46 -05002/*
Ilya Yanok7c619dd2010-06-28 16:44:33 +04003 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05004 */
5
Eran Libertyf046ccd2005-07-28 10:08:46 -05006#ifndef __MPC83XX_H__
7#define __MPC83XX_H__
8
Dave Liuf6eda7f2006-10-25 14:41:21 -05009#include <config.h>
Anton Vorontsovbf30bb12008-05-28 18:20:15 +040010#include <asm/fsl_lbc.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050011#if defined(CONFIG_E300)
12#include <asm/e300.h>
13#endif
14
Heiko Schocher4e8b7502011-09-26 13:36:53 +020015/*
16 * MPC83xx cpu provide RCR register to do reset thing specially
Eran Libertyf046ccd2005-07-28 10:08:46 -050017 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050018#define MPC83xx_RESET
19
Heiko Schocher4e8b7502011-09-26 13:36:53 +020020/*
21 * System reset offset (PowerPC standard)
Eran Libertyf046ccd2005-07-28 10:08:46 -050022 */
Dave Liue0803132006-12-07 21:11:58 +080023#define EXC_OFF_SYS_RESET 0x0100
Rafal Jaworowski02032e82007-06-22 14:58:04 +020024#define _START_OFFSET EXC_OFF_SYS_RESET
Eran Libertyf046ccd2005-07-28 10:08:46 -050025
Heiko Schocher4e8b7502011-09-26 13:36:53 +020026/*
27 * IMMRBAR - Internal Memory Register Base Address
Eran Libertyf046ccd2005-07-28 10:08:46 -050028 */
Scott Woode4c09502008-06-30 14:13:28 -050029#ifndef CONFIG_DEFAULT_IMMR
Heiko Schocher4e8b7502011-09-26 13:36:53 +020030/* Default IMMR base address */
31#define CONFIG_DEFAULT_IMMR 0xFF400000
Scott Woode4c09502008-06-30 14:13:28 -050032#endif
Heiko Schocher4e8b7502011-09-26 13:36:53 +020033/* Register offset to immr */
34#define IMMRBAR 0x0000
35#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
Dave Liue0803132006-12-07 21:11:58 +080036#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
Eran Libertyf046ccd2005-07-28 10:08:46 -050037
Heiko Schocher4e8b7502011-09-26 13:36:53 +020038/*
39 * LAWBAR - Local Access Window Base Address Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050040 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +020041/* Register offset to immr */
42#define LBLAWBAR0 0x0020
Dave Liue0803132006-12-07 21:11:58 +080043#define LBLAWAR0 0x0024
44#define LBLAWBAR1 0x0028
45#define LBLAWAR1 0x002C
46#define LBLAWBAR2 0x0030
47#define LBLAWAR2 0x0034
48#define LBLAWBAR3 0x0038
49#define LBLAWAR3 0x003C
Heiko Schocher4e8b7502011-09-26 13:36:53 +020050#define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
Eran Libertyf046ccd2005-07-28 10:08:46 -050051
Heiko Schocher4e8b7502011-09-26 13:36:53 +020052/*
53 * SPRIDR - System Part and Revision ID Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050054 */
Kim Phillipse5c4ade2008-03-28 10:19:07 -050055#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
56#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
Eran Libertyf046ccd2005-07-28 10:08:46 -050057
Peter Tyser2c7920a2009-05-22 17:23:25 -050058#if defined(CONFIG_MPC834x)
Kim Phillipse5c4ade2008-03-28 10:19:07 -050059#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
60#define REVID_MINOR(spridr) (spridr & 0x000000FF)
61#else
62#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
63#define REVID_MINOR(spridr) (spridr & 0x0000000F)
64#endif
Dave Liue0803132006-12-07 21:11:58 +080065
Kim Phillipse5c4ade2008-03-28 10:19:07 -050066#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
Kim Phillips6b70ffb2008-06-16 15:55:53 -050067#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
Dave Liue0803132006-12-07 21:11:58 +080068
Ilya Yanok7c619dd2010-06-28 16:44:33 +040069#define SPR_8308 0x8100
Gerlando Falautoa88731a2012-10-10 22:13:08 +000070#define SPR_8309 0x8110
Kim Phillips6b70ffb2008-06-16 15:55:53 -050071#define SPR_831X_FAMILY 0x80B
Kim Phillipse5c4ade2008-03-28 10:19:07 -050072#define SPR_8311 0x80B2
73#define SPR_8313 0x80B0
74#define SPR_8314 0x80B6
75#define SPR_8315 0x80B4
Kim Phillips6b70ffb2008-06-16 15:55:53 -050076#define SPR_832X_FAMILY 0x806
Kim Phillipse5c4ade2008-03-28 10:19:07 -050077#define SPR_8321 0x8066
78#define SPR_8323 0x8062
Kim Phillips6b70ffb2008-06-16 15:55:53 -050079#define SPR_834X_FAMILY 0x803
Kim Phillipse5c4ade2008-03-28 10:19:07 -050080#define SPR_8343 0x8036
81#define SPR_8347_TBGA_ 0x8032
82#define SPR_8347_PBGA_ 0x8034
83#define SPR_8349 0x8030
Kim Phillips6b70ffb2008-06-16 15:55:53 -050084#define SPR_836X_FAMILY 0x804
Kim Phillipse5c4ade2008-03-28 10:19:07 -050085#define SPR_8358_TBGA_ 0x804A
86#define SPR_8358_PBGA_ 0x804E
87#define SPR_8360 0x8048
Kim Phillips6b70ffb2008-06-16 15:55:53 -050088#define SPR_837X_FAMILY 0x80C
Kim Phillipse5c4ade2008-03-28 10:19:07 -050089#define SPR_8377 0x80C6
90#define SPR_8378 0x80C4
91#define SPR_8379 0x80C2
Scott Woodd87c57b2007-04-16 14:31:55 -050092
Heiko Schocher4e8b7502011-09-26 13:36:53 +020093/*
94 * SPCR - System Priority Configuration Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050095 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +020096/* PCI Highest Priority Enable */
97#define SPCR_PCIHPE 0x10000000
Dave Liue0803132006-12-07 21:11:58 +080098#define SPCR_PCIHPE_SHIFT (31-3)
Heiko Schocher4e8b7502011-09-26 13:36:53 +020099/* PCI bridge system bus request priority */
100#define SPCR_PCIPR 0x03000000
Dave Liue0803132006-12-07 21:11:58 +0800101#define SPCR_PCIPR_SHIFT (31-7)
102#define SPCR_OPT 0x00800000 /* Optimize */
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400103#define SPCR_OPT_SHIFT (31-8)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200104/* E300 PowerPC core time base unit enable */
105#define SPCR_TBEN 0x00400000
Dave Liue0803132006-12-07 21:11:58 +0800106#define SPCR_TBEN_SHIFT (31-9)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200107/* E300 PowerPC Core system bus request priority */
108#define SPCR_COREPR 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800109#define SPCR_COREPR_SHIFT (31-11)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500110
Peter Tyser2c7920a2009-05-22 17:23:25 -0500111#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800112/* SPCR bits - MPC8349 specific */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200113/* TSEC1 data priority */
114#define SPCR_TSEC1DP 0x00003000
Dave Liue0803132006-12-07 21:11:58 +0800115#define SPCR_TSEC1DP_SHIFT (31-19)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200116/* TSEC1 buffer descriptor priority */
117#define SPCR_TSEC1BDP 0x00000C00
Dave Liue0803132006-12-07 21:11:58 +0800118#define SPCR_TSEC1BDP_SHIFT (31-21)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200119/* TSEC1 emergency priority */
120#define SPCR_TSEC1EP 0x00000300
Dave Liue0803132006-12-07 21:11:58 +0800121#define SPCR_TSEC1EP_SHIFT (31-23)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200122/* TSEC2 data priority */
123#define SPCR_TSEC2DP 0x00000030
Dave Liue0803132006-12-07 21:11:58 +0800124#define SPCR_TSEC2DP_SHIFT (31-27)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200125/* TSEC2 buffer descriptor priority */
126#define SPCR_TSEC2BDP 0x0000000C
Dave Liue0803132006-12-07 21:11:58 +0800127#define SPCR_TSEC2BDP_SHIFT (31-29)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200128/* TSEC2 emergency priority */
129#define SPCR_TSEC2EP 0x00000003
Dave Liue0803132006-12-07 21:11:58 +0800130#define SPCR_TSEC2EP_SHIFT (31-31)
Scott Woodd87c57b2007-04-16 14:31:55 -0500131
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400132#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
133 defined(CONFIG_MPC837x)
134/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200135/* TSEC data priority */
136#define SPCR_TSECDP 0x00003000
Scott Woodd87c57b2007-04-16 14:31:55 -0500137#define SPCR_TSECDP_SHIFT (31-19)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200138/* TSEC buffer descriptor priority */
139#define SPCR_TSECBDP 0x00000C00
Dave Liuec2638e2008-01-10 23:05:00 +0800140#define SPCR_TSECBDP_SHIFT (31-21)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200141/* TSEC emergency priority */
142#define SPCR_TSECEP 0x00000300
Dave Liuec2638e2008-01-10 23:05:00 +0800143#define SPCR_TSECEP_SHIFT (31-23)
Dave Liu5f820432006-11-03 19:33:44 -0600144#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500145
Dave Liue0803132006-12-07 21:11:58 +0800146/* SICRL/H - System I/O Configuration Register Low/High
147 */
Peter Tyser2c7920a2009-05-22 17:23:25 -0500148#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800149/* SICRL bits - MPC8349 specific */
150#define SICRL_LDP_A 0x80000000
151#define SICRL_USB1 0x40000000
152#define SICRL_USB0 0x20000000
153#define SICRL_UART 0x0C000000
154#define SICRL_GPIO1_A 0x02000000
155#define SICRL_GPIO1_B 0x01000000
156#define SICRL_GPIO1_C 0x00800000
157#define SICRL_GPIO1_D 0x00400000
158#define SICRL_GPIO1_E 0x00200000
159#define SICRL_GPIO1_F 0x00180000
160#define SICRL_GPIO1_G 0x00040000
161#define SICRL_GPIO1_H 0x00020000
162#define SICRL_GPIO1_I 0x00010000
163#define SICRL_GPIO1_J 0x00008000
164#define SICRL_GPIO1_K 0x00004000
165#define SICRL_GPIO1_L 0x00003000
Eran Libertyf046ccd2005-07-28 10:08:46 -0500166
Dave Liue0803132006-12-07 21:11:58 +0800167/* SICRH bits - MPC8349 specific */
168#define SICRH_DDR 0x80000000
169#define SICRH_TSEC1_A 0x10000000
170#define SICRH_TSEC1_B 0x08000000
171#define SICRH_TSEC1_C 0x04000000
172#define SICRH_TSEC1_D 0x02000000
173#define SICRH_TSEC1_E 0x01000000
174#define SICRH_TSEC1_F 0x00800000
175#define SICRH_TSEC2_A 0x00400000
176#define SICRH_TSEC2_B 0x00200000
177#define SICRH_TSEC2_C 0x00100000
178#define SICRH_TSEC2_D 0x00080000
179#define SICRH_TSEC2_E 0x00040000
180#define SICRH_TSEC2_F 0x00020000
181#define SICRH_TSEC2_G 0x00010000
182#define SICRH_TSEC2_H 0x00008000
183#define SICRH_GPIO2_A 0x00004000
184#define SICRH_GPIO2_B 0x00002000
185#define SICRH_GPIO2_C 0x00001000
186#define SICRH_GPIO2_D 0x00000800
187#define SICRH_GPIO2_E 0x00000400
188#define SICRH_GPIO2_F 0x00000200
189#define SICRH_GPIO2_G 0x00000180
190#define SICRH_GPIO2_H 0x00000060
191#define SICRH_TSOBI1 0x00000002
192#define SICRH_TSOBI2 0x00000001
193
194#elif defined(CONFIG_MPC8360)
195/* SICRL bits - MPC8360 specific */
196#define SICRL_LDP_A 0xC0000000
197#define SICRL_LCLK_1 0x10000000
198#define SICRL_LCLK_2 0x08000000
199#define SICRL_SRCID_A 0x03000000
200#define SICRL_IRQ_CKSTP_A 0x00C00000
201
202/* SICRH bits - MPC8360 specific */
203#define SICRH_DDR 0x80000000
204#define SICRH_SECONDARY_DDR 0x40000000
205#define SICRH_SDDROE 0x20000000
206#define SICRH_IRQ3 0x10000000
207#define SICRH_UC1EOBI 0x00000004
208#define SICRH_UC2E1OBI 0x00000002
209#define SICRH_UC2E2OBI 0x00000001
Dave Liu24c3aca2006-12-07 21:13:15 +0800210
Peter Tyser2c7920a2009-05-22 17:23:25 -0500211#elif defined(CONFIG_MPC832x)
212/* SICRL bits - MPC832x specific */
Dave Liu24c3aca2006-12-07 21:13:15 +0800213#define SICRL_LDP_LCS_A 0x80000000
214#define SICRL_IRQ_CKS 0x20000000
215#define SICRL_PCI_MSRC 0x10000000
216#define SICRL_URT_CTPR 0x06000000
217#define SICRL_IRQ_CTPR 0x00C00000
Scott Woodd87c57b2007-04-16 14:31:55 -0500218
Dave Liu555da612007-09-18 12:36:58 +0800219#elif defined(CONFIG_MPC8313)
220/* SICRL bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500221#define SICRL_LBC 0x30000000
222#define SICRL_UART 0x0C000000
223#define SICRL_SPI_A 0x03000000
224#define SICRL_SPI_B 0x00C00000
225#define SICRL_SPI_C 0x00300000
226#define SICRL_SPI_D 0x000C0000
Ron Madridf9863252010-06-01 17:00:49 -0700227#define SICRL_USBDR_11 0x00000C00
228#define SICRL_USBDR_10 0x00000800
229#define SICRL_USBDR_01 0x00000400
230#define SICRL_USBDR_00 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500231#define SICRL_ETSEC1_A 0x0000000C
232#define SICRL_ETSEC2_A 0x00000003
233
Dave Liu555da612007-09-18 12:36:58 +0800234/* SICRH bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500235#define SICRH_INTR_A 0x02000000
236#define SICRH_INTR_B 0x00C00000
237#define SICRH_IIC 0x00300000
238#define SICRH_ETSEC2_B 0x000C0000
239#define SICRH_ETSEC2_C 0x00030000
240#define SICRH_ETSEC2_D 0x0000C000
241#define SICRH_ETSEC2_E 0x00003000
242#define SICRH_ETSEC2_F 0x00000C00
243#define SICRH_ETSEC2_G 0x00000300
244#define SICRH_ETSEC1_B 0x00000080
245#define SICRH_ETSEC1_C 0x00000060
246#define SICRH_GTX1_DLY 0x00000008
247#define SICRH_GTX2_DLY 0x00000004
248#define SICRH_TSOBI1 0x00000002
249#define SICRH_TSOBI2 0x00000001
250
Dave Liu555da612007-09-18 12:36:58 +0800251#elif defined(CONFIG_MPC8315)
252/* SICRL bits - MPC8315 specific */
253#define SICRL_DMA_CH0 0xc0000000
254#define SICRL_DMA_SPI 0x30000000
255#define SICRL_UART 0x0c000000
256#define SICRL_IRQ4 0x02000000
257#define SICRL_IRQ5 0x01800000
258#define SICRL_IRQ6_7 0x00400000
259#define SICRL_IIC1 0x00300000
260#define SICRL_TDM 0x000c0000
261#define SICRL_TDM_SHARED 0x00030000
262#define SICRL_PCI_A 0x0000c000
263#define SICRL_ELBC_A 0x00003000
264#define SICRL_ETSEC1_A 0x000000c0
265#define SICRL_ETSEC1_B 0x00000030
266#define SICRL_ETSEC1_C 0x0000000c
267#define SICRL_TSEXPOBI 0x00000001
268
269/* SICRH bits - MPC8315 specific */
270#define SICRH_GPIO_0 0xc0000000
271#define SICRH_GPIO_1 0x30000000
272#define SICRH_GPIO_2 0x0c000000
273#define SICRH_GPIO_3 0x03000000
274#define SICRH_GPIO_4 0x00c00000
275#define SICRH_GPIO_5 0x00300000
276#define SICRH_GPIO_6 0x000c0000
277#define SICRH_GPIO_7 0x00030000
278#define SICRH_GPIO_8 0x0000c000
279#define SICRH_GPIO_9 0x00003000
280#define SICRH_GPIO_10 0x00000c00
281#define SICRH_GPIO_11 0x00000300
282#define SICRH_ETSEC2_A 0x000000c0
283#define SICRH_TSOBI1 0x00000002
284#define SICRH_TSOBI2 0x00000001
285
Peter Tyser2c7920a2009-05-22 17:23:25 -0500286#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800287/* SICRL bits - MPC837x specific */
288#define SICRL_USB_A 0xC0000000
289#define SICRL_USB_B 0x30000000
Andy Fleminge1ac3872008-10-30 16:50:14 -0500290#define SICRL_USB_B_SD 0x20000000
Dave Liu03051c32007-09-18 12:36:11 +0800291#define SICRL_UART 0x0C000000
292#define SICRL_GPIO_A 0x02000000
293#define SICRL_GPIO_B 0x01000000
294#define SICRL_GPIO_C 0x00800000
295#define SICRL_GPIO_D 0x00400000
296#define SICRL_GPIO_E 0x00200000
297#define SICRL_GPIO_F 0x00180000
298#define SICRL_GPIO_G 0x00040000
299#define SICRL_GPIO_H 0x00020000
300#define SICRL_GPIO_I 0x00010000
301#define SICRL_GPIO_J 0x00008000
302#define SICRL_GPIO_K 0x00004000
303#define SICRL_GPIO_L 0x00003000
304#define SICRL_DMA_A 0x00000800
305#define SICRL_DMA_B 0x00000400
306#define SICRL_DMA_C 0x00000200
307#define SICRL_DMA_D 0x00000100
308#define SICRL_DMA_E 0x00000080
309#define SICRL_DMA_F 0x00000040
310#define SICRL_DMA_G 0x00000020
311#define SICRL_DMA_H 0x00000010
312#define SICRL_DMA_I 0x00000008
313#define SICRL_DMA_J 0x00000004
314#define SICRL_LDP_A 0x00000002
315#define SICRL_LDP_B 0x00000001
316
317/* SICRH bits - MPC837x specific */
318#define SICRH_DDR 0x80000000
319#define SICRH_TSEC1_A 0x10000000
320#define SICRH_TSEC1_B 0x08000000
321#define SICRH_TSEC2_A 0x00400000
322#define SICRH_TSEC2_B 0x00200000
323#define SICRH_TSEC2_C 0x00100000
324#define SICRH_TSEC2_D 0x00080000
325#define SICRH_TSEC2_E 0x00040000
326#define SICRH_TMR 0x00010000
327#define SICRH_GPIO2_A 0x00008000
328#define SICRH_GPIO2_B 0x00004000
329#define SICRH_GPIO2_C 0x00002000
330#define SICRH_GPIO2_D 0x00001000
331#define SICRH_GPIO2_E 0x00000C00
Andy Fleminge1ac3872008-10-30 16:50:14 -0500332#define SICRH_GPIO2_E_SD 0x00000800
Dave Liu03051c32007-09-18 12:36:11 +0800333#define SICRH_GPIO2_F 0x00000300
334#define SICRH_GPIO2_G 0x000000C0
335#define SICRH_GPIO2_H 0x00000030
336#define SICRH_SPI 0x00000003
Andy Fleminge1ac3872008-10-30 16:50:14 -0500337#define SICRH_SPI_SD 0x00000001
Ilya Yanokf3ce2502010-09-17 23:41:48 +0200338
339#elif defined(CONFIG_MPC8308)
340/* SICRL bits - MPC8308 specific */
341#define SICRL_SPI_PF0 (0 << 28)
342#define SICRL_SPI_PF1 (1 << 28)
343#define SICRL_SPI_PF3 (3 << 28)
344#define SICRL_UART_PF0 (0 << 26)
345#define SICRL_UART_PF1 (1 << 26)
346#define SICRL_UART_PF3 (3 << 26)
347#define SICRL_IRQ_PF0 (0 << 24)
348#define SICRL_IRQ_PF1 (1 << 24)
349#define SICRL_I2C2_PF0 (0 << 20)
350#define SICRL_I2C2_PF1 (1 << 20)
351#define SICRL_ETSEC1_TX_CLK (0 << 6)
352#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
353
354/* SICRH bits - MPC8308 specific */
355#define SICRH_ESDHC_A_SD (0 << 30)
356#define SICRH_ESDHC_A_GTM (1 << 30)
357#define SICRH_ESDHC_A_GPIO (3 << 30)
358#define SICRH_ESDHC_B_SD (0 << 28)
359#define SICRH_ESDHC_B_GTM (1 << 28)
360#define SICRH_ESDHC_B_GPIO (3 << 28)
361#define SICRH_ESDHC_C_SD (0 << 26)
362#define SICRH_ESDHC_C_GTM (1 << 26)
363#define SICRH_ESDHC_C_GPIO (3 << 26)
364#define SICRH_GPIO_A_GPIO (0 << 24)
365#define SICRH_GPIO_A_TSEC2 (1 << 24)
366#define SICRH_GPIO_B_GPIO (0 << 22)
367#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
368#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
369#define SICRH_IEEE1588_A_TMR (1 << 20)
370#define SICRH_IEEE1588_A_GPIO (3 << 20)
371#define SICRH_USB (1 << 18)
372#define SICRH_GTM_GTM (1 << 16)
373#define SICRH_GTM_GPIO (3 << 16)
374#define SICRH_IEEE1588_B_TMR (1 << 14)
375#define SICRH_IEEE1588_B_GPIO (3 << 14)
376#define SICRH_ETSEC2_CRS (1 << 12)
377#define SICRH_ETSEC2_GPIO (3 << 12)
378#define SICRH_GPIOSEL_0 (0 << 8)
379#define SICRH_GPIOSEL_1 (1 << 8)
380#define SICRH_TMROBI_V3P3 (0 << 4)
381#define SICRH_TMROBI_V2P5 (1 << 4)
382#define SICRH_TSOBI1_V3P3 (0 << 1)
383#define SICRH_TSOBI1_V2P5 (1 << 1)
384#define SICRH_TSOBI2_V3P3 (0 << 0)
385#define SICRH_TSOBI2_V2P5 (1 << 0)
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000386
387#elif defined(CONFIG_MPC8309)
388/* SICR_1 */
389#define SICR_1_UART1_UART1S (0 << (30-2))
390#define SICR_1_UART1_UART1RTS (1 << (30-2))
391#define SICR_1_I2C_I2C (0 << (30-4))
392#define SICR_1_I2C_CKSTOP (1 << (30-4))
393#define SICR_1_IRQ_A_IRQ (0 << (30-6))
394#define SICR_1_IRQ_A_MCP (1 << (30-6))
395#define SICR_1_IRQ_B_IRQ (0 << (30-8))
396#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
397#define SICR_1_GPIO_A_GPIO (0 << (30-10))
398#define SICR_1_GPIO_A_SD (2 << (30-10))
399#define SICR_1_GPIO_A_DDR (3 << (30-10))
400#define SICR_1_GPIO_B_GPIO (0 << (30-12))
401#define SICR_1_GPIO_B_SD (2 << (30-12))
402#define SICR_1_GPIO_B_QE (3 << (30-12))
403#define SICR_1_GPIO_C_GPIO (0 << (30-14))
404#define SICR_1_GPIO_C_CAN (1 << (30-14))
405#define SICR_1_GPIO_C_DDR (2 << (30-14))
406#define SICR_1_GPIO_C_LCS (3 << (30-14))
407#define SICR_1_GPIO_D_GPIO (0 << (30-16))
408#define SICR_1_GPIO_D_CAN (1 << (30-16))
409#define SICR_1_GPIO_D_DDR (2 << (30-16))
410#define SICR_1_GPIO_D_LCS (3 << (30-16))
411#define SICR_1_GPIO_E_GPIO (0 << (30-18))
412#define SICR_1_GPIO_E_CAN (1 << (30-18))
413#define SICR_1_GPIO_E_DDR (2 << (30-18))
414#define SICR_1_GPIO_E_LCS (3 << (30-18))
415#define SICR_1_GPIO_F_GPIO (0 << (30-20))
416#define SICR_1_GPIO_F_CAN (1 << (30-20))
417#define SICR_1_GPIO_F_CK (2 << (30-20))
418#define SICR_1_USB_A_USBDR (0 << (30-22))
419#define SICR_1_USB_A_UART2S (1 << (30-22))
420#define SICR_1_USB_B_USBDR (0 << (30-24))
421#define SICR_1_USB_B_UART2S (1 << (30-24))
422#define SICR_1_USB_B_UART2RTS (2 << (30-24))
423#define SICR_1_USB_C_USBDR (0 << (30-26))
424#define SICR_1_USB_C_QE_EXT (3 << (30-26))
425#define SICR_1_FEC1_FEC1 (0 << (30-28))
426#define SICR_1_FEC1_GTM (1 << (30-28))
427#define SICR_1_FEC1_GPIO (2 << (30-28))
428#define SICR_1_FEC2_FEC2 (0 << (30-30))
429#define SICR_1_FEC2_GTM (1 << (30-30))
430#define SICR_1_FEC2_GPIO (2 << (30-30))
431/* SICR_2 */
432#define SICR_2_FEC3_FEC3 (0 << (30-0))
433#define SICR_2_FEC3_TMR (1 << (30-0))
434#define SICR_2_FEC3_GPIO (2 << (30-0))
435#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
436#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
437#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
438#define SICR_2_ELBC_A_LA (0 << (30-4))
439#define SICR_2_ELBC_B_LCLK (0 << (30-6))
440#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
441#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
442#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
443/* bits 10-11 unused */
444#define SICR_2_USB_D_USBDR (0 << (30-12))
445#define SICR_2_USB_D_GPIO (2 << (30-12))
446#define SICR_2_USB_D_QE_BRG (3 << (30-12))
447#define SICR_2_PCI_PCI (0 << (30-14))
448#define SICR_2_PCI_CPCI_HS (2 << (30-14))
449#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
450#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
451#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
452#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
453#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
454#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
455#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
456#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
457#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
458#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
459#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
460#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
461#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
462#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
463#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
464#define SICR_2_QUIESCE_B (0 << (30-24))
465
Dave Liue0803132006-12-07 21:11:58 +0800466#endif
467
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200468/*
469 * SWCRR - System Watchdog Control Register
Dave Liue0803132006-12-07 21:11:58 +0800470 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200471/* Register offset to immr */
472#define SWCRR 0x0204
473/* Software Watchdog Time Count */
474#define SWCRR_SWTC 0xFFFF0000
475/* Watchdog Enable bit */
476#define SWCRR_SWEN 0x00000004
477/* Software Watchdog Reset/Interrupt Select bit */
478#define SWCRR_SWRI 0x00000002
479/* Software Watchdog Counter Prescale bit */
480#define SWCRR_SWPR 0x00000001
481#define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
482 SWCRR_SWRI | SWCRR_SWPR))
Dave Liue0803132006-12-07 21:11:58 +0800483
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200484/*
485 * SWCNR - System Watchdog Counter Register
Dave Liue0803132006-12-07 21:11:58 +0800486 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200487/* Register offset to immr */
488#define SWCNR 0x0208
489/* Software Watchdog Count mask */
490#define SWCNR_SWCN 0x0000FFFF
Dave Liue0803132006-12-07 21:11:58 +0800491#define SWCNR_RES ~(SWCNR_SWCN)
492
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200493/*
494 * SWSRR - System Watchdog Service Register
Dave Liue0803132006-12-07 21:11:58 +0800495 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200496/* Register offset to immr */
497#define SWSRR 0x020E
Dave Liue0803132006-12-07 21:11:58 +0800498
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200499/*
500 * ACR - Arbiter Configuration Register
Dave Liue0803132006-12-07 21:11:58 +0800501 */
502#define ACR_COREDIS 0x10000000 /* Core disable */
503#define ACR_COREDIS_SHIFT (31-7)
504#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
505#define ACR_PIPE_DEP_SHIFT (31-15)
506#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
507#define ACR_PCI_RPTCNT_SHIFT (31-19)
508#define ACR_RPTCNT 0x00000700 /* Repeat count */
509#define ACR_RPTCNT_SHIFT (31-23)
510#define ACR_APARK 0x00000030 /* Address parking */
511#define ACR_APARK_SHIFT (31-27)
512#define ACR_PARKM 0x0000000F /* Parking master */
513#define ACR_PARKM_SHIFT (31-31)
514
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200515/*
516 * ATR - Arbiter Timers Register
Dave Liue0803132006-12-07 21:11:58 +0800517 */
518#define ATR_DTO 0x00FF0000 /* Data time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700519#define ATR_DTO_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800520#define ATR_ATO 0x000000FF /* Address time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700521#define ATR_ATO_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800522
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200523/*
524 * AER - Arbiter Event Register
Dave Liue0803132006-12-07 21:11:58 +0800525 */
526#define AER_ETEA 0x00000020 /* Transfer error */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200527/* Reserved transfer type */
528#define AER_RES 0x00000010
529/* External control word transfer type */
530#define AER_ECW 0x00000008
531/* Address Only transfer type */
532#define AER_AO 0x00000004
Dave Liue0803132006-12-07 21:11:58 +0800533#define AER_DTO 0x00000002 /* Data time out */
534#define AER_ATO 0x00000001 /* Address time out */
535
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200536/*
537 * AEATR - Arbiter Event Address Register
Dave Liue0803132006-12-07 21:11:58 +0800538 */
539#define AEATR_EVENT 0x07000000 /* Event type */
Nick Spence002d27c2008-08-22 23:52:40 -0700540#define AEATR_EVENT_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800541#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
Nick Spence002d27c2008-08-22 23:52:40 -0700542#define AEATR_MSTR_ID_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800543#define AEATR_TBST 0x00000800 /* Transfer burst */
Nick Spence002d27c2008-08-22 23:52:40 -0700544#define AEATR_TBST_SHIFT 11
Dave Liue0803132006-12-07 21:11:58 +0800545#define AEATR_TSIZE 0x00000700 /* Transfer Size */
Nick Spence002d27c2008-08-22 23:52:40 -0700546#define AEATR_TSIZE_SHIFT 8
Dave Liue0803132006-12-07 21:11:58 +0800547#define AEATR_TTYPE 0x0000001F /* Transfer Type */
Nick Spence002d27c2008-08-22 23:52:40 -0700548#define AEATR_TTYPE_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800549
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200550/*
551 * HRCWL - Hard Reset Configuration Word Low
Dave Liue0803132006-12-07 21:11:58 +0800552 */
553#define HRCWL_LBIUCM 0x80000000
554#define HRCWL_LBIUCM_SHIFT 31
555#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
556#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
557
558#define HRCWL_DDRCM 0x40000000
559#define HRCWL_DDRCM_SHIFT 30
560#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
561#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
562
563#define HRCWL_SPMF 0x0f000000
564#define HRCWL_SPMF_SHIFT 24
565#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
566#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
567#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
568#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
569#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
570#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
571#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
572#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
573#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
574#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
575#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
576#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
577#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
578#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
579#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
580#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
581
582#define HRCWL_VCO_BYPASS 0x00000000
583#define HRCWL_VCO_1X2 0x00000000
584#define HRCWL_VCO_1X4 0x00200000
585#define HRCWL_VCO_1X8 0x00400000
586
587#define HRCWL_COREPLL 0x007F0000
588#define HRCWL_COREPLL_SHIFT 16
589#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
590#define HRCWL_CORE_TO_CSB_1X1 0x00020000
591#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
592#define HRCWL_CORE_TO_CSB_2X1 0x00040000
593#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
594#define HRCWL_CORE_TO_CSB_3X1 0x00060000
595
Peter Tyser2c7920a2009-05-22 17:23:25 -0500596#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
Dave Liue0803132006-12-07 21:11:58 +0800597#define HRCWL_CEVCOD 0x000000C0
598#define HRCWL_CEVCOD_SHIFT 6
599#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
600#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
601#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
602
603#define HRCWL_CEPDF 0x00000020
604#define HRCWL_CEPDF_SHIFT 5
605#define HRCWL_CE_PLL_DIV_1X1 0x00000000
606#define HRCWL_CE_PLL_DIV_2X1 0x00000020
607
608#define HRCWL_CEPMF 0x0000001F
609#define HRCWL_CEPMF_SHIFT 0
610#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
611#define HRCWL_CE_TO_PLL_1X2 0x00000002
612#define HRCWL_CE_TO_PLL_1X3 0x00000003
613#define HRCWL_CE_TO_PLL_1X4 0x00000004
614#define HRCWL_CE_TO_PLL_1X5 0x00000005
615#define HRCWL_CE_TO_PLL_1X6 0x00000006
616#define HRCWL_CE_TO_PLL_1X7 0x00000007
617#define HRCWL_CE_TO_PLL_1X8 0x00000008
618#define HRCWL_CE_TO_PLL_1X9 0x00000009
619#define HRCWL_CE_TO_PLL_1X10 0x0000000A
620#define HRCWL_CE_TO_PLL_1X11 0x0000000B
621#define HRCWL_CE_TO_PLL_1X12 0x0000000C
622#define HRCWL_CE_TO_PLL_1X13 0x0000000D
623#define HRCWL_CE_TO_PLL_1X14 0x0000000E
624#define HRCWL_CE_TO_PLL_1X15 0x0000000F
625#define HRCWL_CE_TO_PLL_1X16 0x00000010
626#define HRCWL_CE_TO_PLL_1X17 0x00000011
627#define HRCWL_CE_TO_PLL_1X18 0x00000012
628#define HRCWL_CE_TO_PLL_1X19 0x00000013
629#define HRCWL_CE_TO_PLL_1X20 0x00000014
630#define HRCWL_CE_TO_PLL_1X21 0x00000015
631#define HRCWL_CE_TO_PLL_1X22 0x00000016
632#define HRCWL_CE_TO_PLL_1X23 0x00000017
633#define HRCWL_CE_TO_PLL_1X24 0x00000018
634#define HRCWL_CE_TO_PLL_1X25 0x00000019
635#define HRCWL_CE_TO_PLL_1X26 0x0000001A
636#define HRCWL_CE_TO_PLL_1X27 0x0000001B
637#define HRCWL_CE_TO_PLL_1X28 0x0000001C
638#define HRCWL_CE_TO_PLL_1X29 0x0000001D
639#define HRCWL_CE_TO_PLL_1X30 0x0000001E
640#define HRCWL_CE_TO_PLL_1X31 0x0000001F
Dave Liu03051c32007-09-18 12:36:11 +0800641
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400642#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
Dave Liu6f3931a2008-01-10 23:06:05 +0800643#define HRCWL_SVCOD 0x30000000
644#define HRCWL_SVCOD_SHIFT 28
645#define HRCWL_SVCOD_DIV_2 0x00000000
646#define HRCWL_SVCOD_DIV_4 0x10000000
647#define HRCWL_SVCOD_DIV_8 0x20000000
648#define HRCWL_SVCOD_DIV_1 0x30000000
649
Peter Tyser2c7920a2009-05-22 17:23:25 -0500650#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800651#define HRCWL_SVCOD 0x30000000
652#define HRCWL_SVCOD_SHIFT 28
653#define HRCWL_SVCOD_DIV_4 0x00000000
654#define HRCWL_SVCOD_DIV_8 0x10000000
655#define HRCWL_SVCOD_DIV_2 0x20000000
656#define HRCWL_SVCOD_DIV_1 0x30000000
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000657#elif defined(CONFIG_MPC8309)
658
659#define HRCWL_CEVCOD 0x000000C0
660#define HRCWL_CEVCOD_SHIFT 6
661/*
662 * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
663 * these are different than with 8360, 832x
664 */
665#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
666#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
667#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
668
669#define HRCWL_CEPDF 0x00000020
670#define HRCWL_CEPDF_SHIFT 5
671#define HRCWL_CE_PLL_DIV_1X1 0x00000000
672#define HRCWL_CE_PLL_DIV_2X1 0x00000020
673
674#define HRCWL_CEPMF 0x0000001F
675#define HRCWL_CEPMF_SHIFT 0
676#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
677#define HRCWL_CE_TO_PLL_1X2 0x00000002
678#define HRCWL_CE_TO_PLL_1X3 0x00000003
679#define HRCWL_CE_TO_PLL_1X4 0x00000004
680#define HRCWL_CE_TO_PLL_1X5 0x00000005
681#define HRCWL_CE_TO_PLL_1X6 0x00000006
682#define HRCWL_CE_TO_PLL_1X7 0x00000007
683#define HRCWL_CE_TO_PLL_1X8 0x00000008
684#define HRCWL_CE_TO_PLL_1X9 0x00000009
685#define HRCWL_CE_TO_PLL_1X10 0x0000000A
686#define HRCWL_CE_TO_PLL_1X11 0x0000000B
687#define HRCWL_CE_TO_PLL_1X12 0x0000000C
688#define HRCWL_CE_TO_PLL_1X13 0x0000000D
689#define HRCWL_CE_TO_PLL_1X14 0x0000000E
690#define HRCWL_CE_TO_PLL_1X15 0x0000000F
691#define HRCWL_CE_TO_PLL_1X16 0x00000010
692#define HRCWL_CE_TO_PLL_1X17 0x00000011
693#define HRCWL_CE_TO_PLL_1X18 0x00000012
694#define HRCWL_CE_TO_PLL_1X19 0x00000013
695#define HRCWL_CE_TO_PLL_1X20 0x00000014
696#define HRCWL_CE_TO_PLL_1X21 0x00000015
697#define HRCWL_CE_TO_PLL_1X22 0x00000016
698#define HRCWL_CE_TO_PLL_1X23 0x00000017
699#define HRCWL_CE_TO_PLL_1X24 0x00000018
700#define HRCWL_CE_TO_PLL_1X25 0x00000019
701#define HRCWL_CE_TO_PLL_1X26 0x0000001A
702#define HRCWL_CE_TO_PLL_1X27 0x0000001B
703#define HRCWL_CE_TO_PLL_1X28 0x0000001C
704#define HRCWL_CE_TO_PLL_1X29 0x0000001D
705#define HRCWL_CE_TO_PLL_1X30 0x0000001E
706#define HRCWL_CE_TO_PLL_1X31 0x0000001F
707
708#define HRCWL_SVCOD 0x30000000
709#define HRCWL_SVCOD_SHIFT 28
710#define HRCWL_SVCOD_DIV_2 0x00000000
711#define HRCWL_SVCOD_DIV_4 0x10000000
712#define HRCWL_SVCOD_DIV_8 0x20000000
713#define HRCWL_SVCOD_DIV_1 0x30000000
Dave Liue0803132006-12-07 21:11:58 +0800714#endif
715
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200716/*
717 * HRCWH - Hardware Reset Configuration Word High
Dave Liue0803132006-12-07 21:11:58 +0800718 */
719#define HRCWH_PCI_HOST 0x80000000
720#define HRCWH_PCI_HOST_SHIFT 31
721#define HRCWH_PCI_AGENT 0x00000000
722
Peter Tyser2c7920a2009-05-22 17:23:25 -0500723#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800724#define HRCWH_32_BIT_PCI 0x00000000
725#define HRCWH_64_BIT_PCI 0x40000000
726#endif
727
728#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
729#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
730
731#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
732#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
733
Peter Tyser2c7920a2009-05-22 17:23:25 -0500734#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800735#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
736#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
737
738#elif defined(CONFIG_MPC8360)
739#define HRCWH_PCICKDRV_DISABLE 0x00000000
740#define HRCWH_PCICKDRV_ENABLE 0x10000000
741#endif
742
743#define HRCWH_CORE_DISABLE 0x08000000
744#define HRCWH_CORE_ENABLE 0x00000000
745
746#define HRCWH_FROM_0X00000100 0x00000000
747#define HRCWH_FROM_0XFFF00100 0x04000000
748
749#define HRCWH_BOOTSEQ_DISABLE 0x00000000
750#define HRCWH_BOOTSEQ_NORMAL 0x01000000
751#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
752
753#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
754#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
755
756#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
757#define HRCWH_ROM_LOC_PCI1 0x00100000
Peter Tyser2c7920a2009-05-22 17:23:25 -0500758#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800759#define HRCWH_ROM_LOC_PCI2 0x00200000
760#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500761#if defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800762#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
763#endif
Dave Liue0803132006-12-07 21:11:58 +0800764#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
765#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
766#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
767
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400768#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
769 defined(CONFIG_MPC837x)
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200770#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
Scott Woodd87c57b2007-04-16 14:31:55 -0500771#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200772#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
Scott Woodd87c57b2007-04-16 14:31:55 -0500773#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
774
775#define HRCWH_RL_EXT_LEGACY 0x00000000
776#define HRCWH_RL_EXT_NAND 0x00040000
777
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400778#define HRCWH_TSEC1M_MASK 0x0000E000
Scott Woodd87c57b2007-04-16 14:31:55 -0500779#define HRCWH_TSEC1M_IN_MII 0x00000000
780#define HRCWH_TSEC1M_IN_RMII 0x00002000
781#define HRCWH_TSEC1M_IN_RGMII 0x00006000
782#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
783#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
784
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400785#define HRCWH_TSEC2M_MASK 0x00001C00
Scott Woodd87c57b2007-04-16 14:31:55 -0500786#define HRCWH_TSEC2M_IN_MII 0x00000000
787#define HRCWH_TSEC2M_IN_RMII 0x00000400
788#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
789#define HRCWH_TSEC2M_IN_RTBI 0x00001400
790#define HRCWH_TSEC2M_IN_SGMII 0x00001800
791#endif
792
Peter Tyser2c7920a2009-05-22 17:23:25 -0500793#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800794#define HRCWH_TSEC1M_IN_RGMII 0x00000000
795#define HRCWH_TSEC1M_IN_RTBI 0x00004000
796#define HRCWH_TSEC1M_IN_GMII 0x00008000
797#define HRCWH_TSEC1M_IN_TBI 0x0000C000
798#define HRCWH_TSEC2M_IN_RGMII 0x00000000
799#define HRCWH_TSEC2M_IN_RTBI 0x00001000
800#define HRCWH_TSEC2M_IN_GMII 0x00002000
801#define HRCWH_TSEC2M_IN_TBI 0x00003000
802#endif
803
804#if defined(CONFIG_MPC8360)
805#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
806#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
807#endif
808
809#define HRCWH_BIG_ENDIAN 0x00000000
810#define HRCWH_LITTLE_ENDIAN 0x00000008
811
812#define HRCWH_LALE_NORMAL 0x00000000
813#define HRCWH_LALE_EARLY 0x00000004
814
815#define HRCWH_LDP_SET 0x00000000
816#define HRCWH_LDP_CLEAR 0x00000002
817
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200818/*
819 * RSR - Reset Status Register
Dave Liue0803132006-12-07 21:11:58 +0800820 */
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400821#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
822 defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800823#define RSR_RSTSRC 0xF0000000 /* Reset source */
824#define RSR_RSTSRC_SHIFT 28
825#else
Dave Liue0803132006-12-07 21:11:58 +0800826#define RSR_RSTSRC 0xE0000000 /* Reset source */
827#define RSR_RSTSRC_SHIFT 29
Dave Liu03051c32007-09-18 12:36:11 +0800828#endif
Dave Liue0803132006-12-07 21:11:58 +0800829#define RSR_BSF 0x00010000 /* Boot seq. fail */
830#define RSR_BSF_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200831/* software soft reset */
832#define RSR_SWSR 0x00002000
Dave Liue0803132006-12-07 21:11:58 +0800833#define RSR_SWSR_SHIFT 13
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200834/* software hard reset */
835#define RSR_SWHR 0x00001000
Dave Liue0803132006-12-07 21:11:58 +0800836#define RSR_SWHR_SHIFT 12
837#define RSR_JHRS 0x00000200 /* jtag hreset */
838#define RSR_JHRS_SHIFT 9
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200839/* jtag sreset status */
840#define RSR_JSRS 0x00000100
Dave Liue0803132006-12-07 21:11:58 +0800841#define RSR_JSRS_SHIFT 8
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200842/* checkstop reset status */
843#define RSR_CSHR 0x00000010
Dave Liue0803132006-12-07 21:11:58 +0800844#define RSR_CSHR_SHIFT 4
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200845/* software watchdog reset status */
846#define RSR_SWRS 0x00000008
Dave Liue0803132006-12-07 21:11:58 +0800847#define RSR_SWRS_SHIFT 3
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200848/* bus monitop reset status */
849#define RSR_BMRS 0x00000004
Dave Liue0803132006-12-07 21:11:58 +0800850#define RSR_BMRS_SHIFT 2
851#define RSR_SRS 0x00000002 /* soft reset status */
852#define RSR_SRS_SHIFT 1
853#define RSR_HRS 0x00000001 /* hard reset status */
854#define RSR_HRS_SHIFT 0
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200855#define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
856 RSR_SWHR | RSR_JHRS | \
857 RSR_JSRS | RSR_CSHR | \
858 RSR_SWRS | RSR_BMRS | \
859 RSR_SRS | RSR_HRS))
860/*
861 * RMR - Reset Mode Register
Dave Liue0803132006-12-07 21:11:58 +0800862 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200863/* checkstop reset enable */
864#define RMR_CSRE 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800865#define RMR_CSRE_SHIFT 0
866#define RMR_RES ~(RMR_CSRE)
867
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200868/*
869 * RCR - Reset Control Register
Dave Liue0803132006-12-07 21:11:58 +0800870 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200871/* software hard reset */
872#define RCR_SWHR 0x00000002
873/* software soft reset */
874#define RCR_SWSR 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800875#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
876
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200877/*
878 * RCER - Reset Control Enable Register
Dave Liue0803132006-12-07 21:11:58 +0800879 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200880/* software hard reset */
881#define RCER_CRE 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800882#define RCER_RES ~(RCER_CRE)
883
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200884/*
885 * SPMR - System PLL Mode Register
Dave Liue0803132006-12-07 21:11:58 +0800886 */
887#define SPMR_LBIUCM 0x80000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100888#define SPMR_LBIUCM_SHIFT 31
Dave Liue0803132006-12-07 21:11:58 +0800889#define SPMR_DDRCM 0x40000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100890#define SPMR_DDRCM_SHIFT 30
Dave Liue0803132006-12-07 21:11:58 +0800891#define SPMR_SPMF 0x0F000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100892#define SPMR_SPMF_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800893#define SPMR_CKID 0x00800000
894#define SPMR_CKID_SHIFT 23
895#define SPMR_COREPLL 0x007F0000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100896#define SPMR_COREPLL_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800897#define SPMR_CEVCOD 0x000000C0
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100898#define SPMR_CEVCOD_SHIFT 6
Dave Liue0803132006-12-07 21:11:58 +0800899#define SPMR_CEPDF 0x00000020
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100900#define SPMR_CEPDF_SHIFT 5
Dave Liue0803132006-12-07 21:11:58 +0800901#define SPMR_CEPMF 0x0000001F
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100902#define SPMR_CEPMF_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800903
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200904/*
905 * OCCR - Output Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +0800906 */
907#define OCCR_PCICOE0 0x80000000
908#define OCCR_PCICOE1 0x40000000
909#define OCCR_PCICOE2 0x20000000
910#define OCCR_PCICOE3 0x10000000
911#define OCCR_PCICOE4 0x08000000
912#define OCCR_PCICOE5 0x04000000
913#define OCCR_PCICOE6 0x02000000
914#define OCCR_PCICOE7 0x01000000
915#define OCCR_PCICD0 0x00800000
916#define OCCR_PCICD1 0x00400000
917#define OCCR_PCICD2 0x00200000
918#define OCCR_PCICD3 0x00100000
919#define OCCR_PCICD4 0x00080000
920#define OCCR_PCICD5 0x00040000
921#define OCCR_PCICD6 0x00020000
922#define OCCR_PCICD7 0x00010000
923#define OCCR_PCI1CR 0x00000002
924#define OCCR_PCI2CR 0x00000001
925#define OCCR_PCICR OCCR_PCI1CR
926
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200927/*
928 * SCCR - System Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +0800929 */
930#define SCCR_ENCCM 0x03000000
931#define SCCR_ENCCM_SHIFT 24
932#define SCCR_ENCCM_0 0x00000000
933#define SCCR_ENCCM_1 0x01000000
934#define SCCR_ENCCM_2 0x02000000
935#define SCCR_ENCCM_3 0x03000000
936
937#define SCCR_PCICM 0x00010000
938#define SCCR_PCICM_SHIFT 16
939
Peter Tyser2c7920a2009-05-22 17:23:25 -0500940#if defined(CONFIG_MPC834x)
Dave Liu03051c32007-09-18 12:36:11 +0800941/* SCCR bits - MPC834x specific */
Dave Liue0803132006-12-07 21:11:58 +0800942#define SCCR_TSEC1CM 0xc0000000
943#define SCCR_TSEC1CM_SHIFT 30
944#define SCCR_TSEC1CM_0 0x00000000
945#define SCCR_TSEC1CM_1 0x40000000
946#define SCCR_TSEC1CM_2 0x80000000
947#define SCCR_TSEC1CM_3 0xC0000000
948
949#define SCCR_TSEC2CM 0x30000000
950#define SCCR_TSEC2CM_SHIFT 28
951#define SCCR_TSEC2CM_0 0x00000000
952#define SCCR_TSEC2CM_1 0x10000000
953#define SCCR_TSEC2CM_2 0x20000000
954#define SCCR_TSEC2CM_3 0x30000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500955
Dave Liu03051c32007-09-18 12:36:11 +0800956/* The MPH must have the same clock ratio as DR, unless its clock disabled */
957#define SCCR_USBMPHCM 0x00c00000
958#define SCCR_USBMPHCM_SHIFT 22
959#define SCCR_USBDRCM 0x00300000
960#define SCCR_USBDRCM_SHIFT 20
961#define SCCR_USBCM 0x00f00000
962#define SCCR_USBCM_SHIFT 20
963#define SCCR_USBCM_0 0x00000000
964#define SCCR_USBCM_1 0x00500000
965#define SCCR_USBCM_2 0x00A00000
966#define SCCR_USBCM_3 0x00F00000
967
Dave Liu555da612007-09-18 12:36:58 +0800968#elif defined(CONFIG_MPC8313)
Dave Liua8cb43a2008-01-17 18:23:19 +0800969/* TSEC1 bits are for TSEC2 as well */
Scott Woodd87c57b2007-04-16 14:31:55 -0500970#define SCCR_TSEC1CM 0xc0000000
971#define SCCR_TSEC1CM_SHIFT 30
Kim Phillips9e896472008-01-16 12:06:16 -0600972#define SCCR_TSEC1CM_0 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500973#define SCCR_TSEC1CM_1 0x40000000
974#define SCCR_TSEC1CM_2 0x80000000
975#define SCCR_TSEC1CM_3 0xC0000000
976
977#define SCCR_TSEC1ON 0x20000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500978#define SCCR_TSEC1ON_SHIFT 29
Scott Woodd87c57b2007-04-16 14:31:55 -0500979#define SCCR_TSEC2ON 0x10000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500980#define SCCR_TSEC2ON_SHIFT 28
Scott Woodd87c57b2007-04-16 14:31:55 -0500981
Dave Liue0803132006-12-07 21:11:58 +0800982#define SCCR_USBDRCM 0x00300000
983#define SCCR_USBDRCM_SHIFT 20
Dave Liu03051c32007-09-18 12:36:11 +0800984#define SCCR_USBDRCM_0 0x00000000
985#define SCCR_USBDRCM_1 0x00100000
986#define SCCR_USBDRCM_2 0x00200000
987#define SCCR_USBDRCM_3 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800988
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400989#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
990/* SCCR bits - MPC8315/MPC8308 specific */
Dave Liu555da612007-09-18 12:36:58 +0800991#define SCCR_TSEC1CM 0xc0000000
992#define SCCR_TSEC1CM_SHIFT 30
993#define SCCR_TSEC1CM_0 0x00000000
994#define SCCR_TSEC1CM_1 0x40000000
995#define SCCR_TSEC1CM_2 0x80000000
996#define SCCR_TSEC1CM_3 0xC0000000
997
998#define SCCR_TSEC2CM 0x30000000
999#define SCCR_TSEC2CM_SHIFT 28
1000#define SCCR_TSEC2CM_0 0x00000000
1001#define SCCR_TSEC2CM_1 0x10000000
1002#define SCCR_TSEC2CM_2 0x20000000
1003#define SCCR_TSEC2CM_3 0x30000000
1004
Ilya Yanok7c619dd2010-06-28 16:44:33 +04001005#define SCCR_SDHCCM 0x0c000000
1006#define SCCR_SDHCCM_SHIFT 26
1007#define SCCR_SDHCCM_0 0x00000000
1008#define SCCR_SDHCCM_1 0x04000000
1009#define SCCR_SDHCCM_2 0x08000000
1010#define SCCR_SDHCCM_3 0x0c000000
1011
Dave Liu6f3931a2008-01-10 23:06:05 +08001012#define SCCR_USBDRCM 0x00c00000
1013#define SCCR_USBDRCM_SHIFT 22
Dave Liu555da612007-09-18 12:36:58 +08001014#define SCCR_USBDRCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +08001015#define SCCR_USBDRCM_1 0x00400000
1016#define SCCR_USBDRCM_2 0x00800000
1017#define SCCR_USBDRCM_3 0x00c00000
Dave Liu555da612007-09-18 12:36:58 +08001018
Dave Liu6f3931a2008-01-10 23:06:05 +08001019#define SCCR_SATA1CM 0x00003000
1020#define SCCR_SATA1CM_SHIFT 12
1021#define SCCR_SATACM 0x00003c00
1022#define SCCR_SATACM_SHIFT 10
Dave Liu555da612007-09-18 12:36:58 +08001023#define SCCR_SATACM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +08001024#define SCCR_SATACM_1 0x00001400
1025#define SCCR_SATACM_2 0x00002800
1026#define SCCR_SATACM_3 0x00003c00
Dave Liu555da612007-09-18 12:36:58 +08001027
Dave Liu6f3931a2008-01-10 23:06:05 +08001028#define SCCR_TDMCM 0x00000030
1029#define SCCR_TDMCM_SHIFT 4
Dave Liu555da612007-09-18 12:36:58 +08001030#define SCCR_TDMCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +08001031#define SCCR_TDMCM_1 0x00000010
1032#define SCCR_TDMCM_2 0x00000020
1033#define SCCR_TDMCM_3 0x00000030
Dave Liu555da612007-09-18 12:36:58 +08001034
Peter Tyser2c7920a2009-05-22 17:23:25 -05001035#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +08001036/* SCCR bits - MPC837x specific */
1037#define SCCR_TSEC1CM 0xc0000000
1038#define SCCR_TSEC1CM_SHIFT 30
1039#define SCCR_TSEC1CM_0 0x00000000
1040#define SCCR_TSEC1CM_1 0x40000000
1041#define SCCR_TSEC1CM_2 0x80000000
1042#define SCCR_TSEC1CM_3 0xC0000000
1043
1044#define SCCR_TSEC2CM 0x30000000
1045#define SCCR_TSEC2CM_SHIFT 28
1046#define SCCR_TSEC2CM_0 0x00000000
1047#define SCCR_TSEC2CM_1 0x10000000
1048#define SCCR_TSEC2CM_2 0x20000000
1049#define SCCR_TSEC2CM_3 0x30000000
1050
1051#define SCCR_SDHCCM 0x0c000000
1052#define SCCR_SDHCCM_SHIFT 26
1053#define SCCR_SDHCCM_0 0x00000000
1054#define SCCR_SDHCCM_1 0x04000000
1055#define SCCR_SDHCCM_2 0x08000000
1056#define SCCR_SDHCCM_3 0x0c000000
1057
1058#define SCCR_USBDRCM 0x00c00000
1059#define SCCR_USBDRCM_SHIFT 22
1060#define SCCR_USBDRCM_0 0x00000000
1061#define SCCR_USBDRCM_1 0x00400000
1062#define SCCR_USBDRCM_2 0x00800000
1063#define SCCR_USBDRCM_3 0x00c00000
1064
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001065/* All of the four SATA controllers must have the same clock ratio */
1066#define SCCR_SATA1CM 0x000000c0
1067#define SCCR_SATA1CM_SHIFT 6
1068#define SCCR_SATACM 0x000000ff
1069#define SCCR_SATACM_SHIFT 0
1070#define SCCR_SATACM_0 0x00000000
1071#define SCCR_SATACM_1 0x00000055
1072#define SCCR_SATACM_2 0x000000aa
1073#define SCCR_SATACM_3 0x000000ff
Gerlando Falautoa88731a2012-10-10 22:13:08 +00001074#elif defined(CONFIG_MPC8309)
1075/* SCCR bits - MPC8309 specific */
1076#define SCCR_SDHCCM 0x0c000000
1077#define SCCR_SDHCCM_SHIFT 26
1078#define SCCR_SDHCCM_0 0x00000000
1079#define SCCR_SDHCCM_1 0x04000000
1080#define SCCR_SDHCCM_2 0x08000000
1081#define SCCR_SDHCCM_3 0x0c000000
1082
1083#define SCCR_USBDRCM 0x00c00000
1084#define SCCR_USBDRCM_SHIFT 22
1085#define SCCR_USBDRCM_0 0x00000000
1086#define SCCR_USBDRCM_1 0x00400000
1087#define SCCR_USBDRCM_2 0x00800000
1088#define SCCR_USBDRCM_3 0x00c00000
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001089#endif
1090
Dave Liu03051c32007-09-18 12:36:11 +08001091#define SCCR_PCIEXP1CM 0x00300000
1092#define SCCR_PCIEXP1CM_SHIFT 20
1093#define SCCR_PCIEXP1CM_0 0x00000000
1094#define SCCR_PCIEXP1CM_1 0x00100000
1095#define SCCR_PCIEXP1CM_2 0x00200000
1096#define SCCR_PCIEXP1CM_3 0x00300000
1097
1098#define SCCR_PCIEXP2CM 0x000c0000
1099#define SCCR_PCIEXP2CM_SHIFT 18
1100#define SCCR_PCIEXP2CM_0 0x00000000
1101#define SCCR_PCIEXP2CM_1 0x00040000
1102#define SCCR_PCIEXP2CM_2 0x00080000
1103#define SCCR_PCIEXP2CM_3 0x000c0000
1104
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001105/*
1106 * CSn_BDNS - Chip Select memory Bounds Register
Dave Liue0803132006-12-07 21:11:58 +08001107 */
1108#define CSBNDS_SA 0x00FF0000
1109#define CSBNDS_SA_SHIFT 8
1110#define CSBNDS_EA 0x000000FF
1111#define CSBNDS_EA_SHIFT 24
1112
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001113/*
1114 * CSn_CONFIG - Chip Select Configuration Register
Dave Liue0803132006-12-07 21:11:58 +08001115 */
1116#define CSCONFIG_EN 0x80000000
1117#define CSCONFIG_AP 0x00800000
Gerlando Falauto8afad912012-10-10 22:13:07 +00001118#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
Joe Hershberger2fef4022011-10-11 23:57:29 -05001119#define CSCONFIG_ODT_RD_NEVER 0x00000000
1120#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
1121#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
1122#define CSCONFIG_ODT_RD_ALL 0x00400000
1123#define CSCONFIG_ODT_WR_NEVER 0x00000000
1124#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
1125#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
1126#define CSCONFIG_ODT_WR_ALL 0x00040000
1127#elif defined(CONFIG_MPC832x)
1128#define CSCONFIG_ODT_RD_CFG 0x00400000
Heiko Schocher6d2c26a2009-08-21 16:30:30 -05001129#define CSCONFIG_ODT_WR_CFG 0x00040000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001130#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
1131#define CSCONFIG_ODT_RD_NEVER 0x00000000
1132#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
1133#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
1134#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
1135#define CSCONFIG_ODT_RD_ALL 0x00400000
1136#define CSCONFIG_ODT_WR_NEVER 0x00000000
1137#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
1138#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
1139#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
1140#define CSCONFIG_ODT_WR_ALL 0x00040000
Heiko Schocher6d2c26a2009-08-21 16:30:30 -05001141#endif
Tor Krilld82b4fc2008-06-02 15:09:30 +02001142#define CSCONFIG_BANK_BIT_3 0x00004000
Dave Liue0803132006-12-07 21:11:58 +08001143#define CSCONFIG_ROW_BIT 0x00000700
1144#define CSCONFIG_ROW_BIT_12 0x00000000
1145#define CSCONFIG_ROW_BIT_13 0x00000100
1146#define CSCONFIG_ROW_BIT_14 0x00000200
1147#define CSCONFIG_COL_BIT 0x00000007
1148#define CSCONFIG_COL_BIT_8 0x00000000
1149#define CSCONFIG_COL_BIT_9 0x00000001
1150#define CSCONFIG_COL_BIT_10 0x00000002
1151#define CSCONFIG_COL_BIT_11 0x00000003
1152
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001153/*
1154 * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
Scott Woodd87c57b2007-04-16 14:31:55 -05001155 */
1156#define TIMING_CFG0_RWT 0xC0000000
1157#define TIMING_CFG0_RWT_SHIFT 30
1158#define TIMING_CFG0_WRT 0x30000000
1159#define TIMING_CFG0_WRT_SHIFT 28
1160#define TIMING_CFG0_RRT 0x0C000000
1161#define TIMING_CFG0_RRT_SHIFT 26
1162#define TIMING_CFG0_WWT 0x03000000
1163#define TIMING_CFG0_WWT_SHIFT 24
1164#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
1165#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
1166#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
1167#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
1168#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
1169#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
Anton Vorontsovd892b2d2008-03-24 20:46:57 +03001170#define TIMING_CFG0_MRS_CYC 0x0000000F
Scott Woodd87c57b2007-04-16 14:31:55 -05001171#define TIMING_CFG0_MRS_CYC_SHIFT 0
1172
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001173/*
1174 * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
Dave Liue0803132006-12-07 21:11:58 +08001175 */
1176#define TIMING_CFG1_PRETOACT 0x70000000
1177#define TIMING_CFG1_PRETOACT_SHIFT 28
1178#define TIMING_CFG1_ACTTOPRE 0x0F000000
1179#define TIMING_CFG1_ACTTOPRE_SHIFT 24
1180#define TIMING_CFG1_ACTTORW 0x00700000
1181#define TIMING_CFG1_ACTTORW_SHIFT 20
1182#define TIMING_CFG1_CASLAT 0x00070000
1183#define TIMING_CFG1_CASLAT_SHIFT 16
1184#define TIMING_CFG1_REFREC 0x0000F000
1185#define TIMING_CFG1_REFREC_SHIFT 12
1186#define TIMING_CFG1_WRREC 0x00000700
1187#define TIMING_CFG1_WRREC_SHIFT 8
1188#define TIMING_CFG1_ACTTOACT 0x00000070
1189#define TIMING_CFG1_ACTTOACT_SHIFT 4
1190#define TIMING_CFG1_WRTORD 0x00000007
1191#define TIMING_CFG1_WRTORD_SHIFT 0
1192#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
1193#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
Heiko Schocherfacdad52008-11-19 10:10:30 +01001194#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
1195#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
1196#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
Heiko Schocher2b68b232009-02-11 19:26:15 +01001197#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
1198#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
Dave Liue0803132006-12-07 21:11:58 +08001199
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001200/*
1201 * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
Dave Liue0803132006-12-07 21:11:58 +08001202 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +08001203#define TIMING_CFG2_CPO 0x0F800000
1204#define TIMING_CFG2_CPO_SHIFT 23
Dave Liue0803132006-12-07 21:11:58 +08001205#define TIMING_CFG2_ACSM 0x00080000
1206#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
1207#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001208/* default (= CASLAT + 1) */
1209#define TIMING_CFG2_CPO_DEF 0x00000000
Dave Liue0803132006-12-07 21:11:58 +08001210
Scott Woodd87c57b2007-04-16 14:31:55 -05001211#define TIMING_CFG2_ADD_LAT 0x70000000
1212#define TIMING_CFG2_ADD_LAT_SHIFT 28
1213#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
1214#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
1215#define TIMING_CFG2_RD_TO_PRE 0x0000E000
1216#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
1217#define TIMING_CFG2_CKE_PLS 0x000001C0
1218#define TIMING_CFG2_CKE_PLS_SHIFT 6
1219#define TIMING_CFG2_FOUR_ACT 0x0000003F
1220#define TIMING_CFG2_FOUR_ACT_SHIFT 0
1221
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001222/*
Heiko Schocherf1ccd102011-09-26 13:36:54 +02001223 * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1224 */
1225#define TIMING_CFG3_EXT_REFREC 0x00070000
1226#define TIMING_CFG3_EXT_REFREC_SHIFT 16
1227
1228/*
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001229 * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
Dave Liue0803132006-12-07 21:11:58 +08001230 */
1231#define SDRAM_CFG_MEM_EN 0x80000000
1232#define SDRAM_CFG_SREN 0x40000000
1233#define SDRAM_CFG_ECC_EN 0x20000000
1234#define SDRAM_CFG_RD_EN 0x10000000
Kim Phillipsbbea46f2007-08-16 22:52:48 -05001235#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
1236#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
1237#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
Dave Liue0803132006-12-07 21:11:58 +08001238#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
1239#define SDRAM_CFG_DYN_PWR 0x00200000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001240#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
1241#define SDRAM_CFG_DBW_MASK 0x00180000
1242#define SDRAM_CFG_DBW_16 0x00100000
1243#define SDRAM_CFG_DBW_32 0x00080000
1244#else
Dave Liue0803132006-12-07 21:11:58 +08001245#define SDRAM_CFG_32_BE 0x00080000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001246#endif
1247#if !defined(CONFIG_MPC8308)
Dave Liue0803132006-12-07 21:11:58 +08001248#define SDRAM_CFG_8_BE 0x00040000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001249#endif
Dave Liue0803132006-12-07 21:11:58 +08001250#define SDRAM_CFG_NCAP 0x00020000
1251#define SDRAM_CFG_2T_EN 0x00008000
Andre Schwarza7b81262011-04-14 14:53:37 +02001252#define SDRAM_CFG_HSE 0x00000008
Scott Woodd87c57b2007-04-16 14:31:55 -05001253#define SDRAM_CFG_BI 0x00000001
Dave Liue0803132006-12-07 21:11:58 +08001254
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001255/*
1256 * DDR_SDRAM_MODE - DDR SDRAM Mode Register
Dave Liue0803132006-12-07 21:11:58 +08001257 */
1258#define SDRAM_MODE_ESD 0xFFFF0000
1259#define SDRAM_MODE_ESD_SHIFT 16
1260#define SDRAM_MODE_SD 0x0000FFFF
1261#define SDRAM_MODE_SD_SHIFT 0
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001262/* select extended mode reg */
1263#define DDR_MODE_EXT_MODEREG 0x4000
1264/* operating mode, mask */
1265#define DDR_MODE_EXT_OPMODE 0x3FF8
Dave Liue0803132006-12-07 21:11:58 +08001266#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001267/* QFC / compatibility, mask */
1268#define DDR_MODE_QFC 0x0004
1269/* compatible to older SDRAMs */
1270#define DDR_MODE_QFC_COMP 0x0000
1271/* weak drivers */
1272#define DDR_MODE_WEAK 0x0002
1273/* disable DLL */
1274#define DDR_MODE_DLL_DIS 0x0001
1275/* CAS latency, mask */
1276#define DDR_MODE_CASLAT 0x0070
Dave Liue0803132006-12-07 21:11:58 +08001277#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
1278#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
1279#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
1280#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001281/* sequential burst */
1282#define DDR_MODE_BTYPE_SEQ 0x0000
1283/* interleaved burst */
1284#define DDR_MODE_BTYPE_ILVD 0x0008
Dave Liue0803132006-12-07 21:11:58 +08001285#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
1286#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001287/* exact value for 7.8125us */
1288#define DDR_REFINT_166MHZ_7US 1302
1289/* use 256 cycles as a starting point */
1290#define DDR_BSTOPRE 256
1291/* select mode register */
1292#define DDR_MODE_MODEREG 0x0000
Dave Liue0803132006-12-07 21:11:58 +08001293
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001294/*
1295 * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
Dave Liue0803132006-12-07 21:11:58 +08001296 */
1297#define SDRAM_INTERVAL_REFINT 0x3FFF0000
1298#define SDRAM_INTERVAL_REFINT_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +08001299#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
1300
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001301/*
1302 * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +08001303 */
1304#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
1305#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
1306#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
1307#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
1308#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
1309
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001310/*
1311 * ECC_ERR_INJECT - Memory data path error injection mask ECC
Dave Liue0803132006-12-07 21:11:58 +08001312 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001313/* ECC Mirror Byte */
1314#define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
1315/* Error Injection Enable */
1316#define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
1317/* ECC Erroe Injection Enable */
1318#define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001319#define ECC_ERR_INJECT_EEIM_SHIFT 0
1320
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001321/*
1322 * CAPTURE_ECC - Memory data path read capture ECC
Dave Liue0803132006-12-07 21:11:58 +08001323 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001324#define CAPTURE_ECC_ECE (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001325#define CAPTURE_ECC_ECE_SHIFT 0
1326
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001327/*
1328 * ERR_DETECT - Memory error detect
Dave Liue0803132006-12-07 21:11:58 +08001329 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001330/* Multiple Memory Errors */
1331#define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
1332/* Multiple-Bit Error */
1333#define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
1334/* Single-Bit ECC Error Pickup */
1335#define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
1336/* Memory Select Error */
1337#define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
Dave Liue0803132006-12-07 21:11:58 +08001338
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001339/*
1340 * ERR_DISABLE - Memory error disable
Dave Liue0803132006-12-07 21:11:58 +08001341 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001342/* Multiple-Bit ECC Error Disable */
1343#define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
1344/* Sinle-Bit ECC Error disable */
1345#define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
1346/* Memory Select Error Disable */
1347#define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
1348#define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
1349 ECC_ERROR_DISABLE_SBED | \
1350 ECC_ERROR_DISABLE_MBED))
1351
1352/*
1353 * ERR_INT_EN - Memory error interrupt enable
Dave Liue0803132006-12-07 21:11:58 +08001354 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001355/* Multiple-Bit ECC Error Interrupt Enable */
1356#define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
1357/* Single-Bit ECC Error Interrupt Enable */
1358#define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
1359/* Memory Select Error Interrupt Enable */
1360#define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
1361#define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
1362 ECC_ERR_INT_EN_SBEE | \
1363 ECC_ERR_INT_EN_MSEE))
1364
1365/*
1366 * CAPTURE_ATTRIBUTES - Memory error attributes capture
Dave Liue0803132006-12-07 21:11:58 +08001367 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001368/* Data Beat Num */
1369#define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
Dave Liue0803132006-12-07 21:11:58 +08001370#define ECC_CAPT_ATTR_BNUM_SHIFT 28
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001371/* Transaction Size */
1372#define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
Dave Liue0803132006-12-07 21:11:58 +08001373#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
1374#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
1375#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
1376#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
1377#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001378/* Transaction Source */
1379#define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
Dave Liue0803132006-12-07 21:11:58 +08001380#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1381#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1382#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
1383#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
1384#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
1385#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
1386#define ECC_CAPT_ATTR_TSRC_I2C 0x9
1387#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
1388#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
1389#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
1390#define ECC_CAPT_ATTR_TSRC_DMA 0xF
1391#define ECC_CAPT_ATTR_TSRC_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001392/* Transaction Type */
1393#define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
Dave Liue0803132006-12-07 21:11:58 +08001394#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
1395#define ECC_CAPT_ATTR_TTYP_READ 0x2
1396#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
1397#define ECC_CAPT_ATTR_TTYP_SHIFT 12
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001398#define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
Dave Liue0803132006-12-07 21:11:58 +08001399
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001400/*
1401 * ERR_SBE - Single bit ECC memory error management
Dave Liue0803132006-12-07 21:11:58 +08001402 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001403/* Single-Bit Error Threshold 0..255 */
1404#define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
Dave Liue0803132006-12-07 21:11:58 +08001405#define ECC_ERROR_MAN_SBET_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001406/* Single Bit Error Counter 0..255 */
1407#define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001408#define ECC_ERROR_MAN_SBEC_SHIFT 0
1409
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001410/*
1411 * CONFIG_ADDRESS - PCI Config Address Register
Dave Liue0803132006-12-07 21:11:58 +08001412 */
1413#define PCI_CONFIG_ADDRESS_EN 0x80000000
1414#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1415#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1416#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1417#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1418#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1419#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1420#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1421#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
Dave Liu5f820432006-11-03 19:33:44 -06001422
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001423/*
1424 * POTAR - PCI Outbound Translation Address Register
Dave Liue0803132006-12-07 21:11:58 +08001425 */
1426#define POTAR_TA_MASK 0x000fffff
1427
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001428/*
1429 * POBAR - PCI Outbound Base Address Register
Dave Liue0803132006-12-07 21:11:58 +08001430 */
1431#define POBAR_BA_MASK 0x000fffff
1432
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001433/*
1434 * POCMR - PCI Outbound Comparision Mask Register
Dave Liue0803132006-12-07 21:11:58 +08001435 */
1436#define POCMR_EN 0x80000000
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001437/* 0-memory space 1-I/O space */
1438#define POCMR_IO 0x40000000
Dave Liue0803132006-12-07 21:11:58 +08001439#define POCMR_SE 0x20000000 /* streaming enable */
1440#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1441#define POCMR_CM_MASK 0x000fffff
1442#define POCMR_CM_4G 0x00000000
1443#define POCMR_CM_2G 0x00080000
1444#define POCMR_CM_1G 0x000C0000
1445#define POCMR_CM_512M 0x000E0000
1446#define POCMR_CM_256M 0x000F0000
1447#define POCMR_CM_128M 0x000F8000
1448#define POCMR_CM_64M 0x000FC000
1449#define POCMR_CM_32M 0x000FE000
1450#define POCMR_CM_16M 0x000FF000
1451#define POCMR_CM_8M 0x000FF800
1452#define POCMR_CM_4M 0x000FFC00
1453#define POCMR_CM_2M 0x000FFE00
1454#define POCMR_CM_1M 0x000FFF00
1455#define POCMR_CM_512K 0x000FFF80
1456#define POCMR_CM_256K 0x000FFFC0
1457#define POCMR_CM_128K 0x000FFFE0
1458#define POCMR_CM_64K 0x000FFFF0
1459#define POCMR_CM_32K 0x000FFFF8
1460#define POCMR_CM_16K 0x000FFFFC
1461#define POCMR_CM_8K 0x000FFFFE
1462#define POCMR_CM_4K 0x000FFFFF
1463
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001464/*
1465 * PITAR - PCI Inbound Translation Address Register
Dave Liue0803132006-12-07 21:11:58 +08001466 */
1467#define PITAR_TA_MASK 0x000fffff
1468
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001469/*
1470 * PIBAR - PCI Inbound Base/Extended Address Register
Dave Liue0803132006-12-07 21:11:58 +08001471 */
1472#define PIBAR_MASK 0xffffffff
1473#define PIEBAR_EBA_MASK 0x000fffff
1474
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001475/*
1476 * PIWAR - PCI Inbound Windows Attributes Register
Dave Liue0803132006-12-07 21:11:58 +08001477 */
1478#define PIWAR_EN 0x80000000
1479#define PIWAR_PF 0x20000000
1480#define PIWAR_RTT_MASK 0x000f0000
1481#define PIWAR_RTT_NO_SNOOP 0x00040000
1482#define PIWAR_RTT_SNOOP 0x00050000
1483#define PIWAR_WTT_MASK 0x0000f000
1484#define PIWAR_WTT_NO_SNOOP 0x00004000
1485#define PIWAR_WTT_SNOOP 0x00005000
1486#define PIWAR_IWS_MASK 0x0000003F
1487#define PIWAR_IWS_4K 0x0000000B
1488#define PIWAR_IWS_8K 0x0000000C
1489#define PIWAR_IWS_16K 0x0000000D
1490#define PIWAR_IWS_32K 0x0000000E
1491#define PIWAR_IWS_64K 0x0000000F
1492#define PIWAR_IWS_128K 0x00000010
1493#define PIWAR_IWS_256K 0x00000011
1494#define PIWAR_IWS_512K 0x00000012
1495#define PIWAR_IWS_1M 0x00000013
1496#define PIWAR_IWS_2M 0x00000014
1497#define PIWAR_IWS_4M 0x00000015
1498#define PIWAR_IWS_8M 0x00000016
1499#define PIWAR_IWS_16M 0x00000017
1500#define PIWAR_IWS_32M 0x00000018
1501#define PIWAR_IWS_64M 0x00000019
1502#define PIWAR_IWS_128M 0x0000001A
1503#define PIWAR_IWS_256M 0x0000001B
1504#define PIWAR_IWS_512M 0x0000001C
1505#define PIWAR_IWS_1G 0x0000001D
1506#define PIWAR_IWS_2G 0x0000001E
Dave Liuf6eda7f2006-10-25 14:41:21 -05001507
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001508/*
1509 * PMCCR1 - PCI Configuration Register 1
Scott Woodd87c57b2007-04-16 14:31:55 -05001510 */
1511#define PMCCR1_POWER_OFF 0x00000020
1512
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001513/*
1514 * DDRCDR - DDR Control Driver Register
Scott Woodd87c57b2007-04-16 14:31:55 -05001515 */
Kim Phillips9e896472008-01-16 12:06:16 -06001516#define DDRCDR_DHC_EN 0x80000000
Scott Woodd87c57b2007-04-16 14:31:55 -05001517#define DDRCDR_EN 0x40000000
1518#define DDRCDR_PZ 0x3C000000
1519#define DDRCDR_PZ_MAXZ 0x00000000
1520#define DDRCDR_PZ_HIZ 0x20000000
1521#define DDRCDR_PZ_NOMZ 0x30000000
1522#define DDRCDR_PZ_LOZ 0x38000000
1523#define DDRCDR_PZ_MINZ 0x3C000000
1524#define DDRCDR_NZ 0x3C000000
1525#define DDRCDR_NZ_MAXZ 0x00000000
1526#define DDRCDR_NZ_HIZ 0x02000000
1527#define DDRCDR_NZ_NOMZ 0x03000000
1528#define DDRCDR_NZ_LOZ 0x03800000
1529#define DDRCDR_NZ_MINZ 0x03C00000
1530#define DDRCDR_ODT 0x00080000
1531#define DDRCDR_DDR_CFG 0x00040000
1532#define DDRCDR_M_ODR 0x00000002
1533#define DDRCDR_Q_DRN 0x00000001
1534
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001535/*
1536 * PCIE Bridge Register
1537 */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001538#define PEX_CSB_CTRL_OBPIOE 0x00000001
1539#define PEX_CSB_CTRL_IBPIOE 0x00000002
1540#define PEX_CSB_CTRL_WDMAE 0x00000004
1541#define PEX_CSB_CTRL_RDMAE 0x00000008
1542
1543#define PEX_CSB_OBCTRL_PIOE 0x00000001
1544#define PEX_CSB_OBCTRL_MEMWE 0x00000002
1545#define PEX_CSB_OBCTRL_IOWE 0x00000004
1546#define PEX_CSB_OBCTRL_CFGWE 0x00000008
1547
1548#define PEX_CSB_IBCTRL_PIOE 0x00000001
1549
1550#define PEX_OWAR_EN 0x00000001
1551#define PEX_OWAR_TYPE_CFG 0x00000000
1552#define PEX_OWAR_TYPE_IO 0x00000002
1553#define PEX_OWAR_TYPE_MEM 0x00000004
1554#define PEX_OWAR_RLXO 0x00000008
1555#define PEX_OWAR_NANP 0x00000010
1556#define PEX_OWAR_SIZE 0xFFFFF000
1557
1558#define PEX_IWAR_EN 0x00000001
1559#define PEX_IWAR_TYPE_INT 0x00000000
1560#define PEX_IWAR_TYPE_PF 0x00000004
1561#define PEX_IWAR_TYPE_NO_PF 0x00000006
1562#define PEX_IWAR_NSOV 0x00000008
1563#define PEX_IWAR_NSNP 0x00000010
1564#define PEX_IWAR_SIZE 0xFFFFF000
1565#define PEX_IWAR_SIZE_1M 0x000FF000
1566#define PEX_IWAR_SIZE_2M 0x001FF000
1567#define PEX_IWAR_SIZE_4M 0x003FF000
1568#define PEX_IWAR_SIZE_8M 0x007FF000
1569#define PEX_IWAR_SIZE_16M 0x00FFF000
1570#define PEX_IWAR_SIZE_32M 0x01FFF000
1571#define PEX_IWAR_SIZE_64M 0x03FFF000
1572#define PEX_IWAR_SIZE_128M 0x07FFF000
1573#define PEX_IWAR_SIZE_256M 0x0FFFF000
1574
1575#define PEX_GCLK_RATIO 0x440
1576
Scott Wood49ea3b62007-04-16 14:34:21 -05001577#ifndef __ASSEMBLY__
1578struct pci_region;
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001579void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
Ira Snyder75f35202009-01-12 13:32:26 -08001580void mpc83xx_pcislave_unlock(int bus);
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001581void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
Scott Wood49ea3b62007-04-16 14:34:21 -05001582#endif
1583
Eran Libertyf046ccd2005-07-28 10:08:46 -05001584#endif /* __MPC83XX_H__ */