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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Ilya Yanok7c619dd2010-06-28 16:44:33 +04002 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
Eran Libertyf046ccd2005-07-28 10:08:46 -050011 */
12
Eran Libertyf046ccd2005-07-28 10:08:46 -050013#ifndef __MPC83XX_H__
14#define __MPC83XX_H__
15
Dave Liuf6eda7f2006-10-25 14:41:21 -050016#include <config.h>
Anton Vorontsovbf30bb12008-05-28 18:20:15 +040017#include <asm/fsl_lbc.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050018#if defined(CONFIG_E300)
19#include <asm/e300.h>
20#endif
21
Dave Liue0803132006-12-07 21:11:58 +080022/* MPC83xx cpu provide RCR register to do reset thing specially
Eran Libertyf046ccd2005-07-28 10:08:46 -050023 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050024#define MPC83xx_RESET
25
Dave Liue0803132006-12-07 21:11:58 +080026/* System reset offset (PowerPC standard)
Eran Libertyf046ccd2005-07-28 10:08:46 -050027 */
Dave Liue0803132006-12-07 21:11:58 +080028#define EXC_OFF_SYS_RESET 0x0100
Rafal Jaworowski02032e82007-06-22 14:58:04 +020029#define _START_OFFSET EXC_OFF_SYS_RESET
Eran Libertyf046ccd2005-07-28 10:08:46 -050030
Dave Liue0803132006-12-07 21:11:58 +080031/* IMMRBAR - Internal Memory Register Base Address
Eran Libertyf046ccd2005-07-28 10:08:46 -050032 */
Scott Woode4c09502008-06-30 14:13:28 -050033#ifndef CONFIG_DEFAULT_IMMR
Dave Liue0803132006-12-07 21:11:58 +080034#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
Scott Woode4c09502008-06-30 14:13:28 -050035#endif
Dave Liue0803132006-12-07 21:11:58 +080036#define IMMRBAR 0x0000 /* Register offset to immr */
37#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
38#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
Eran Libertyf046ccd2005-07-28 10:08:46 -050039
Dave Liue0803132006-12-07 21:11:58 +080040/* LAWBAR - Local Access Window Base Address Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050041 */
Dave Liue0803132006-12-07 21:11:58 +080042#define LBLAWBAR0 0x0020 /* Register offset to immr */
43#define LBLAWAR0 0x0024
44#define LBLAWBAR1 0x0028
45#define LBLAWAR1 0x002C
46#define LBLAWBAR2 0x0030
47#define LBLAWAR2 0x0034
48#define LBLAWBAR3 0x0038
49#define LBLAWAR3 0x003C
50#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
Eran Libertyf046ccd2005-07-28 10:08:46 -050051
Dave Liue0803132006-12-07 21:11:58 +080052/* SPRIDR - System Part and Revision ID Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050053 */
Kim Phillipse5c4ade2008-03-28 10:19:07 -050054#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
55#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
Eran Libertyf046ccd2005-07-28 10:08:46 -050056
Peter Tyser2c7920a2009-05-22 17:23:25 -050057#if defined(CONFIG_MPC834x)
Kim Phillipse5c4ade2008-03-28 10:19:07 -050058#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
59#define REVID_MINOR(spridr) (spridr & 0x000000FF)
60#else
61#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
62#define REVID_MINOR(spridr) (spridr & 0x0000000F)
63#endif
Dave Liue0803132006-12-07 21:11:58 +080064
Kim Phillipse5c4ade2008-03-28 10:19:07 -050065#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
Kim Phillips6b70ffb2008-06-16 15:55:53 -050066#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
Dave Liue0803132006-12-07 21:11:58 +080067
Ilya Yanok7c619dd2010-06-28 16:44:33 +040068#define SPR_8308 0x8100
Kim Phillips6b70ffb2008-06-16 15:55:53 -050069#define SPR_831X_FAMILY 0x80B
Kim Phillipse5c4ade2008-03-28 10:19:07 -050070#define SPR_8311 0x80B2
71#define SPR_8313 0x80B0
72#define SPR_8314 0x80B6
73#define SPR_8315 0x80B4
Kim Phillips6b70ffb2008-06-16 15:55:53 -050074#define SPR_832X_FAMILY 0x806
Kim Phillipse5c4ade2008-03-28 10:19:07 -050075#define SPR_8321 0x8066
76#define SPR_8323 0x8062
Kim Phillips6b70ffb2008-06-16 15:55:53 -050077#define SPR_834X_FAMILY 0x803
Kim Phillipse5c4ade2008-03-28 10:19:07 -050078#define SPR_8343 0x8036
79#define SPR_8347_TBGA_ 0x8032
80#define SPR_8347_PBGA_ 0x8034
81#define SPR_8349 0x8030
Kim Phillips6b70ffb2008-06-16 15:55:53 -050082#define SPR_836X_FAMILY 0x804
Kim Phillipse5c4ade2008-03-28 10:19:07 -050083#define SPR_8358_TBGA_ 0x804A
84#define SPR_8358_PBGA_ 0x804E
85#define SPR_8360 0x8048
Kim Phillips6b70ffb2008-06-16 15:55:53 -050086#define SPR_837X_FAMILY 0x80C
Kim Phillipse5c4ade2008-03-28 10:19:07 -050087#define SPR_8377 0x80C6
88#define SPR_8378 0x80C4
89#define SPR_8379 0x80C2
Scott Woodd87c57b2007-04-16 14:31:55 -050090
Dave Liue0803132006-12-07 21:11:58 +080091/* SPCR - System Priority Configuration Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050092 */
Dave Liue0803132006-12-07 21:11:58 +080093#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
94#define SPCR_PCIHPE_SHIFT (31-3)
95#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
96#define SPCR_PCIPR_SHIFT (31-7)
97#define SPCR_OPT 0x00800000 /* Optimize */
Michael Barkowski5bbeea82008-03-20 13:15:34 -040098#define SPCR_OPT_SHIFT (31-8)
Dave Liue0803132006-12-07 21:11:58 +080099#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
100#define SPCR_TBEN_SHIFT (31-9)
101#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
102#define SPCR_COREPR_SHIFT (31-11)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500103
Peter Tyser2c7920a2009-05-22 17:23:25 -0500104#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800105/* SPCR bits - MPC8349 specific */
106#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
107#define SPCR_TSEC1DP_SHIFT (31-19)
108#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
109#define SPCR_TSEC1BDP_SHIFT (31-21)
110#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
111#define SPCR_TSEC1EP_SHIFT (31-23)
112#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
113#define SPCR_TSEC2DP_SHIFT (31-27)
114#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
115#define SPCR_TSEC2BDP_SHIFT (31-29)
116#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
117#define SPCR_TSEC2EP_SHIFT (31-31)
Scott Woodd87c57b2007-04-16 14:31:55 -0500118
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400119#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
120 defined(CONFIG_MPC837x)
121/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500122#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
123#define SPCR_TSECDP_SHIFT (31-19)
Dave Liuec2638e2008-01-10 23:05:00 +0800124#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
125#define SPCR_TSECBDP_SHIFT (31-21)
126#define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */
127#define SPCR_TSECEP_SHIFT (31-23)
Dave Liu5f820432006-11-03 19:33:44 -0600128#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500129
Dave Liue0803132006-12-07 21:11:58 +0800130/* SICRL/H - System I/O Configuration Register Low/High
131 */
Peter Tyser2c7920a2009-05-22 17:23:25 -0500132#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800133/* SICRL bits - MPC8349 specific */
134#define SICRL_LDP_A 0x80000000
135#define SICRL_USB1 0x40000000
136#define SICRL_USB0 0x20000000
137#define SICRL_UART 0x0C000000
138#define SICRL_GPIO1_A 0x02000000
139#define SICRL_GPIO1_B 0x01000000
140#define SICRL_GPIO1_C 0x00800000
141#define SICRL_GPIO1_D 0x00400000
142#define SICRL_GPIO1_E 0x00200000
143#define SICRL_GPIO1_F 0x00180000
144#define SICRL_GPIO1_G 0x00040000
145#define SICRL_GPIO1_H 0x00020000
146#define SICRL_GPIO1_I 0x00010000
147#define SICRL_GPIO1_J 0x00008000
148#define SICRL_GPIO1_K 0x00004000
149#define SICRL_GPIO1_L 0x00003000
Eran Libertyf046ccd2005-07-28 10:08:46 -0500150
Dave Liue0803132006-12-07 21:11:58 +0800151/* SICRH bits - MPC8349 specific */
152#define SICRH_DDR 0x80000000
153#define SICRH_TSEC1_A 0x10000000
154#define SICRH_TSEC1_B 0x08000000
155#define SICRH_TSEC1_C 0x04000000
156#define SICRH_TSEC1_D 0x02000000
157#define SICRH_TSEC1_E 0x01000000
158#define SICRH_TSEC1_F 0x00800000
159#define SICRH_TSEC2_A 0x00400000
160#define SICRH_TSEC2_B 0x00200000
161#define SICRH_TSEC2_C 0x00100000
162#define SICRH_TSEC2_D 0x00080000
163#define SICRH_TSEC2_E 0x00040000
164#define SICRH_TSEC2_F 0x00020000
165#define SICRH_TSEC2_G 0x00010000
166#define SICRH_TSEC2_H 0x00008000
167#define SICRH_GPIO2_A 0x00004000
168#define SICRH_GPIO2_B 0x00002000
169#define SICRH_GPIO2_C 0x00001000
170#define SICRH_GPIO2_D 0x00000800
171#define SICRH_GPIO2_E 0x00000400
172#define SICRH_GPIO2_F 0x00000200
173#define SICRH_GPIO2_G 0x00000180
174#define SICRH_GPIO2_H 0x00000060
175#define SICRH_TSOBI1 0x00000002
176#define SICRH_TSOBI2 0x00000001
177
178#elif defined(CONFIG_MPC8360)
179/* SICRL bits - MPC8360 specific */
180#define SICRL_LDP_A 0xC0000000
181#define SICRL_LCLK_1 0x10000000
182#define SICRL_LCLK_2 0x08000000
183#define SICRL_SRCID_A 0x03000000
184#define SICRL_IRQ_CKSTP_A 0x00C00000
185
186/* SICRH bits - MPC8360 specific */
187#define SICRH_DDR 0x80000000
188#define SICRH_SECONDARY_DDR 0x40000000
189#define SICRH_SDDROE 0x20000000
190#define SICRH_IRQ3 0x10000000
191#define SICRH_UC1EOBI 0x00000004
192#define SICRH_UC2E1OBI 0x00000002
193#define SICRH_UC2E2OBI 0x00000001
Dave Liu24c3aca2006-12-07 21:13:15 +0800194
Peter Tyser2c7920a2009-05-22 17:23:25 -0500195#elif defined(CONFIG_MPC832x)
196/* SICRL bits - MPC832x specific */
Dave Liu24c3aca2006-12-07 21:13:15 +0800197#define SICRL_LDP_LCS_A 0x80000000
198#define SICRL_IRQ_CKS 0x20000000
199#define SICRL_PCI_MSRC 0x10000000
200#define SICRL_URT_CTPR 0x06000000
201#define SICRL_IRQ_CTPR 0x00C00000
Scott Woodd87c57b2007-04-16 14:31:55 -0500202
Dave Liu555da612007-09-18 12:36:58 +0800203#elif defined(CONFIG_MPC8313)
204/* SICRL bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500205#define SICRL_LBC 0x30000000
206#define SICRL_UART 0x0C000000
207#define SICRL_SPI_A 0x03000000
208#define SICRL_SPI_B 0x00C00000
209#define SICRL_SPI_C 0x00300000
210#define SICRL_SPI_D 0x000C0000
Ron Madridf9863252010-06-01 17:00:49 -0700211#define SICRL_USBDR_11 0x00000C00
212#define SICRL_USBDR_10 0x00000800
213#define SICRL_USBDR_01 0x00000400
214#define SICRL_USBDR_00 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500215#define SICRL_ETSEC1_A 0x0000000C
216#define SICRL_ETSEC2_A 0x00000003
217
Dave Liu555da612007-09-18 12:36:58 +0800218/* SICRH bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500219#define SICRH_INTR_A 0x02000000
220#define SICRH_INTR_B 0x00C00000
221#define SICRH_IIC 0x00300000
222#define SICRH_ETSEC2_B 0x000C0000
223#define SICRH_ETSEC2_C 0x00030000
224#define SICRH_ETSEC2_D 0x0000C000
225#define SICRH_ETSEC2_E 0x00003000
226#define SICRH_ETSEC2_F 0x00000C00
227#define SICRH_ETSEC2_G 0x00000300
228#define SICRH_ETSEC1_B 0x00000080
229#define SICRH_ETSEC1_C 0x00000060
230#define SICRH_GTX1_DLY 0x00000008
231#define SICRH_GTX2_DLY 0x00000004
232#define SICRH_TSOBI1 0x00000002
233#define SICRH_TSOBI2 0x00000001
234
Dave Liu555da612007-09-18 12:36:58 +0800235#elif defined(CONFIG_MPC8315)
236/* SICRL bits - MPC8315 specific */
237#define SICRL_DMA_CH0 0xc0000000
238#define SICRL_DMA_SPI 0x30000000
239#define SICRL_UART 0x0c000000
240#define SICRL_IRQ4 0x02000000
241#define SICRL_IRQ5 0x01800000
242#define SICRL_IRQ6_7 0x00400000
243#define SICRL_IIC1 0x00300000
244#define SICRL_TDM 0x000c0000
245#define SICRL_TDM_SHARED 0x00030000
246#define SICRL_PCI_A 0x0000c000
247#define SICRL_ELBC_A 0x00003000
248#define SICRL_ETSEC1_A 0x000000c0
249#define SICRL_ETSEC1_B 0x00000030
250#define SICRL_ETSEC1_C 0x0000000c
251#define SICRL_TSEXPOBI 0x00000001
252
253/* SICRH bits - MPC8315 specific */
254#define SICRH_GPIO_0 0xc0000000
255#define SICRH_GPIO_1 0x30000000
256#define SICRH_GPIO_2 0x0c000000
257#define SICRH_GPIO_3 0x03000000
258#define SICRH_GPIO_4 0x00c00000
259#define SICRH_GPIO_5 0x00300000
260#define SICRH_GPIO_6 0x000c0000
261#define SICRH_GPIO_7 0x00030000
262#define SICRH_GPIO_8 0x0000c000
263#define SICRH_GPIO_9 0x00003000
264#define SICRH_GPIO_10 0x00000c00
265#define SICRH_GPIO_11 0x00000300
266#define SICRH_ETSEC2_A 0x000000c0
267#define SICRH_TSOBI1 0x00000002
268#define SICRH_TSOBI2 0x00000001
269
Peter Tyser2c7920a2009-05-22 17:23:25 -0500270#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800271/* SICRL bits - MPC837x specific */
272#define SICRL_USB_A 0xC0000000
273#define SICRL_USB_B 0x30000000
Andy Fleminge1ac3872008-10-30 16:50:14 -0500274#define SICRL_USB_B_SD 0x20000000
Dave Liu03051c32007-09-18 12:36:11 +0800275#define SICRL_UART 0x0C000000
276#define SICRL_GPIO_A 0x02000000
277#define SICRL_GPIO_B 0x01000000
278#define SICRL_GPIO_C 0x00800000
279#define SICRL_GPIO_D 0x00400000
280#define SICRL_GPIO_E 0x00200000
281#define SICRL_GPIO_F 0x00180000
282#define SICRL_GPIO_G 0x00040000
283#define SICRL_GPIO_H 0x00020000
284#define SICRL_GPIO_I 0x00010000
285#define SICRL_GPIO_J 0x00008000
286#define SICRL_GPIO_K 0x00004000
287#define SICRL_GPIO_L 0x00003000
288#define SICRL_DMA_A 0x00000800
289#define SICRL_DMA_B 0x00000400
290#define SICRL_DMA_C 0x00000200
291#define SICRL_DMA_D 0x00000100
292#define SICRL_DMA_E 0x00000080
293#define SICRL_DMA_F 0x00000040
294#define SICRL_DMA_G 0x00000020
295#define SICRL_DMA_H 0x00000010
296#define SICRL_DMA_I 0x00000008
297#define SICRL_DMA_J 0x00000004
298#define SICRL_LDP_A 0x00000002
299#define SICRL_LDP_B 0x00000001
300
301/* SICRH bits - MPC837x specific */
302#define SICRH_DDR 0x80000000
303#define SICRH_TSEC1_A 0x10000000
304#define SICRH_TSEC1_B 0x08000000
305#define SICRH_TSEC2_A 0x00400000
306#define SICRH_TSEC2_B 0x00200000
307#define SICRH_TSEC2_C 0x00100000
308#define SICRH_TSEC2_D 0x00080000
309#define SICRH_TSEC2_E 0x00040000
310#define SICRH_TMR 0x00010000
311#define SICRH_GPIO2_A 0x00008000
312#define SICRH_GPIO2_B 0x00004000
313#define SICRH_GPIO2_C 0x00002000
314#define SICRH_GPIO2_D 0x00001000
315#define SICRH_GPIO2_E 0x00000C00
Andy Fleminge1ac3872008-10-30 16:50:14 -0500316#define SICRH_GPIO2_E_SD 0x00000800
Dave Liu03051c32007-09-18 12:36:11 +0800317#define SICRH_GPIO2_F 0x00000300
318#define SICRH_GPIO2_G 0x000000C0
319#define SICRH_GPIO2_H 0x00000030
320#define SICRH_SPI 0x00000003
Andy Fleminge1ac3872008-10-30 16:50:14 -0500321#define SICRH_SPI_SD 0x00000001
Ilya Yanokf3ce2502010-09-17 23:41:48 +0200322
323#elif defined(CONFIG_MPC8308)
324/* SICRL bits - MPC8308 specific */
325#define SICRL_SPI_PF0 (0 << 28)
326#define SICRL_SPI_PF1 (1 << 28)
327#define SICRL_SPI_PF3 (3 << 28)
328#define SICRL_UART_PF0 (0 << 26)
329#define SICRL_UART_PF1 (1 << 26)
330#define SICRL_UART_PF3 (3 << 26)
331#define SICRL_IRQ_PF0 (0 << 24)
332#define SICRL_IRQ_PF1 (1 << 24)
333#define SICRL_I2C2_PF0 (0 << 20)
334#define SICRL_I2C2_PF1 (1 << 20)
335#define SICRL_ETSEC1_TX_CLK (0 << 6)
336#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
337
338/* SICRH bits - MPC8308 specific */
339#define SICRH_ESDHC_A_SD (0 << 30)
340#define SICRH_ESDHC_A_GTM (1 << 30)
341#define SICRH_ESDHC_A_GPIO (3 << 30)
342#define SICRH_ESDHC_B_SD (0 << 28)
343#define SICRH_ESDHC_B_GTM (1 << 28)
344#define SICRH_ESDHC_B_GPIO (3 << 28)
345#define SICRH_ESDHC_C_SD (0 << 26)
346#define SICRH_ESDHC_C_GTM (1 << 26)
347#define SICRH_ESDHC_C_GPIO (3 << 26)
348#define SICRH_GPIO_A_GPIO (0 << 24)
349#define SICRH_GPIO_A_TSEC2 (1 << 24)
350#define SICRH_GPIO_B_GPIO (0 << 22)
351#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
352#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
353#define SICRH_IEEE1588_A_TMR (1 << 20)
354#define SICRH_IEEE1588_A_GPIO (3 << 20)
355#define SICRH_USB (1 << 18)
356#define SICRH_GTM_GTM (1 << 16)
357#define SICRH_GTM_GPIO (3 << 16)
358#define SICRH_IEEE1588_B_TMR (1 << 14)
359#define SICRH_IEEE1588_B_GPIO (3 << 14)
360#define SICRH_ETSEC2_CRS (1 << 12)
361#define SICRH_ETSEC2_GPIO (3 << 12)
362#define SICRH_GPIOSEL_0 (0 << 8)
363#define SICRH_GPIOSEL_1 (1 << 8)
364#define SICRH_TMROBI_V3P3 (0 << 4)
365#define SICRH_TMROBI_V2P5 (1 << 4)
366#define SICRH_TSOBI1_V3P3 (0 << 1)
367#define SICRH_TSOBI1_V2P5 (1 << 1)
368#define SICRH_TSOBI2_V3P3 (0 << 0)
369#define SICRH_TSOBI2_V2P5 (1 << 0)
Dave Liue0803132006-12-07 21:11:58 +0800370#endif
371
372/* SWCRR - System Watchdog Control Register
373 */
374#define SWCRR 0x0204 /* Register offset to immr */
375#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
376#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
377#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
378#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
379#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
380
381/* SWCNR - System Watchdog Counter Register
382 */
383#define SWCNR 0x0208 /* Register offset to immr */
384#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
385#define SWCNR_RES ~(SWCNR_SWCN)
386
387/* SWSRR - System Watchdog Service Register
388 */
389#define SWSRR 0x020E /* Register offset to immr */
390
391/* ACR - Arbiter Configuration Register
392 */
393#define ACR_COREDIS 0x10000000 /* Core disable */
394#define ACR_COREDIS_SHIFT (31-7)
395#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
396#define ACR_PIPE_DEP_SHIFT (31-15)
397#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
398#define ACR_PCI_RPTCNT_SHIFT (31-19)
399#define ACR_RPTCNT 0x00000700 /* Repeat count */
400#define ACR_RPTCNT_SHIFT (31-23)
401#define ACR_APARK 0x00000030 /* Address parking */
402#define ACR_APARK_SHIFT (31-27)
403#define ACR_PARKM 0x0000000F /* Parking master */
404#define ACR_PARKM_SHIFT (31-31)
405
406/* ATR - Arbiter Timers Register
407 */
408#define ATR_DTO 0x00FF0000 /* Data time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700409#define ATR_DTO_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800410#define ATR_ATO 0x000000FF /* Address time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700411#define ATR_ATO_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800412
413/* AER - Arbiter Event Register
414 */
415#define AER_ETEA 0x00000020 /* Transfer error */
416#define AER_RES 0x00000010 /* Reserved transfer type */
417#define AER_ECW 0x00000008 /* External control word transfer type */
418#define AER_AO 0x00000004 /* Address Only transfer type */
419#define AER_DTO 0x00000002 /* Data time out */
420#define AER_ATO 0x00000001 /* Address time out */
421
422/* AEATR - Arbiter Event Address Register
423 */
424#define AEATR_EVENT 0x07000000 /* Event type */
Nick Spence002d27c2008-08-22 23:52:40 -0700425#define AEATR_EVENT_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800426#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
Nick Spence002d27c2008-08-22 23:52:40 -0700427#define AEATR_MSTR_ID_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800428#define AEATR_TBST 0x00000800 /* Transfer burst */
Nick Spence002d27c2008-08-22 23:52:40 -0700429#define AEATR_TBST_SHIFT 11
Dave Liue0803132006-12-07 21:11:58 +0800430#define AEATR_TSIZE 0x00000700 /* Transfer Size */
Nick Spence002d27c2008-08-22 23:52:40 -0700431#define AEATR_TSIZE_SHIFT 8
Dave Liue0803132006-12-07 21:11:58 +0800432#define AEATR_TTYPE 0x0000001F /* Transfer Type */
Nick Spence002d27c2008-08-22 23:52:40 -0700433#define AEATR_TTYPE_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800434
435/* HRCWL - Hard Reset Configuration Word Low
436 */
437#define HRCWL_LBIUCM 0x80000000
438#define HRCWL_LBIUCM_SHIFT 31
439#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
440#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
441
442#define HRCWL_DDRCM 0x40000000
443#define HRCWL_DDRCM_SHIFT 30
444#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
445#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
446
447#define HRCWL_SPMF 0x0f000000
448#define HRCWL_SPMF_SHIFT 24
449#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
450#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
451#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
452#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
453#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
454#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
455#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
456#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
457#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
458#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
459#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
460#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
461#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
462#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
463#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
464#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
465
466#define HRCWL_VCO_BYPASS 0x00000000
467#define HRCWL_VCO_1X2 0x00000000
468#define HRCWL_VCO_1X4 0x00200000
469#define HRCWL_VCO_1X8 0x00400000
470
471#define HRCWL_COREPLL 0x007F0000
472#define HRCWL_COREPLL_SHIFT 16
473#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
474#define HRCWL_CORE_TO_CSB_1X1 0x00020000
475#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
476#define HRCWL_CORE_TO_CSB_2X1 0x00040000
477#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
478#define HRCWL_CORE_TO_CSB_3X1 0x00060000
479
Peter Tyser2c7920a2009-05-22 17:23:25 -0500480#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
Dave Liue0803132006-12-07 21:11:58 +0800481#define HRCWL_CEVCOD 0x000000C0
482#define HRCWL_CEVCOD_SHIFT 6
483#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
484#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
485#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
486
487#define HRCWL_CEPDF 0x00000020
488#define HRCWL_CEPDF_SHIFT 5
489#define HRCWL_CE_PLL_DIV_1X1 0x00000000
490#define HRCWL_CE_PLL_DIV_2X1 0x00000020
491
492#define HRCWL_CEPMF 0x0000001F
493#define HRCWL_CEPMF_SHIFT 0
494#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
495#define HRCWL_CE_TO_PLL_1X2 0x00000002
496#define HRCWL_CE_TO_PLL_1X3 0x00000003
497#define HRCWL_CE_TO_PLL_1X4 0x00000004
498#define HRCWL_CE_TO_PLL_1X5 0x00000005
499#define HRCWL_CE_TO_PLL_1X6 0x00000006
500#define HRCWL_CE_TO_PLL_1X7 0x00000007
501#define HRCWL_CE_TO_PLL_1X8 0x00000008
502#define HRCWL_CE_TO_PLL_1X9 0x00000009
503#define HRCWL_CE_TO_PLL_1X10 0x0000000A
504#define HRCWL_CE_TO_PLL_1X11 0x0000000B
505#define HRCWL_CE_TO_PLL_1X12 0x0000000C
506#define HRCWL_CE_TO_PLL_1X13 0x0000000D
507#define HRCWL_CE_TO_PLL_1X14 0x0000000E
508#define HRCWL_CE_TO_PLL_1X15 0x0000000F
509#define HRCWL_CE_TO_PLL_1X16 0x00000010
510#define HRCWL_CE_TO_PLL_1X17 0x00000011
511#define HRCWL_CE_TO_PLL_1X18 0x00000012
512#define HRCWL_CE_TO_PLL_1X19 0x00000013
513#define HRCWL_CE_TO_PLL_1X20 0x00000014
514#define HRCWL_CE_TO_PLL_1X21 0x00000015
515#define HRCWL_CE_TO_PLL_1X22 0x00000016
516#define HRCWL_CE_TO_PLL_1X23 0x00000017
517#define HRCWL_CE_TO_PLL_1X24 0x00000018
518#define HRCWL_CE_TO_PLL_1X25 0x00000019
519#define HRCWL_CE_TO_PLL_1X26 0x0000001A
520#define HRCWL_CE_TO_PLL_1X27 0x0000001B
521#define HRCWL_CE_TO_PLL_1X28 0x0000001C
522#define HRCWL_CE_TO_PLL_1X29 0x0000001D
523#define HRCWL_CE_TO_PLL_1X30 0x0000001E
524#define HRCWL_CE_TO_PLL_1X31 0x0000001F
Dave Liu03051c32007-09-18 12:36:11 +0800525
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400526#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
Dave Liu6f3931a2008-01-10 23:06:05 +0800527#define HRCWL_SVCOD 0x30000000
528#define HRCWL_SVCOD_SHIFT 28
529#define HRCWL_SVCOD_DIV_2 0x00000000
530#define HRCWL_SVCOD_DIV_4 0x10000000
531#define HRCWL_SVCOD_DIV_8 0x20000000
532#define HRCWL_SVCOD_DIV_1 0x30000000
533
Peter Tyser2c7920a2009-05-22 17:23:25 -0500534#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800535#define HRCWL_SVCOD 0x30000000
536#define HRCWL_SVCOD_SHIFT 28
537#define HRCWL_SVCOD_DIV_4 0x00000000
538#define HRCWL_SVCOD_DIV_8 0x10000000
539#define HRCWL_SVCOD_DIV_2 0x20000000
540#define HRCWL_SVCOD_DIV_1 0x30000000
Dave Liue0803132006-12-07 21:11:58 +0800541#endif
542
543/* HRCWH - Hardware Reset Configuration Word High
544 */
545#define HRCWH_PCI_HOST 0x80000000
546#define HRCWH_PCI_HOST_SHIFT 31
547#define HRCWH_PCI_AGENT 0x00000000
548
Peter Tyser2c7920a2009-05-22 17:23:25 -0500549#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800550#define HRCWH_32_BIT_PCI 0x00000000
551#define HRCWH_64_BIT_PCI 0x40000000
552#endif
553
554#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
555#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
556
557#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
558#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
559
Peter Tyser2c7920a2009-05-22 17:23:25 -0500560#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800561#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
562#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
563
564#elif defined(CONFIG_MPC8360)
565#define HRCWH_PCICKDRV_DISABLE 0x00000000
566#define HRCWH_PCICKDRV_ENABLE 0x10000000
567#endif
568
569#define HRCWH_CORE_DISABLE 0x08000000
570#define HRCWH_CORE_ENABLE 0x00000000
571
572#define HRCWH_FROM_0X00000100 0x00000000
573#define HRCWH_FROM_0XFFF00100 0x04000000
574
575#define HRCWH_BOOTSEQ_DISABLE 0x00000000
576#define HRCWH_BOOTSEQ_NORMAL 0x01000000
577#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
578
579#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
580#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
581
582#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
583#define HRCWH_ROM_LOC_PCI1 0x00100000
Peter Tyser2c7920a2009-05-22 17:23:25 -0500584#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800585#define HRCWH_ROM_LOC_PCI2 0x00200000
586#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500587#if defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800588#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
589#endif
Dave Liue0803132006-12-07 21:11:58 +0800590#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
591#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
592#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
593
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400594#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
595 defined(CONFIG_MPC837x)
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200596#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
Scott Woodd87c57b2007-04-16 14:31:55 -0500597#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200598#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
Scott Woodd87c57b2007-04-16 14:31:55 -0500599#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
600
601#define HRCWH_RL_EXT_LEGACY 0x00000000
602#define HRCWH_RL_EXT_NAND 0x00040000
603
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400604#define HRCWH_TSEC1M_MASK 0x0000E000
Scott Woodd87c57b2007-04-16 14:31:55 -0500605#define HRCWH_TSEC1M_IN_MII 0x00000000
606#define HRCWH_TSEC1M_IN_RMII 0x00002000
607#define HRCWH_TSEC1M_IN_RGMII 0x00006000
608#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
609#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
610
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400611#define HRCWH_TSEC2M_MASK 0x00001C00
Scott Woodd87c57b2007-04-16 14:31:55 -0500612#define HRCWH_TSEC2M_IN_MII 0x00000000
613#define HRCWH_TSEC2M_IN_RMII 0x00000400
614#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
615#define HRCWH_TSEC2M_IN_RTBI 0x00001400
616#define HRCWH_TSEC2M_IN_SGMII 0x00001800
617#endif
618
Peter Tyser2c7920a2009-05-22 17:23:25 -0500619#if defined(CONFIG_MPC834x)
Dave Liue0803132006-12-07 21:11:58 +0800620#define HRCWH_TSEC1M_IN_RGMII 0x00000000
621#define HRCWH_TSEC1M_IN_RTBI 0x00004000
622#define HRCWH_TSEC1M_IN_GMII 0x00008000
623#define HRCWH_TSEC1M_IN_TBI 0x0000C000
624#define HRCWH_TSEC2M_IN_RGMII 0x00000000
625#define HRCWH_TSEC2M_IN_RTBI 0x00001000
626#define HRCWH_TSEC2M_IN_GMII 0x00002000
627#define HRCWH_TSEC2M_IN_TBI 0x00003000
628#endif
629
630#if defined(CONFIG_MPC8360)
631#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
632#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
633#endif
634
635#define HRCWH_BIG_ENDIAN 0x00000000
636#define HRCWH_LITTLE_ENDIAN 0x00000008
637
638#define HRCWH_LALE_NORMAL 0x00000000
639#define HRCWH_LALE_EARLY 0x00000004
640
641#define HRCWH_LDP_SET 0x00000000
642#define HRCWH_LDP_CLEAR 0x00000002
643
644/* RSR - Reset Status Register
645 */
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400646#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
647 defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800648#define RSR_RSTSRC 0xF0000000 /* Reset source */
649#define RSR_RSTSRC_SHIFT 28
650#else
Dave Liue0803132006-12-07 21:11:58 +0800651#define RSR_RSTSRC 0xE0000000 /* Reset source */
652#define RSR_RSTSRC_SHIFT 29
Dave Liu03051c32007-09-18 12:36:11 +0800653#endif
Dave Liue0803132006-12-07 21:11:58 +0800654#define RSR_BSF 0x00010000 /* Boot seq. fail */
655#define RSR_BSF_SHIFT 16
656#define RSR_SWSR 0x00002000 /* software soft reset */
657#define RSR_SWSR_SHIFT 13
658#define RSR_SWHR 0x00001000 /* software hard reset */
659#define RSR_SWHR_SHIFT 12
660#define RSR_JHRS 0x00000200 /* jtag hreset */
661#define RSR_JHRS_SHIFT 9
662#define RSR_JSRS 0x00000100 /* jtag sreset status */
663#define RSR_JSRS_SHIFT 8
664#define RSR_CSHR 0x00000010 /* checkstop reset status */
665#define RSR_CSHR_SHIFT 4
666#define RSR_SWRS 0x00000008 /* software watchdog reset status */
667#define RSR_SWRS_SHIFT 3
668#define RSR_BMRS 0x00000004 /* bus monitop reset status */
669#define RSR_BMRS_SHIFT 2
670#define RSR_SRS 0x00000002 /* soft reset status */
671#define RSR_SRS_SHIFT 1
672#define RSR_HRS 0x00000001 /* hard reset status */
673#define RSR_HRS_SHIFT 0
674#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
675 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
676 RSR_BMRS | RSR_SRS | RSR_HRS)
677/* RMR - Reset Mode Register
678 */
679#define RMR_CSRE 0x00000001 /* checkstop reset enable */
680#define RMR_CSRE_SHIFT 0
681#define RMR_RES ~(RMR_CSRE)
682
683/* RCR - Reset Control Register
684 */
685#define RCR_SWHR 0x00000002 /* software hard reset */
686#define RCR_SWSR 0x00000001 /* software soft reset */
687#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
688
689/* RCER - Reset Control Enable Register
690 */
691#define RCER_CRE 0x00000001 /* software hard reset */
692#define RCER_RES ~(RCER_CRE)
693
694/* SPMR - System PLL Mode Register
695 */
696#define SPMR_LBIUCM 0x80000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100697#define SPMR_LBIUCM_SHIFT 31
Dave Liue0803132006-12-07 21:11:58 +0800698#define SPMR_DDRCM 0x40000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100699#define SPMR_DDRCM_SHIFT 30
Dave Liue0803132006-12-07 21:11:58 +0800700#define SPMR_SPMF 0x0F000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100701#define SPMR_SPMF_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800702#define SPMR_CKID 0x00800000
703#define SPMR_CKID_SHIFT 23
704#define SPMR_COREPLL 0x007F0000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100705#define SPMR_COREPLL_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800706#define SPMR_CEVCOD 0x000000C0
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100707#define SPMR_CEVCOD_SHIFT 6
Dave Liue0803132006-12-07 21:11:58 +0800708#define SPMR_CEPDF 0x00000020
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100709#define SPMR_CEPDF_SHIFT 5
Dave Liue0803132006-12-07 21:11:58 +0800710#define SPMR_CEPMF 0x0000001F
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100711#define SPMR_CEPMF_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800712
713/* OCCR - Output Clock Control Register
714 */
715#define OCCR_PCICOE0 0x80000000
716#define OCCR_PCICOE1 0x40000000
717#define OCCR_PCICOE2 0x20000000
718#define OCCR_PCICOE3 0x10000000
719#define OCCR_PCICOE4 0x08000000
720#define OCCR_PCICOE5 0x04000000
721#define OCCR_PCICOE6 0x02000000
722#define OCCR_PCICOE7 0x01000000
723#define OCCR_PCICD0 0x00800000
724#define OCCR_PCICD1 0x00400000
725#define OCCR_PCICD2 0x00200000
726#define OCCR_PCICD3 0x00100000
727#define OCCR_PCICD4 0x00080000
728#define OCCR_PCICD5 0x00040000
729#define OCCR_PCICD6 0x00020000
730#define OCCR_PCICD7 0x00010000
731#define OCCR_PCI1CR 0x00000002
732#define OCCR_PCI2CR 0x00000001
733#define OCCR_PCICR OCCR_PCI1CR
734
735/* SCCR - System Clock Control Register
736 */
737#define SCCR_ENCCM 0x03000000
738#define SCCR_ENCCM_SHIFT 24
739#define SCCR_ENCCM_0 0x00000000
740#define SCCR_ENCCM_1 0x01000000
741#define SCCR_ENCCM_2 0x02000000
742#define SCCR_ENCCM_3 0x03000000
743
744#define SCCR_PCICM 0x00010000
745#define SCCR_PCICM_SHIFT 16
746
Peter Tyser2c7920a2009-05-22 17:23:25 -0500747#if defined(CONFIG_MPC834x)
Dave Liu03051c32007-09-18 12:36:11 +0800748/* SCCR bits - MPC834x specific */
Dave Liue0803132006-12-07 21:11:58 +0800749#define SCCR_TSEC1CM 0xc0000000
750#define SCCR_TSEC1CM_SHIFT 30
751#define SCCR_TSEC1CM_0 0x00000000
752#define SCCR_TSEC1CM_1 0x40000000
753#define SCCR_TSEC1CM_2 0x80000000
754#define SCCR_TSEC1CM_3 0xC0000000
755
756#define SCCR_TSEC2CM 0x30000000
757#define SCCR_TSEC2CM_SHIFT 28
758#define SCCR_TSEC2CM_0 0x00000000
759#define SCCR_TSEC2CM_1 0x10000000
760#define SCCR_TSEC2CM_2 0x20000000
761#define SCCR_TSEC2CM_3 0x30000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500762
Dave Liu03051c32007-09-18 12:36:11 +0800763/* The MPH must have the same clock ratio as DR, unless its clock disabled */
764#define SCCR_USBMPHCM 0x00c00000
765#define SCCR_USBMPHCM_SHIFT 22
766#define SCCR_USBDRCM 0x00300000
767#define SCCR_USBDRCM_SHIFT 20
768#define SCCR_USBCM 0x00f00000
769#define SCCR_USBCM_SHIFT 20
770#define SCCR_USBCM_0 0x00000000
771#define SCCR_USBCM_1 0x00500000
772#define SCCR_USBCM_2 0x00A00000
773#define SCCR_USBCM_3 0x00F00000
774
Dave Liu555da612007-09-18 12:36:58 +0800775#elif defined(CONFIG_MPC8313)
Dave Liua8cb43a2008-01-17 18:23:19 +0800776/* TSEC1 bits are for TSEC2 as well */
Scott Woodd87c57b2007-04-16 14:31:55 -0500777#define SCCR_TSEC1CM 0xc0000000
778#define SCCR_TSEC1CM_SHIFT 30
Kim Phillips9e896472008-01-16 12:06:16 -0600779#define SCCR_TSEC1CM_0 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500780#define SCCR_TSEC1CM_1 0x40000000
781#define SCCR_TSEC1CM_2 0x80000000
782#define SCCR_TSEC1CM_3 0xC0000000
783
784#define SCCR_TSEC1ON 0x20000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500785#define SCCR_TSEC1ON_SHIFT 29
Scott Woodd87c57b2007-04-16 14:31:55 -0500786#define SCCR_TSEC2ON 0x10000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500787#define SCCR_TSEC2ON_SHIFT 28
Scott Woodd87c57b2007-04-16 14:31:55 -0500788
Dave Liue0803132006-12-07 21:11:58 +0800789#define SCCR_USBDRCM 0x00300000
790#define SCCR_USBDRCM_SHIFT 20
Dave Liu03051c32007-09-18 12:36:11 +0800791#define SCCR_USBDRCM_0 0x00000000
792#define SCCR_USBDRCM_1 0x00100000
793#define SCCR_USBDRCM_2 0x00200000
794#define SCCR_USBDRCM_3 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800795
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400796#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
797/* SCCR bits - MPC8315/MPC8308 specific */
Dave Liu555da612007-09-18 12:36:58 +0800798#define SCCR_TSEC1CM 0xc0000000
799#define SCCR_TSEC1CM_SHIFT 30
800#define SCCR_TSEC1CM_0 0x00000000
801#define SCCR_TSEC1CM_1 0x40000000
802#define SCCR_TSEC1CM_2 0x80000000
803#define SCCR_TSEC1CM_3 0xC0000000
804
805#define SCCR_TSEC2CM 0x30000000
806#define SCCR_TSEC2CM_SHIFT 28
807#define SCCR_TSEC2CM_0 0x00000000
808#define SCCR_TSEC2CM_1 0x10000000
809#define SCCR_TSEC2CM_2 0x20000000
810#define SCCR_TSEC2CM_3 0x30000000
811
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400812#define SCCR_SDHCCM 0x0c000000
813#define SCCR_SDHCCM_SHIFT 26
814#define SCCR_SDHCCM_0 0x00000000
815#define SCCR_SDHCCM_1 0x04000000
816#define SCCR_SDHCCM_2 0x08000000
817#define SCCR_SDHCCM_3 0x0c000000
818
Dave Liu6f3931a2008-01-10 23:06:05 +0800819#define SCCR_USBDRCM 0x00c00000
820#define SCCR_USBDRCM_SHIFT 22
Dave Liu555da612007-09-18 12:36:58 +0800821#define SCCR_USBDRCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800822#define SCCR_USBDRCM_1 0x00400000
823#define SCCR_USBDRCM_2 0x00800000
824#define SCCR_USBDRCM_3 0x00c00000
Dave Liu555da612007-09-18 12:36:58 +0800825
Dave Liu6f3931a2008-01-10 23:06:05 +0800826#define SCCR_SATA1CM 0x00003000
827#define SCCR_SATA1CM_SHIFT 12
828#define SCCR_SATACM 0x00003c00
829#define SCCR_SATACM_SHIFT 10
Dave Liu555da612007-09-18 12:36:58 +0800830#define SCCR_SATACM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800831#define SCCR_SATACM_1 0x00001400
832#define SCCR_SATACM_2 0x00002800
833#define SCCR_SATACM_3 0x00003c00
Dave Liu555da612007-09-18 12:36:58 +0800834
Dave Liu6f3931a2008-01-10 23:06:05 +0800835#define SCCR_TDMCM 0x00000030
836#define SCCR_TDMCM_SHIFT 4
Dave Liu555da612007-09-18 12:36:58 +0800837#define SCCR_TDMCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800838#define SCCR_TDMCM_1 0x00000010
839#define SCCR_TDMCM_2 0x00000020
840#define SCCR_TDMCM_3 0x00000030
Dave Liu555da612007-09-18 12:36:58 +0800841
Peter Tyser2c7920a2009-05-22 17:23:25 -0500842#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800843/* SCCR bits - MPC837x specific */
844#define SCCR_TSEC1CM 0xc0000000
845#define SCCR_TSEC1CM_SHIFT 30
846#define SCCR_TSEC1CM_0 0x00000000
847#define SCCR_TSEC1CM_1 0x40000000
848#define SCCR_TSEC1CM_2 0x80000000
849#define SCCR_TSEC1CM_3 0xC0000000
850
851#define SCCR_TSEC2CM 0x30000000
852#define SCCR_TSEC2CM_SHIFT 28
853#define SCCR_TSEC2CM_0 0x00000000
854#define SCCR_TSEC2CM_1 0x10000000
855#define SCCR_TSEC2CM_2 0x20000000
856#define SCCR_TSEC2CM_3 0x30000000
857
858#define SCCR_SDHCCM 0x0c000000
859#define SCCR_SDHCCM_SHIFT 26
860#define SCCR_SDHCCM_0 0x00000000
861#define SCCR_SDHCCM_1 0x04000000
862#define SCCR_SDHCCM_2 0x08000000
863#define SCCR_SDHCCM_3 0x0c000000
864
865#define SCCR_USBDRCM 0x00c00000
866#define SCCR_USBDRCM_SHIFT 22
867#define SCCR_USBDRCM_0 0x00000000
868#define SCCR_USBDRCM_1 0x00400000
869#define SCCR_USBDRCM_2 0x00800000
870#define SCCR_USBDRCM_3 0x00c00000
871
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300872/* All of the four SATA controllers must have the same clock ratio */
873#define SCCR_SATA1CM 0x000000c0
874#define SCCR_SATA1CM_SHIFT 6
875#define SCCR_SATACM 0x000000ff
876#define SCCR_SATACM_SHIFT 0
877#define SCCR_SATACM_0 0x00000000
878#define SCCR_SATACM_1 0x00000055
879#define SCCR_SATACM_2 0x000000aa
880#define SCCR_SATACM_3 0x000000ff
881#endif
882
Dave Liu03051c32007-09-18 12:36:11 +0800883#define SCCR_PCIEXP1CM 0x00300000
884#define SCCR_PCIEXP1CM_SHIFT 20
885#define SCCR_PCIEXP1CM_0 0x00000000
886#define SCCR_PCIEXP1CM_1 0x00100000
887#define SCCR_PCIEXP1CM_2 0x00200000
888#define SCCR_PCIEXP1CM_3 0x00300000
889
890#define SCCR_PCIEXP2CM 0x000c0000
891#define SCCR_PCIEXP2CM_SHIFT 18
892#define SCCR_PCIEXP2CM_0 0x00000000
893#define SCCR_PCIEXP2CM_1 0x00040000
894#define SCCR_PCIEXP2CM_2 0x00080000
895#define SCCR_PCIEXP2CM_3 0x000c0000
896
Dave Liue0803132006-12-07 21:11:58 +0800897/* CSn_BDNS - Chip Select memory Bounds Register
898 */
899#define CSBNDS_SA 0x00FF0000
900#define CSBNDS_SA_SHIFT 8
901#define CSBNDS_EA 0x000000FF
902#define CSBNDS_EA_SHIFT 24
903
904/* CSn_CONFIG - Chip Select Configuration Register
905 */
906#define CSCONFIG_EN 0x80000000
907#define CSCONFIG_AP 0x00800000
Kim Phillips9e896472008-01-16 12:06:16 -0600908#define CSCONFIG_ODT_WR_ACS 0x00010000
Heiko Schocher6d2c26a2009-08-21 16:30:30 -0500909#if defined(CONFIG_MPC832x)
910#define CSCONFIG_ODT_WR_CFG 0x00040000
911#endif
Tor Krilld82b4fc2008-06-02 15:09:30 +0200912#define CSCONFIG_BANK_BIT_3 0x00004000
Dave Liue0803132006-12-07 21:11:58 +0800913#define CSCONFIG_ROW_BIT 0x00000700
914#define CSCONFIG_ROW_BIT_12 0x00000000
915#define CSCONFIG_ROW_BIT_13 0x00000100
916#define CSCONFIG_ROW_BIT_14 0x00000200
917#define CSCONFIG_COL_BIT 0x00000007
918#define CSCONFIG_COL_BIT_8 0x00000000
919#define CSCONFIG_COL_BIT_9 0x00000001
920#define CSCONFIG_COL_BIT_10 0x00000002
921#define CSCONFIG_COL_BIT_11 0x00000003
922
Scott Woodd87c57b2007-04-16 14:31:55 -0500923/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
924 */
925#define TIMING_CFG0_RWT 0xC0000000
926#define TIMING_CFG0_RWT_SHIFT 30
927#define TIMING_CFG0_WRT 0x30000000
928#define TIMING_CFG0_WRT_SHIFT 28
929#define TIMING_CFG0_RRT 0x0C000000
930#define TIMING_CFG0_RRT_SHIFT 26
931#define TIMING_CFG0_WWT 0x03000000
932#define TIMING_CFG0_WWT_SHIFT 24
933#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
934#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
935#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
936#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
937#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
938#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300939#define TIMING_CFG0_MRS_CYC 0x0000000F
Scott Woodd87c57b2007-04-16 14:31:55 -0500940#define TIMING_CFG0_MRS_CYC_SHIFT 0
941
Dave Liue0803132006-12-07 21:11:58 +0800942/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
943 */
944#define TIMING_CFG1_PRETOACT 0x70000000
945#define TIMING_CFG1_PRETOACT_SHIFT 28
946#define TIMING_CFG1_ACTTOPRE 0x0F000000
947#define TIMING_CFG1_ACTTOPRE_SHIFT 24
948#define TIMING_CFG1_ACTTORW 0x00700000
949#define TIMING_CFG1_ACTTORW_SHIFT 20
950#define TIMING_CFG1_CASLAT 0x00070000
951#define TIMING_CFG1_CASLAT_SHIFT 16
952#define TIMING_CFG1_REFREC 0x0000F000
953#define TIMING_CFG1_REFREC_SHIFT 12
954#define TIMING_CFG1_WRREC 0x00000700
955#define TIMING_CFG1_WRREC_SHIFT 8
956#define TIMING_CFG1_ACTTOACT 0x00000070
957#define TIMING_CFG1_ACTTOACT_SHIFT 4
958#define TIMING_CFG1_WRTORD 0x00000007
959#define TIMING_CFG1_WRTORD_SHIFT 0
960#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
961#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
Heiko Schocherfacdad52008-11-19 10:10:30 +0100962#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
963#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
964#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
Heiko Schocher2b68b232009-02-11 19:26:15 +0100965#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
966#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
Dave Liue0803132006-12-07 21:11:58 +0800967
968/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
969 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800970#define TIMING_CFG2_CPO 0x0F800000
971#define TIMING_CFG2_CPO_SHIFT 23
Dave Liue0803132006-12-07 21:11:58 +0800972#define TIMING_CFG2_ACSM 0x00080000
973#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
974#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
975#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
976
Scott Woodd87c57b2007-04-16 14:31:55 -0500977#define TIMING_CFG2_ADD_LAT 0x70000000
978#define TIMING_CFG2_ADD_LAT_SHIFT 28
979#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
980#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
981#define TIMING_CFG2_RD_TO_PRE 0x0000E000
982#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
983#define TIMING_CFG2_CKE_PLS 0x000001C0
984#define TIMING_CFG2_CKE_PLS_SHIFT 6
985#define TIMING_CFG2_FOUR_ACT 0x0000003F
986#define TIMING_CFG2_FOUR_ACT_SHIFT 0
987
Dave Liue0803132006-12-07 21:11:58 +0800988/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
989 */
990#define SDRAM_CFG_MEM_EN 0x80000000
991#define SDRAM_CFG_SREN 0x40000000
992#define SDRAM_CFG_ECC_EN 0x20000000
993#define SDRAM_CFG_RD_EN 0x10000000
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500994#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
995#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
996#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
Dave Liue0803132006-12-07 21:11:58 +0800997#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
998#define SDRAM_CFG_DYN_PWR 0x00200000
999#define SDRAM_CFG_32_BE 0x00080000
1000#define SDRAM_CFG_8_BE 0x00040000
1001#define SDRAM_CFG_NCAP 0x00020000
1002#define SDRAM_CFG_2T_EN 0x00008000
Scott Woodd87c57b2007-04-16 14:31:55 -05001003#define SDRAM_CFG_BI 0x00000001
Dave Liue0803132006-12-07 21:11:58 +08001004
1005/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
1006 */
1007#define SDRAM_MODE_ESD 0xFFFF0000
1008#define SDRAM_MODE_ESD_SHIFT 16
1009#define SDRAM_MODE_SD 0x0000FFFF
1010#define SDRAM_MODE_SD_SHIFT 0
1011#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
1012#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
1013#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
1014#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
1015#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
1016#define DDR_MODE_WEAK 0x0002 /* weak drivers */
1017#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
1018#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
1019#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
1020#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
1021#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
1022#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
1023#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
1024#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
1025#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
1026#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
1027#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
1028#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
1029#define DDR_MODE_MODEREG 0x0000 /* select mode register */
1030
1031/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
1032 */
1033#define SDRAM_INTERVAL_REFINT 0x3FFF0000
1034#define SDRAM_INTERVAL_REFINT_SHIFT 16
1035#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
1036#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
1037
1038/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
1039 */
1040#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
1041#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
1042#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
1043#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
1044#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
1045
1046/* ECC_ERR_INJECT - Memory data path error injection mask ECC
1047 */
1048#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
1049#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
1050#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
1051#define ECC_ERR_INJECT_EEIM_SHIFT 0
1052
1053/* CAPTURE_ECC - Memory data path read capture ECC
1054 */
1055#define CAPTURE_ECC_ECE (0xff000000>>24)
1056#define CAPTURE_ECC_ECE_SHIFT 0
1057
1058/* ERR_DETECT - Memory error detect
1059 */
1060#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
1061#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
1062#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
1063#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
1064
1065/* ERR_DISABLE - Memory error disable
1066 */
1067#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
1068#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
1069#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
1070#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
1071 ECC_ERROR_DISABLE_MBED)
1072/* ERR_INT_EN - Memory error interrupt enable
1073 */
1074#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
1075#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
1076#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
1077#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
1078 ECC_ERR_INT_EN_MSEE)
1079/* CAPTURE_ATTRIBUTES - Memory error attributes capture
1080 */
1081#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
1082#define ECC_CAPT_ATTR_BNUM_SHIFT 28
1083#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
1084#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
1085#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
1086#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
1087#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
1088#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
1089#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
1090#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1091#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1092#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
1093#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
1094#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
1095#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
1096#define ECC_CAPT_ATTR_TSRC_I2C 0x9
1097#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
1098#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
1099#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
1100#define ECC_CAPT_ATTR_TSRC_DMA 0xF
1101#define ECC_CAPT_ATTR_TSRC_SHIFT 16
1102#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
1103#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
1104#define ECC_CAPT_ATTR_TTYP_READ 0x2
1105#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
1106#define ECC_CAPT_ATTR_TTYP_SHIFT 12
1107#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
1108
1109/* ERR_SBE - Single bit ECC memory error management
1110 */
1111#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
1112#define ECC_ERROR_MAN_SBET_SHIFT 16
1113#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
1114#define ECC_ERROR_MAN_SBEC_SHIFT 0
1115
Dave Liue0803132006-12-07 21:11:58 +08001116/* CONFIG_ADDRESS - PCI Config Address Register
1117 */
1118#define PCI_CONFIG_ADDRESS_EN 0x80000000
1119#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1120#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1121#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1122#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1123#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1124#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1125#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1126#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
Dave Liu5f820432006-11-03 19:33:44 -06001127
Dave Liue0803132006-12-07 21:11:58 +08001128/* POTAR - PCI Outbound Translation Address Register
1129 */
1130#define POTAR_TA_MASK 0x000fffff
1131
1132/* POBAR - PCI Outbound Base Address Register
1133 */
1134#define POBAR_BA_MASK 0x000fffff
1135
1136/* POCMR - PCI Outbound Comparision Mask Register
1137 */
1138#define POCMR_EN 0x80000000
1139#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
1140#define POCMR_SE 0x20000000 /* streaming enable */
1141#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1142#define POCMR_CM_MASK 0x000fffff
1143#define POCMR_CM_4G 0x00000000
1144#define POCMR_CM_2G 0x00080000
1145#define POCMR_CM_1G 0x000C0000
1146#define POCMR_CM_512M 0x000E0000
1147#define POCMR_CM_256M 0x000F0000
1148#define POCMR_CM_128M 0x000F8000
1149#define POCMR_CM_64M 0x000FC000
1150#define POCMR_CM_32M 0x000FE000
1151#define POCMR_CM_16M 0x000FF000
1152#define POCMR_CM_8M 0x000FF800
1153#define POCMR_CM_4M 0x000FFC00
1154#define POCMR_CM_2M 0x000FFE00
1155#define POCMR_CM_1M 0x000FFF00
1156#define POCMR_CM_512K 0x000FFF80
1157#define POCMR_CM_256K 0x000FFFC0
1158#define POCMR_CM_128K 0x000FFFE0
1159#define POCMR_CM_64K 0x000FFFF0
1160#define POCMR_CM_32K 0x000FFFF8
1161#define POCMR_CM_16K 0x000FFFFC
1162#define POCMR_CM_8K 0x000FFFFE
1163#define POCMR_CM_4K 0x000FFFFF
1164
1165/* PITAR - PCI Inbound Translation Address Register
1166 */
1167#define PITAR_TA_MASK 0x000fffff
1168
1169/* PIBAR - PCI Inbound Base/Extended Address Register
1170 */
1171#define PIBAR_MASK 0xffffffff
1172#define PIEBAR_EBA_MASK 0x000fffff
1173
1174/* PIWAR - PCI Inbound Windows Attributes Register
1175 */
1176#define PIWAR_EN 0x80000000
1177#define PIWAR_PF 0x20000000
1178#define PIWAR_RTT_MASK 0x000f0000
1179#define PIWAR_RTT_NO_SNOOP 0x00040000
1180#define PIWAR_RTT_SNOOP 0x00050000
1181#define PIWAR_WTT_MASK 0x0000f000
1182#define PIWAR_WTT_NO_SNOOP 0x00004000
1183#define PIWAR_WTT_SNOOP 0x00005000
1184#define PIWAR_IWS_MASK 0x0000003F
1185#define PIWAR_IWS_4K 0x0000000B
1186#define PIWAR_IWS_8K 0x0000000C
1187#define PIWAR_IWS_16K 0x0000000D
1188#define PIWAR_IWS_32K 0x0000000E
1189#define PIWAR_IWS_64K 0x0000000F
1190#define PIWAR_IWS_128K 0x00000010
1191#define PIWAR_IWS_256K 0x00000011
1192#define PIWAR_IWS_512K 0x00000012
1193#define PIWAR_IWS_1M 0x00000013
1194#define PIWAR_IWS_2M 0x00000014
1195#define PIWAR_IWS_4M 0x00000015
1196#define PIWAR_IWS_8M 0x00000016
1197#define PIWAR_IWS_16M 0x00000017
1198#define PIWAR_IWS_32M 0x00000018
1199#define PIWAR_IWS_64M 0x00000019
1200#define PIWAR_IWS_128M 0x0000001A
1201#define PIWAR_IWS_256M 0x0000001B
1202#define PIWAR_IWS_512M 0x0000001C
1203#define PIWAR_IWS_1G 0x0000001D
1204#define PIWAR_IWS_2G 0x0000001E
Dave Liuf6eda7f2006-10-25 14:41:21 -05001205
Scott Woodd87c57b2007-04-16 14:31:55 -05001206/* PMCCR1 - PCI Configuration Register 1
1207 */
1208#define PMCCR1_POWER_OFF 0x00000020
1209
Dave Liu03051c32007-09-18 12:36:11 +08001210/* DDRCDR - DDR Control Driver Register
Scott Woodd87c57b2007-04-16 14:31:55 -05001211 */
Kim Phillips9e896472008-01-16 12:06:16 -06001212#define DDRCDR_DHC_EN 0x80000000
Scott Woodd87c57b2007-04-16 14:31:55 -05001213#define DDRCDR_EN 0x40000000
1214#define DDRCDR_PZ 0x3C000000
1215#define DDRCDR_PZ_MAXZ 0x00000000
1216#define DDRCDR_PZ_HIZ 0x20000000
1217#define DDRCDR_PZ_NOMZ 0x30000000
1218#define DDRCDR_PZ_LOZ 0x38000000
1219#define DDRCDR_PZ_MINZ 0x3C000000
1220#define DDRCDR_NZ 0x3C000000
1221#define DDRCDR_NZ_MAXZ 0x00000000
1222#define DDRCDR_NZ_HIZ 0x02000000
1223#define DDRCDR_NZ_NOMZ 0x03000000
1224#define DDRCDR_NZ_LOZ 0x03800000
1225#define DDRCDR_NZ_MINZ 0x03C00000
1226#define DDRCDR_ODT 0x00080000
1227#define DDRCDR_DDR_CFG 0x00040000
1228#define DDRCDR_M_ODR 0x00000002
1229#define DDRCDR_Q_DRN 0x00000001
1230
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001231/* PCIE Bridge Register
1232*/
1233#define PEX_CSB_CTRL_OBPIOE 0x00000001
1234#define PEX_CSB_CTRL_IBPIOE 0x00000002
1235#define PEX_CSB_CTRL_WDMAE 0x00000004
1236#define PEX_CSB_CTRL_RDMAE 0x00000008
1237
1238#define PEX_CSB_OBCTRL_PIOE 0x00000001
1239#define PEX_CSB_OBCTRL_MEMWE 0x00000002
1240#define PEX_CSB_OBCTRL_IOWE 0x00000004
1241#define PEX_CSB_OBCTRL_CFGWE 0x00000008
1242
1243#define PEX_CSB_IBCTRL_PIOE 0x00000001
1244
1245#define PEX_OWAR_EN 0x00000001
1246#define PEX_OWAR_TYPE_CFG 0x00000000
1247#define PEX_OWAR_TYPE_IO 0x00000002
1248#define PEX_OWAR_TYPE_MEM 0x00000004
1249#define PEX_OWAR_RLXO 0x00000008
1250#define PEX_OWAR_NANP 0x00000010
1251#define PEX_OWAR_SIZE 0xFFFFF000
1252
1253#define PEX_IWAR_EN 0x00000001
1254#define PEX_IWAR_TYPE_INT 0x00000000
1255#define PEX_IWAR_TYPE_PF 0x00000004
1256#define PEX_IWAR_TYPE_NO_PF 0x00000006
1257#define PEX_IWAR_NSOV 0x00000008
1258#define PEX_IWAR_NSNP 0x00000010
1259#define PEX_IWAR_SIZE 0xFFFFF000
1260#define PEX_IWAR_SIZE_1M 0x000FF000
1261#define PEX_IWAR_SIZE_2M 0x001FF000
1262#define PEX_IWAR_SIZE_4M 0x003FF000
1263#define PEX_IWAR_SIZE_8M 0x007FF000
1264#define PEX_IWAR_SIZE_16M 0x00FFF000
1265#define PEX_IWAR_SIZE_32M 0x01FFF000
1266#define PEX_IWAR_SIZE_64M 0x03FFF000
1267#define PEX_IWAR_SIZE_128M 0x07FFF000
1268#define PEX_IWAR_SIZE_256M 0x0FFFF000
1269
1270#define PEX_GCLK_RATIO 0x440
1271
Scott Wood49ea3b62007-04-16 14:34:21 -05001272#ifndef __ASSEMBLY__
1273struct pci_region;
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001274void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
Ira Snyder75f35202009-01-12 13:32:26 -08001275void mpc83xx_pcislave_unlock(int bus);
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001276void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
Scott Wood49ea3b62007-04-16 14:34:21 -05001277#endif
1278
Eran Libertyf046ccd2005-07-28 10:08:46 -05001279#endif /* __MPC83XX_H__ */