wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
wdenk | 85ec0bc | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 26 | #include <asm/arch/AT91RM9200.h> |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 27 | |
| 28 | /* ------------------------------------------------------------------------- */ |
| 29 | /* |
| 30 | * Miscelaneous platform dependent initialisations |
| 31 | */ |
| 32 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 33 | int board_init (void) |
| 34 | { |
| 35 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 36 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 37 | /* Enable Ctrlc */ |
| 38 | console_init_f (); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 39 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 40 | /* Correct IRDA resistor problem */ |
| 41 | /* Set PA23_TXD in Output */ |
| 42 | (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 43 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 44 | /* memory and cpu-speed are setup before relocation */ |
| 45 | /* so we do _nothing_ here */ |
| 46 | |
| 47 | /* arch number of AT91RM9200DK-Board */ |
wdenk | 731215e | 2004-10-10 18:41:04 +0000 | [diff] [blame] | 48 | gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 49 | /* adress of boot parameters */ |
| 50 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 51 | |
| 52 | return 0; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 53 | } |
| 54 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 55 | int dram_init (void) |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 56 | { |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 57 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 58 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 59 | gd->bd->bi_dram[0].start = PHYS_SDRAM; |
| 60 | gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
| 61 | return 0; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | /* |
| 65 | * Disk On Chip (NAND) Millenium initialization. |
| 66 | * The NAND lives in the CS2* space |
| 67 | */ |
| 68 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
wdenk | a43278a | 2003-09-11 19:48:06 +0000 | [diff] [blame] | 69 | extern ulong nand_probe (ulong physadr); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 70 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 71 | #define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ |
| 72 | void nand_init (void) |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 73 | { |
| 74 | /* Setup Smart Media, fitst enable the address range of CS3 */ |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 75 | *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; |
| 76 | /* set the bus interface characteristics based on |
| 77 | tDS Data Set up Time 30 - ns |
| 78 | tDH Data Hold Time 20 - ns |
| 79 | tALS ALE Set up Time 20 - ns |
| 80 | 16ns at 60 MHz ~= 3 */ |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 81 | /*memory mapping structures */ |
| 82 | #define SM_ID_RWH (5 << 28) |
| 83 | #define SM_RWH (1 << 28) |
| 84 | #define SM_RWS (0 << 24) |
| 85 | #define SM_TDF (1 << 8) |
| 86 | #define SM_NWS (3) |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 87 | AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | |
| 88 | AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | |
| 89 | SM_TDF | AT91C_SMC2_WSEN | SM_NWS); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 90 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 91 | /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ |
| 92 | *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | |
| 93 | AT91C_PC3_BFBAA_SMWE; |
| 94 | *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | |
| 95 | AT91C_PC3_BFBAA_SMWE; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 96 | |
| 97 | /* Configure PC2 as input (signal READY of the SmartMedia) */ |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 98 | *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ |
| 99 | *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 100 | |
| 101 | /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 102 | *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ |
| 103 | *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 104 | |
wdenk | 8b07a11 | 2004-07-10 21:45:47 +0000 | [diff] [blame] | 105 | /* PIOB and PIOC clock enabling */ |
| 106 | *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; |
| 107 | *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; |
| 108 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 109 | if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) |
wdenk | a43278a | 2003-09-11 19:48:06 +0000 | [diff] [blame] | 110 | printf (" No SmartMedia card inserted\n"); |
| 111 | #ifdef DEBUG |
| 112 | printf (" SmartMedia card inserted\n"); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 113 | |
wdenk | 2abbe07 | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 114 | printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); |
wdenk | a43278a | 2003-09-11 19:48:06 +0000 | [diff] [blame] | 115 | #endif |
| 116 | printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 117 | } |
| 118 | #endif |