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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
wdenk85ec0bc2003-03-31 16:34:49 +000026#include <asm/arch/AT91RM9200.h>
wdenkdc7c9a12003-03-26 06:55:25 +000027
28/* ------------------------------------------------------------------------- */
29/*
30 * Miscelaneous platform dependent initialisations
31 */
32
wdenk2abbe072003-06-16 23:50:08 +000033int board_init (void)
34{
35 DECLARE_GLOBAL_DATA_PTR;
wdenkdc7c9a12003-03-26 06:55:25 +000036
wdenk2abbe072003-06-16 23:50:08 +000037 /* Enable Ctrlc */
38 console_init_f ();
wdenkdc7c9a12003-03-26 06:55:25 +000039
wdenk2abbe072003-06-16 23:50:08 +000040 /* Correct IRDA resistor problem */
41 /* Set PA23_TXD in Output */
42 (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
wdenkdc7c9a12003-03-26 06:55:25 +000043
wdenk2abbe072003-06-16 23:50:08 +000044 /* memory and cpu-speed are setup before relocation */
45 /* so we do _nothing_ here */
46
47 /* arch number of AT91RM9200DK-Board */
wdenk731215e2004-10-10 18:41:04 +000048 gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
wdenk2abbe072003-06-16 23:50:08 +000049 /* adress of boot parameters */
50 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
51
52 return 0;
wdenkdc7c9a12003-03-26 06:55:25 +000053}
54
wdenk2abbe072003-06-16 23:50:08 +000055int dram_init (void)
wdenkdc7c9a12003-03-26 06:55:25 +000056{
wdenk2abbe072003-06-16 23:50:08 +000057 DECLARE_GLOBAL_DATA_PTR;
wdenkdc7c9a12003-03-26 06:55:25 +000058
wdenk2abbe072003-06-16 23:50:08 +000059 gd->bd->bi_dram[0].start = PHYS_SDRAM;
60 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
61 return 0;
wdenkdc7c9a12003-03-26 06:55:25 +000062}
63
64/*
65 * Disk On Chip (NAND) Millenium initialization.
66 * The NAND lives in the CS2* space
67 */
68#if (CONFIG_COMMANDS & CFG_CMD_NAND)
wdenka43278a2003-09-11 19:48:06 +000069extern ulong nand_probe (ulong physadr);
wdenkdc7c9a12003-03-26 06:55:25 +000070
wdenk2abbe072003-06-16 23:50:08 +000071#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
72void nand_init (void)
wdenkdc7c9a12003-03-26 06:55:25 +000073{
74 /* Setup Smart Media, fitst enable the address range of CS3 */
wdenk2abbe072003-06-16 23:50:08 +000075 *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
76 /* set the bus interface characteristics based on
77 tDS Data Set up Time 30 - ns
78 tDH Data Hold Time 20 - ns
79 tALS ALE Set up Time 20 - ns
80 16ns at 60 MHz ~= 3 */
wdenkdc7c9a12003-03-26 06:55:25 +000081/*memory mapping structures */
82#define SM_ID_RWH (5 << 28)
83#define SM_RWH (1 << 28)
84#define SM_RWS (0 << 24)
85#define SM_TDF (1 << 8)
86#define SM_NWS (3)
wdenk2abbe072003-06-16 23:50:08 +000087 AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
88 AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
89 SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
wdenkdc7c9a12003-03-26 06:55:25 +000090
wdenk2abbe072003-06-16 23:50:08 +000091 /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
92 *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
93 AT91C_PC3_BFBAA_SMWE;
94 *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
95 AT91C_PC3_BFBAA_SMWE;
wdenkdc7c9a12003-03-26 06:55:25 +000096
97 /* Configure PC2 as input (signal READY of the SmartMedia) */
wdenk2abbe072003-06-16 23:50:08 +000098 *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
99 *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
wdenkdc7c9a12003-03-26 06:55:25 +0000100
101 /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
wdenk2abbe072003-06-16 23:50:08 +0000102 *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
103 *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
wdenkdc7c9a12003-03-26 06:55:25 +0000104
wdenk8b07a112004-07-10 21:45:47 +0000105 /* PIOB and PIOC clock enabling */
106 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
107 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
108
wdenk2abbe072003-06-16 23:50:08 +0000109 if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
wdenka43278a2003-09-11 19:48:06 +0000110 printf (" No SmartMedia card inserted\n");
111#ifdef DEBUG
112 printf (" SmartMedia card inserted\n");
wdenkdc7c9a12003-03-26 06:55:25 +0000113
wdenk2abbe072003-06-16 23:50:08 +0000114 printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
wdenka43278a2003-09-11 19:48:06 +0000115#endif
116 printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
wdenkdc7c9a12003-03-26 06:55:25 +0000117}
118#endif