blob: c65397367662e1fae7a9a579ed525e5b68384f38 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutcb0b6b02018-04-13 23:51:33 +02002/*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasutcb0b6b02018-04-13 23:51:33 +02005 */
6
7#include <common.h>
8#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -07009#include <cpu_func.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +020010#include <fdtdec.h>
11#include <mmc.h>
12#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070013#include <dm/device_compat.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +020014#include <dm/pinctrl.h>
15#include <linux/compat.h>
Simon Glassc05ed002020-05-10 11:40:11 -060016#include <linux/delay.h>
Masahiro Yamada9d86b892020-02-14 16:40:19 +090017#include <linux/dma-mapping.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +020018#include <linux/io.h>
19#include <linux/sizes.h>
20#include <power/regulator.h>
21#include <asm/unaligned.h>
22
23#include "tmio-common.h"
24
25DECLARE_GLOBAL_DATA_PTR;
26
27static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
28{
29 return readq(priv->regbase + (reg << 1));
30}
31
32static void tmio_sd_writeq(struct tmio_sd_priv *priv,
33 u64 val, unsigned int reg)
34{
35 writeq(val, priv->regbase + (reg << 1));
36}
37
38static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
39{
40 return readw(priv->regbase + (reg >> 1));
41}
42
43static void tmio_sd_writew(struct tmio_sd_priv *priv,
44 u16 val, unsigned int reg)
45{
46 writew(val, priv->regbase + (reg >> 1));
47}
48
49u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
50{
51 u32 val;
52
53 if (priv->caps & TMIO_SD_CAP_64BIT)
54 return readl(priv->regbase + (reg << 1));
55 else if (priv->caps & TMIO_SD_CAP_16BIT) {
56 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
57 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
58 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
59 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
60 }
61 return val;
62 } else
63 return readl(priv->regbase + reg);
64}
65
66void tmio_sd_writel(struct tmio_sd_priv *priv,
67 u32 val, unsigned int reg)
68{
69 if (priv->caps & TMIO_SD_CAP_64BIT)
70 writel(val, priv->regbase + (reg << 1));
71 else if (priv->caps & TMIO_SD_CAP_16BIT) {
72 writew(val & 0xffff, priv->regbase + (reg >> 1));
73 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
74 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
75 reg == TMIO_SD_ARG)
76 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
77 } else
78 writel(val, priv->regbase + reg);
79}
80
Marek Vasut33633eb2018-10-30 22:05:54 +010081static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
Marek Vasutcb0b6b02018-04-13 23:51:33 +020082{
83 struct tmio_sd_priv *priv = dev_get_priv(dev);
84 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
85
86 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
87 /*
88 * TIMEOUT must be returned for unsupported command. Do not
89 * display error log since this might be a part of sequence to
90 * distinguish between SD and MMC.
91 */
92 return -ETIMEDOUT;
93 }
94
95 if (info2 & TMIO_SD_INFO2_ERR_TO) {
96 dev_err(dev, "timeout error\n");
97 return -ETIMEDOUT;
98 }
99
100 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
101 TMIO_SD_INFO2_ERR_IDX)) {
Marek Vasut33633eb2018-10-30 22:05:54 +0100102 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
103 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
104 dev_err(dev, "communication out of sync\n");
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200105 return -EILSEQ;
106 }
107
108 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
109 TMIO_SD_INFO2_ERR_ILW)) {
110 dev_err(dev, "illegal access\n");
111 return -EIO;
112 }
113
114 return 0;
115}
116
Marek Vasut33633eb2018-10-30 22:05:54 +0100117static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
118 unsigned int reg, u32 flag)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200119{
120 struct tmio_sd_priv *priv = dev_get_priv(dev);
121 long wait = 1000000;
122 int ret;
123
124 while (!(tmio_sd_readl(priv, reg) & flag)) {
125 if (wait-- < 0) {
126 dev_err(dev, "timeout\n");
127 return -ETIMEDOUT;
128 }
129
Marek Vasut33633eb2018-10-30 22:05:54 +0100130 ret = tmio_sd_check_error(dev, cmd);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200131 if (ret)
132 return ret;
133
134 udelay(1);
135 }
136
137 return 0;
138}
139
140#define tmio_pio_read_fifo(__width, __suffix) \
141static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
142 char *pbuf, uint blksz) \
143{ \
144 u##__width *buf = (u##__width *)pbuf; \
145 int i; \
146 \
147 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
148 for (i = 0; i < blksz / ((__width) / 8); i++) { \
149 *buf++ = tmio_sd_read##__suffix(priv, \
150 TMIO_SD_BUF); \
151 } \
152 } else { \
153 for (i = 0; i < blksz / ((__width) / 8); i++) { \
154 u##__width data; \
155 data = tmio_sd_read##__suffix(priv, \
156 TMIO_SD_BUF); \
157 put_unaligned(data, buf++); \
158 } \
159 } \
160}
161
162tmio_pio_read_fifo(64, q)
163tmio_pio_read_fifo(32, l)
164tmio_pio_read_fifo(16, w)
165
Marek Vasut33633eb2018-10-30 22:05:54 +0100166static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
167 char *pbuf, uint blocksize)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200168{
169 struct tmio_sd_priv *priv = dev_get_priv(dev);
170 int ret;
171
172 /* wait until the buffer is filled with data */
Marek Vasut33633eb2018-10-30 22:05:54 +0100173 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
174 TMIO_SD_INFO2_BRE);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200175 if (ret)
176 return ret;
177
178 /*
179 * Clear the status flag _before_ read the buffer out because
180 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
181 */
182 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
183
184 if (priv->caps & TMIO_SD_CAP_64BIT)
185 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
186 else if (priv->caps & TMIO_SD_CAP_16BIT)
187 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
188 else
189 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
190
191 return 0;
192}
193
194#define tmio_pio_write_fifo(__width, __suffix) \
195static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
196 const char *pbuf, uint blksz)\
197{ \
198 const u##__width *buf = (const u##__width *)pbuf; \
199 int i; \
200 \
201 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
202 for (i = 0; i < blksz / ((__width) / 8); i++) { \
203 tmio_sd_write##__suffix(priv, *buf++, \
204 TMIO_SD_BUF); \
205 } \
206 } else { \
207 for (i = 0; i < blksz / ((__width) / 8); i++) { \
208 u##__width data = get_unaligned(buf++); \
209 tmio_sd_write##__suffix(priv, data, \
210 TMIO_SD_BUF); \
211 } \
212 } \
213}
214
215tmio_pio_write_fifo(64, q)
216tmio_pio_write_fifo(32, l)
217tmio_pio_write_fifo(16, w)
218
Marek Vasut33633eb2018-10-30 22:05:54 +0100219static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200220 const char *pbuf, uint blocksize)
221{
222 struct tmio_sd_priv *priv = dev_get_priv(dev);
223 int ret;
224
225 /* wait until the buffer becomes empty */
Marek Vasut33633eb2018-10-30 22:05:54 +0100226 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
227 TMIO_SD_INFO2_BWE);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200228 if (ret)
229 return ret;
230
231 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
232
233 if (priv->caps & TMIO_SD_CAP_64BIT)
234 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
235 else if (priv->caps & TMIO_SD_CAP_16BIT)
236 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
237 else
238 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
239
240 return 0;
241}
242
Marek Vasut33633eb2018-10-30 22:05:54 +0100243static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
244 struct mmc_data *data)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200245{
246 const char *src = data->src;
247 char *dest = data->dest;
248 int i, ret;
249
250 for (i = 0; i < data->blocks; i++) {
251 if (data->flags & MMC_DATA_READ)
Marek Vasut33633eb2018-10-30 22:05:54 +0100252 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200253 data->blocksize);
254 else
Marek Vasut33633eb2018-10-30 22:05:54 +0100255 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200256 data->blocksize);
257 if (ret)
258 return ret;
259
260 if (data->flags & MMC_DATA_READ)
261 dest += data->blocksize;
262 else
263 src += data->blocksize;
264 }
265
266 return 0;
267}
268
269static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
270 dma_addr_t dma_addr)
271{
272 u32 tmp;
273
274 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
275 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
276
277 /* enable DMA */
278 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
279 tmp |= TMIO_SD_EXTMODE_DMA_EN;
280 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
281
282 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
283
284 /* suppress the warning "right shift count >= width of type" */
285 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
286
287 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
288
289 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
290}
291
292static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
293 unsigned int blocks)
294{
295 struct tmio_sd_priv *priv = dev_get_priv(dev);
296 long wait = 1000000 + 10 * blocks;
297
298 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
299 if (wait-- < 0) {
300 dev_err(dev, "timeout during DMA\n");
301 return -ETIMEDOUT;
302 }
303
304 udelay(10);
305 }
306
307 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
308 dev_err(dev, "error during DMA\n");
309 return -EIO;
310 }
311
312 return 0;
313}
314
315static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
316{
317 struct tmio_sd_priv *priv = dev_get_priv(dev);
318 size_t len = data->blocks * data->blocksize;
319 void *buf;
320 enum dma_data_direction dir;
321 dma_addr_t dma_addr;
322 u32 poll_flag, tmp;
323 int ret;
324
325 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
326
327 if (data->flags & MMC_DATA_READ) {
328 buf = data->dest;
329 dir = DMA_FROM_DEVICE;
330 /*
331 * The DMA READ completion flag position differs on Socionext
332 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
Marek Vasut992bcf42019-01-11 23:45:54 +0100333 * bit 17 is a hardware bug and forbidden. It is either bit 17
334 * or bit 20 on Renesas SoCs, depending on SoC.
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200335 */
Marek Vasut992bcf42019-01-11 23:45:54 +0100336 poll_flag = priv->read_poll_flag;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200337 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
338 } else {
339 buf = (void *)data->src;
340 dir = DMA_TO_DEVICE;
341 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
342 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
343 }
344
345 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
346
Vignesh Raghavendraeaa8b042020-01-16 14:23:46 +0530347 dma_addr = dma_map_single(buf, len, dir);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200348
349 tmio_sd_dma_start(priv, dma_addr);
350
351 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
352
Marek Vasutcbbe6942019-01-11 23:38:07 +0100353 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
354 udelay(1);
355
Masahiro Yamada950c5962020-02-14 16:40:18 +0900356 dma_unmap_single(dma_addr, len, dir);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200357
358 return ret;
359}
360
361/* check if the address is DMA'able */
Hiroyuki Yokoyama902af102020-03-07 17:32:59 +0100362static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200363{
Hiroyuki Yokoyama902af102020-03-07 17:32:59 +0100364 uintptr_t addr = (uintptr_t)data->src;
Marek Vasut92bde152018-10-03 00:44:37 +0200365
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200366 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
367 return false;
368
Marek Vasutbeced532018-10-03 00:46:24 +0200369#if defined(CONFIG_RCAR_GEN3)
Hiroyuki Yokoyama902af102020-03-07 17:32:59 +0100370 if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
371 return false;
Marek Vasutbeced532018-10-03 00:46:24 +0200372 /* Gen3 DMA has 32bit limit */
373 if (addr >> 32)
374 return false;
375#endif
376
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200377#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
378 defined(CONFIG_SPL_BUILD)
379 /*
380 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
381 * of L2, which is unreachable from the DMA engine.
382 */
383 if (addr < CONFIG_SPL_STACK)
384 return false;
385#endif
386
387 return true;
388}
389
390int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
391 struct mmc_data *data)
392{
393 struct tmio_sd_priv *priv = dev_get_priv(dev);
394 int ret;
395 u32 tmp;
396
397 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
398 dev_err(dev, "command busy\n");
399 return -EBUSY;
400 }
401
402 /* clear all status flags */
403 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
404 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
405
406 /* disable DMA once */
407 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
408 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
409 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
410
411 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
412
413 tmp = cmd->cmdidx;
414
415 if (data) {
416 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
417 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
418
419 /* Do not send CMD12 automatically */
420 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
421
422 if (data->blocks > 1)
423 tmp |= TMIO_SD_CMD_MULTI;
424
425 if (data->flags & MMC_DATA_READ)
426 tmp |= TMIO_SD_CMD_RD;
427 }
428
429 /*
430 * Do not use the response type auto-detection on this hardware.
431 * CMD8, for example, has different response types on SD and eMMC,
432 * while this controller always assumes the response type for SD.
433 * Set the response type manually.
434 */
435 switch (cmd->resp_type) {
436 case MMC_RSP_NONE:
437 tmp |= TMIO_SD_CMD_RSP_NONE;
438 break;
439 case MMC_RSP_R1:
440 tmp |= TMIO_SD_CMD_RSP_R1;
441 break;
442 case MMC_RSP_R1b:
443 tmp |= TMIO_SD_CMD_RSP_R1B;
444 break;
445 case MMC_RSP_R2:
446 tmp |= TMIO_SD_CMD_RSP_R2;
447 break;
448 case MMC_RSP_R3:
449 tmp |= TMIO_SD_CMD_RSP_R3;
450 break;
451 default:
452 dev_err(dev, "unknown response type\n");
453 return -EINVAL;
454 }
455
456 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
457 cmd->cmdidx, tmp, cmd->cmdarg);
458 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
459
Marek Vasut33633eb2018-10-30 22:05:54 +0100460 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
461 TMIO_SD_INFO1_RSP);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200462 if (ret)
463 return ret;
464
465 if (cmd->resp_type & MMC_RSP_136) {
466 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
467 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
468 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
469 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
470
471 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
472 ((rsp_103_72 & 0xff000000) >> 24);
473 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
474 ((rsp_71_40 & 0xff000000) >> 24);
475 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
476 ((rsp_39_8 & 0xff000000) >> 24);
477 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
478 } else {
479 /* bit 39-8 */
480 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
481 }
482
483 if (data) {
484 /* use DMA if the HW supports it and the buffer is aligned */
485 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
Hiroyuki Yokoyama902af102020-03-07 17:32:59 +0100486 tmio_sd_addr_is_dmaable(data))
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200487 ret = tmio_sd_dma_xfer(dev, data);
488 else
Marek Vasut33633eb2018-10-30 22:05:54 +0100489 ret = tmio_sd_pio_xfer(dev, cmd, data);
Marek Vasutb22c8d02018-10-30 21:53:29 +0100490 if (ret)
491 return ret;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200492
Marek Vasut33633eb2018-10-30 22:05:54 +0100493 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
494 TMIO_SD_INFO1_CMP);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200495 if (ret)
496 return ret;
497 }
498
Marek Vasut33633eb2018-10-30 22:05:54 +0100499 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
Marek Vasutb22c8d02018-10-30 21:53:29 +0100500 TMIO_SD_INFO2_SCLKDIVEN);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200501}
502
503static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
504 struct mmc *mmc)
505{
506 u32 val, tmp;
507
508 switch (mmc->bus_width) {
509 case 0:
510 case 1:
511 val = TMIO_SD_OPTION_WIDTH_1;
512 break;
513 case 4:
514 val = TMIO_SD_OPTION_WIDTH_4;
515 break;
516 case 8:
517 val = TMIO_SD_OPTION_WIDTH_8;
518 break;
519 default:
520 return -EINVAL;
521 }
522
523 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
524 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
525 tmp |= val;
526 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
527
528 return 0;
529}
530
531static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
532 struct mmc *mmc)
533{
534 u32 tmp;
535
536 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
537 if (mmc->ddr_mode)
538 tmp |= TMIO_SD_IF_MODE_DDR;
539 else
540 tmp &= ~TMIO_SD_IF_MODE_DDR;
541 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
542}
543
Marek Vasut8ec6a042018-06-13 08:02:55 +0200544static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
545{
546 return priv->clk_get_rate(priv);
547}
548
Marek Vasuted427da2018-11-15 22:01:33 +0100549static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200550{
551 unsigned int divisor;
Marek Vasuted427da2018-11-15 22:01:33 +0100552 u32 tmp, val = 0;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200553 ulong mclk;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200554
Marek Vasuted427da2018-11-15 22:01:33 +0100555 if (mmc->clock) {
556 mclk = tmio_sd_clk_get_rate(priv);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200557
Marek Vasuted427da2018-11-15 22:01:33 +0100558 divisor = DIV_ROUND_UP(mclk, mmc->clock);
Marek Vasut8ec6a042018-06-13 08:02:55 +0200559
Marek Vasuted427da2018-11-15 22:01:33 +0100560 /* Do not set divider to 0xff in DDR mode */
561 if (mmc->ddr_mode && (divisor == 1))
562 divisor = 2;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200563
Marek Vasuted427da2018-11-15 22:01:33 +0100564 if (divisor <= 1)
565 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
566 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
567 else if (divisor <= 2)
568 val = TMIO_SD_CLKCTL_DIV2;
569 else if (divisor <= 4)
570 val = TMIO_SD_CLKCTL_DIV4;
571 else if (divisor <= 8)
572 val = TMIO_SD_CLKCTL_DIV8;
573 else if (divisor <= 16)
574 val = TMIO_SD_CLKCTL_DIV16;
575 else if (divisor <= 32)
576 val = TMIO_SD_CLKCTL_DIV32;
577 else if (divisor <= 64)
578 val = TMIO_SD_CLKCTL_DIV64;
579 else if (divisor <= 128)
580 val = TMIO_SD_CLKCTL_DIV128;
581 else if (divisor <= 256)
582 val = TMIO_SD_CLKCTL_DIV256;
583 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
584 val = TMIO_SD_CLKCTL_DIV512;
585 else
586 val = TMIO_SD_CLKCTL_DIV1024;
587 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200588
589 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
Marek Vasuted427da2018-11-15 22:01:33 +0100590 if (mmc->clock &&
591 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
592 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
593 /*
594 * Stop the clock before changing its rate
595 * to avoid a glitch signal
596 */
597 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
598 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200599
Marek Vasuted427da2018-11-15 22:01:33 +0100600 /* Change the clock rate. */
601 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
602 tmp |= val;
603 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200604
Marek Vasuted427da2018-11-15 22:01:33 +0100605 /* Enable or Disable the clock */
606 if (mmc->clk_disable) {
Marek Vasut59d529a2018-06-13 08:02:55 +0200607 tmp |= TMIO_SD_CLKCTL_OFFEN;
608 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
Marek Vasuted427da2018-11-15 22:01:33 +0100609 } else {
610 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
611 tmp |= TMIO_SD_CLKCTL_SCLKEN;
Marek Vasut59d529a2018-06-13 08:02:55 +0200612 }
Marek Vasuted427da2018-11-15 22:01:33 +0100613
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200614 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
615
616 udelay(1000);
617}
618
619static void tmio_sd_set_pins(struct udevice *dev)
620{
621 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
622
623#ifdef CONFIG_DM_REGULATOR
624 struct tmio_sd_priv *priv = dev_get_priv(dev);
625
626 if (priv->vqmmc_dev) {
627 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
628 regulator_set_value(priv->vqmmc_dev, 1800000);
629 else
630 regulator_set_value(priv->vqmmc_dev, 3300000);
631 regulator_set_enable(priv->vqmmc_dev, true);
632 }
633#endif
634
635#ifdef CONFIG_PINCTRL
Marek Vasut645a5752018-10-28 13:54:10 +0100636 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200637 pinctrl_select_state(dev, "state_uhs");
Marek Vasut645a5752018-10-28 13:54:10 +0100638 else
639 pinctrl_select_state(dev, "default");
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200640#endif
641}
642
643int tmio_sd_set_ios(struct udevice *dev)
644{
645 struct tmio_sd_priv *priv = dev_get_priv(dev);
646 struct mmc *mmc = mmc_get_mmc_dev(dev);
647 int ret;
648
649 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
650 mmc->clock, mmc->ddr_mode, mmc->bus_width);
651
Marek Vasut8171f992018-06-13 08:02:55 +0200652 tmio_sd_set_clk_rate(priv, mmc);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200653 ret = tmio_sd_set_bus_width(priv, mmc);
654 if (ret)
655 return ret;
656 tmio_sd_set_ddr_mode(priv, mmc);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200657 tmio_sd_set_pins(dev);
658
659 return 0;
660}
661
662int tmio_sd_get_cd(struct udevice *dev)
663{
664 struct tmio_sd_priv *priv = dev_get_priv(dev);
665
666 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
667 return 1;
668
669 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
670 TMIO_SD_INFO1_CD);
671}
672
673static void tmio_sd_host_init(struct tmio_sd_priv *priv)
674{
675 u32 tmp;
676
677 /* soft reset of the host */
678 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
679 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
680 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
681 tmp |= TMIO_SD_SOFT_RST_RSTX;
682 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
683
684 /* FIXME: implement eMMC hw_reset */
685
686 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
687
688 /*
689 * Connected to 32bit AXI.
690 * This register dropped backward compatibility at version 0x10.
691 * Write an appropriate value depending on the IP version.
692 */
Marek Vasut4c80f112019-02-14 15:16:24 +0100693 if (priv->version >= 0x10) {
694 if (priv->caps & TMIO_SD_CAP_64BIT)
Marek Vasut5d688842019-02-19 19:20:14 +0100695 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
Marek Vasut4c80f112019-02-14 15:16:24 +0100696 else
697 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
698 } else {
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200699 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
Marek Vasut4c80f112019-02-14 15:16:24 +0100700 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200701
702 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
703 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
704 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
705 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
706 }
707}
708
709int tmio_sd_bind(struct udevice *dev)
710{
711 struct tmio_sd_plat *plat = dev_get_platdata(dev);
712
713 return mmc_bind(dev, &plat->mmc, &plat->cfg);
714}
715
716int tmio_sd_probe(struct udevice *dev, u32 quirks)
717{
718 struct tmio_sd_plat *plat = dev_get_platdata(dev);
719 struct tmio_sd_priv *priv = dev_get_priv(dev);
720 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
721 fdt_addr_t base;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200722 ulong mclk;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200723 int ret;
724
Masahiro Yamada25484932020-07-17 14:36:48 +0900725 base = dev_read_addr(dev);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200726 if (base == FDT_ADDR_T_NONE)
727 return -EINVAL;
728
729 priv->regbase = devm_ioremap(dev, base, SZ_2K);
730 if (!priv->regbase)
731 return -ENOMEM;
732
733#ifdef CONFIG_DM_REGULATOR
734 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
Marek Vasutc83da2e2018-06-13 08:02:55 +0200735 if (priv->vqmmc_dev)
736 regulator_set_value(priv->vqmmc_dev, 3300000);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200737#endif
738
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200739 ret = mmc_of_parse(dev, &plat->cfg);
740 if (ret < 0) {
741 dev_err(dev, "failed to parse host caps\n");
742 return ret;
743 }
744
745 plat->cfg.name = dev->name;
746 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
747
748 if (quirks)
749 priv->caps = quirks;
750
751 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
752 TMIO_SD_VERSION_IP;
753 dev_dbg(dev, "version %x\n", priv->version);
754 if (priv->version >= 0x10) {
755 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
756 priv->caps |= TMIO_SD_CAP_DIV1024;
757 }
758
759 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
760 NULL))
761 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
762
763 tmio_sd_host_init(priv);
764
Marek Vasut8ec6a042018-06-13 08:02:55 +0200765 mclk = tmio_sd_clk_get_rate(priv);
766
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200767 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200768 plat->cfg.f_min = mclk /
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200769 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
Marek Vasut8ec6a042018-06-13 08:02:55 +0200770 plat->cfg.f_max = mclk;
Marek Vasutc453fe32019-03-18 23:43:10 +0100771 if (quirks & TMIO_SD_CAP_16BIT)
772 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
773 else
774 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200775
776 upriv->mmc = &plat->mmc;
777
778 return 0;
779}