blob: 5a8506dcb6bdecadaccbb5db5690be5682e9997e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutcb0b6b02018-04-13 23:51:33 +02002/*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasutcb0b6b02018-04-13 23:51:33 +02005 */
6
Vignesh Raghavendraeaa8b042020-01-16 14:23:46 +05307#include <asm/dma-mapping.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +02008#include <common.h>
9#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070010#include <cpu_func.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +020011#include <fdtdec.h>
12#include <mmc.h>
13#include <dm.h>
14#include <dm/pinctrl.h>
15#include <linux/compat.h>
16#include <linux/dma-direction.h>
17#include <linux/io.h>
18#include <linux/sizes.h>
19#include <power/regulator.h>
20#include <asm/unaligned.h>
21
22#include "tmio-common.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
27{
28 return readq(priv->regbase + (reg << 1));
29}
30
31static void tmio_sd_writeq(struct tmio_sd_priv *priv,
32 u64 val, unsigned int reg)
33{
34 writeq(val, priv->regbase + (reg << 1));
35}
36
37static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
38{
39 return readw(priv->regbase + (reg >> 1));
40}
41
42static void tmio_sd_writew(struct tmio_sd_priv *priv,
43 u16 val, unsigned int reg)
44{
45 writew(val, priv->regbase + (reg >> 1));
46}
47
48u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
49{
50 u32 val;
51
52 if (priv->caps & TMIO_SD_CAP_64BIT)
53 return readl(priv->regbase + (reg << 1));
54 else if (priv->caps & TMIO_SD_CAP_16BIT) {
55 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
56 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
57 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
58 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
59 }
60 return val;
61 } else
62 return readl(priv->regbase + reg);
63}
64
65void tmio_sd_writel(struct tmio_sd_priv *priv,
66 u32 val, unsigned int reg)
67{
68 if (priv->caps & TMIO_SD_CAP_64BIT)
69 writel(val, priv->regbase + (reg << 1));
70 else if (priv->caps & TMIO_SD_CAP_16BIT) {
71 writew(val & 0xffff, priv->regbase + (reg >> 1));
72 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
73 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
74 reg == TMIO_SD_ARG)
75 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
76 } else
77 writel(val, priv->regbase + reg);
78}
79
Marek Vasut33633eb2018-10-30 22:05:54 +010080static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
Marek Vasutcb0b6b02018-04-13 23:51:33 +020081{
82 struct tmio_sd_priv *priv = dev_get_priv(dev);
83 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
84
85 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
86 /*
87 * TIMEOUT must be returned for unsupported command. Do not
88 * display error log since this might be a part of sequence to
89 * distinguish between SD and MMC.
90 */
91 return -ETIMEDOUT;
92 }
93
94 if (info2 & TMIO_SD_INFO2_ERR_TO) {
95 dev_err(dev, "timeout error\n");
96 return -ETIMEDOUT;
97 }
98
99 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
100 TMIO_SD_INFO2_ERR_IDX)) {
Marek Vasut33633eb2018-10-30 22:05:54 +0100101 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
102 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
103 dev_err(dev, "communication out of sync\n");
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200104 return -EILSEQ;
105 }
106
107 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
108 TMIO_SD_INFO2_ERR_ILW)) {
109 dev_err(dev, "illegal access\n");
110 return -EIO;
111 }
112
113 return 0;
114}
115
Marek Vasut33633eb2018-10-30 22:05:54 +0100116static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
117 unsigned int reg, u32 flag)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200118{
119 struct tmio_sd_priv *priv = dev_get_priv(dev);
120 long wait = 1000000;
121 int ret;
122
123 while (!(tmio_sd_readl(priv, reg) & flag)) {
124 if (wait-- < 0) {
125 dev_err(dev, "timeout\n");
126 return -ETIMEDOUT;
127 }
128
Marek Vasut33633eb2018-10-30 22:05:54 +0100129 ret = tmio_sd_check_error(dev, cmd);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200130 if (ret)
131 return ret;
132
133 udelay(1);
134 }
135
136 return 0;
137}
138
139#define tmio_pio_read_fifo(__width, __suffix) \
140static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
141 char *pbuf, uint blksz) \
142{ \
143 u##__width *buf = (u##__width *)pbuf; \
144 int i; \
145 \
146 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
147 for (i = 0; i < blksz / ((__width) / 8); i++) { \
148 *buf++ = tmio_sd_read##__suffix(priv, \
149 TMIO_SD_BUF); \
150 } \
151 } else { \
152 for (i = 0; i < blksz / ((__width) / 8); i++) { \
153 u##__width data; \
154 data = tmio_sd_read##__suffix(priv, \
155 TMIO_SD_BUF); \
156 put_unaligned(data, buf++); \
157 } \
158 } \
159}
160
161tmio_pio_read_fifo(64, q)
162tmio_pio_read_fifo(32, l)
163tmio_pio_read_fifo(16, w)
164
Marek Vasut33633eb2018-10-30 22:05:54 +0100165static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
166 char *pbuf, uint blocksize)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200167{
168 struct tmio_sd_priv *priv = dev_get_priv(dev);
169 int ret;
170
171 /* wait until the buffer is filled with data */
Marek Vasut33633eb2018-10-30 22:05:54 +0100172 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
173 TMIO_SD_INFO2_BRE);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200174 if (ret)
175 return ret;
176
177 /*
178 * Clear the status flag _before_ read the buffer out because
179 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
180 */
181 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
182
183 if (priv->caps & TMIO_SD_CAP_64BIT)
184 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
185 else if (priv->caps & TMIO_SD_CAP_16BIT)
186 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
187 else
188 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
189
190 return 0;
191}
192
193#define tmio_pio_write_fifo(__width, __suffix) \
194static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
195 const char *pbuf, uint blksz)\
196{ \
197 const u##__width *buf = (const u##__width *)pbuf; \
198 int i; \
199 \
200 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
201 for (i = 0; i < blksz / ((__width) / 8); i++) { \
202 tmio_sd_write##__suffix(priv, *buf++, \
203 TMIO_SD_BUF); \
204 } \
205 } else { \
206 for (i = 0; i < blksz / ((__width) / 8); i++) { \
207 u##__width data = get_unaligned(buf++); \
208 tmio_sd_write##__suffix(priv, data, \
209 TMIO_SD_BUF); \
210 } \
211 } \
212}
213
214tmio_pio_write_fifo(64, q)
215tmio_pio_write_fifo(32, l)
216tmio_pio_write_fifo(16, w)
217
Marek Vasut33633eb2018-10-30 22:05:54 +0100218static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200219 const char *pbuf, uint blocksize)
220{
221 struct tmio_sd_priv *priv = dev_get_priv(dev);
222 int ret;
223
224 /* wait until the buffer becomes empty */
Marek Vasut33633eb2018-10-30 22:05:54 +0100225 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
226 TMIO_SD_INFO2_BWE);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200227 if (ret)
228 return ret;
229
230 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
231
232 if (priv->caps & TMIO_SD_CAP_64BIT)
233 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
234 else if (priv->caps & TMIO_SD_CAP_16BIT)
235 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
236 else
237 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
238
239 return 0;
240}
241
Marek Vasut33633eb2018-10-30 22:05:54 +0100242static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200244{
245 const char *src = data->src;
246 char *dest = data->dest;
247 int i, ret;
248
249 for (i = 0; i < data->blocks; i++) {
250 if (data->flags & MMC_DATA_READ)
Marek Vasut33633eb2018-10-30 22:05:54 +0100251 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200252 data->blocksize);
253 else
Marek Vasut33633eb2018-10-30 22:05:54 +0100254 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200255 data->blocksize);
256 if (ret)
257 return ret;
258
259 if (data->flags & MMC_DATA_READ)
260 dest += data->blocksize;
261 else
262 src += data->blocksize;
263 }
264
265 return 0;
266}
267
268static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
269 dma_addr_t dma_addr)
270{
271 u32 tmp;
272
273 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
274 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
275
276 /* enable DMA */
277 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
278 tmp |= TMIO_SD_EXTMODE_DMA_EN;
279 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
280
281 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
282
283 /* suppress the warning "right shift count >= width of type" */
284 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
285
286 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
287
288 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
289}
290
291static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
292 unsigned int blocks)
293{
294 struct tmio_sd_priv *priv = dev_get_priv(dev);
295 long wait = 1000000 + 10 * blocks;
296
297 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
298 if (wait-- < 0) {
299 dev_err(dev, "timeout during DMA\n");
300 return -ETIMEDOUT;
301 }
302
303 udelay(10);
304 }
305
306 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
307 dev_err(dev, "error during DMA\n");
308 return -EIO;
309 }
310
311 return 0;
312}
313
314static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
315{
316 struct tmio_sd_priv *priv = dev_get_priv(dev);
317 size_t len = data->blocks * data->blocksize;
318 void *buf;
319 enum dma_data_direction dir;
320 dma_addr_t dma_addr;
321 u32 poll_flag, tmp;
322 int ret;
323
324 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
325
326 if (data->flags & MMC_DATA_READ) {
327 buf = data->dest;
328 dir = DMA_FROM_DEVICE;
329 /*
330 * The DMA READ completion flag position differs on Socionext
331 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
Marek Vasut992bcf42019-01-11 23:45:54 +0100332 * bit 17 is a hardware bug and forbidden. It is either bit 17
333 * or bit 20 on Renesas SoCs, depending on SoC.
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200334 */
Marek Vasut992bcf42019-01-11 23:45:54 +0100335 poll_flag = priv->read_poll_flag;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200336 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
337 } else {
338 buf = (void *)data->src;
339 dir = DMA_TO_DEVICE;
340 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
341 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
342 }
343
344 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
345
Vignesh Raghavendraeaa8b042020-01-16 14:23:46 +0530346 dma_addr = dma_map_single(buf, len, dir);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200347
348 tmio_sd_dma_start(priv, dma_addr);
349
350 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
351
Marek Vasutcbbe6942019-01-11 23:38:07 +0100352 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
353 udelay(1);
354
Vignesh Raghavendraeaa8b042020-01-16 14:23:46 +0530355 dma_unmap_single(buf, len, dir);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200356
357 return ret;
358}
359
360/* check if the address is DMA'able */
Marek Vasut92bde152018-10-03 00:44:37 +0200361static bool tmio_sd_addr_is_dmaable(const char *src)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200362{
Marek Vasut92bde152018-10-03 00:44:37 +0200363 uintptr_t addr = (uintptr_t)src;
364
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200365 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
366 return false;
367
Marek Vasutbeced532018-10-03 00:46:24 +0200368#if defined(CONFIG_RCAR_GEN3)
369 /* Gen3 DMA has 32bit limit */
370 if (addr >> 32)
371 return false;
372#endif
373
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200374#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
375 defined(CONFIG_SPL_BUILD)
376 /*
377 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
378 * of L2, which is unreachable from the DMA engine.
379 */
380 if (addr < CONFIG_SPL_STACK)
381 return false;
382#endif
383
384 return true;
385}
386
387int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
388 struct mmc_data *data)
389{
390 struct tmio_sd_priv *priv = dev_get_priv(dev);
391 int ret;
392 u32 tmp;
393
394 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
395 dev_err(dev, "command busy\n");
396 return -EBUSY;
397 }
398
399 /* clear all status flags */
400 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
401 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
402
403 /* disable DMA once */
404 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
405 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
406 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
407
408 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
409
410 tmp = cmd->cmdidx;
411
412 if (data) {
413 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
414 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
415
416 /* Do not send CMD12 automatically */
417 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
418
419 if (data->blocks > 1)
420 tmp |= TMIO_SD_CMD_MULTI;
421
422 if (data->flags & MMC_DATA_READ)
423 tmp |= TMIO_SD_CMD_RD;
424 }
425
426 /*
427 * Do not use the response type auto-detection on this hardware.
428 * CMD8, for example, has different response types on SD and eMMC,
429 * while this controller always assumes the response type for SD.
430 * Set the response type manually.
431 */
432 switch (cmd->resp_type) {
433 case MMC_RSP_NONE:
434 tmp |= TMIO_SD_CMD_RSP_NONE;
435 break;
436 case MMC_RSP_R1:
437 tmp |= TMIO_SD_CMD_RSP_R1;
438 break;
439 case MMC_RSP_R1b:
440 tmp |= TMIO_SD_CMD_RSP_R1B;
441 break;
442 case MMC_RSP_R2:
443 tmp |= TMIO_SD_CMD_RSP_R2;
444 break;
445 case MMC_RSP_R3:
446 tmp |= TMIO_SD_CMD_RSP_R3;
447 break;
448 default:
449 dev_err(dev, "unknown response type\n");
450 return -EINVAL;
451 }
452
453 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
454 cmd->cmdidx, tmp, cmd->cmdarg);
455 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
456
Marek Vasut33633eb2018-10-30 22:05:54 +0100457 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
458 TMIO_SD_INFO1_RSP);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200459 if (ret)
460 return ret;
461
462 if (cmd->resp_type & MMC_RSP_136) {
463 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
464 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
465 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
466 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
467
468 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
469 ((rsp_103_72 & 0xff000000) >> 24);
470 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
471 ((rsp_71_40 & 0xff000000) >> 24);
472 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
473 ((rsp_39_8 & 0xff000000) >> 24);
474 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
475 } else {
476 /* bit 39-8 */
477 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
478 }
479
480 if (data) {
481 /* use DMA if the HW supports it and the buffer is aligned */
482 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
Marek Vasut92bde152018-10-03 00:44:37 +0200483 tmio_sd_addr_is_dmaable(data->src))
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200484 ret = tmio_sd_dma_xfer(dev, data);
485 else
Marek Vasut33633eb2018-10-30 22:05:54 +0100486 ret = tmio_sd_pio_xfer(dev, cmd, data);
Marek Vasutb22c8d02018-10-30 21:53:29 +0100487 if (ret)
488 return ret;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200489
Marek Vasut33633eb2018-10-30 22:05:54 +0100490 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
491 TMIO_SD_INFO1_CMP);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200492 if (ret)
493 return ret;
494 }
495
Marek Vasut33633eb2018-10-30 22:05:54 +0100496 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
Marek Vasutb22c8d02018-10-30 21:53:29 +0100497 TMIO_SD_INFO2_SCLKDIVEN);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200498}
499
500static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
501 struct mmc *mmc)
502{
503 u32 val, tmp;
504
505 switch (mmc->bus_width) {
506 case 0:
507 case 1:
508 val = TMIO_SD_OPTION_WIDTH_1;
509 break;
510 case 4:
511 val = TMIO_SD_OPTION_WIDTH_4;
512 break;
513 case 8:
514 val = TMIO_SD_OPTION_WIDTH_8;
515 break;
516 default:
517 return -EINVAL;
518 }
519
520 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
521 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
522 tmp |= val;
523 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
524
525 return 0;
526}
527
528static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
529 struct mmc *mmc)
530{
531 u32 tmp;
532
533 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
534 if (mmc->ddr_mode)
535 tmp |= TMIO_SD_IF_MODE_DDR;
536 else
537 tmp &= ~TMIO_SD_IF_MODE_DDR;
538 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
539}
540
Marek Vasut8ec6a042018-06-13 08:02:55 +0200541static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
542{
543 return priv->clk_get_rate(priv);
544}
545
Marek Vasuted427da2018-11-15 22:01:33 +0100546static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200547{
548 unsigned int divisor;
Marek Vasuted427da2018-11-15 22:01:33 +0100549 u32 tmp, val = 0;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200550 ulong mclk;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200551
Marek Vasuted427da2018-11-15 22:01:33 +0100552 if (mmc->clock) {
553 mclk = tmio_sd_clk_get_rate(priv);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200554
Marek Vasuted427da2018-11-15 22:01:33 +0100555 divisor = DIV_ROUND_UP(mclk, mmc->clock);
Marek Vasut8ec6a042018-06-13 08:02:55 +0200556
Marek Vasuted427da2018-11-15 22:01:33 +0100557 /* Do not set divider to 0xff in DDR mode */
558 if (mmc->ddr_mode && (divisor == 1))
559 divisor = 2;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200560
Marek Vasuted427da2018-11-15 22:01:33 +0100561 if (divisor <= 1)
562 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
563 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
564 else if (divisor <= 2)
565 val = TMIO_SD_CLKCTL_DIV2;
566 else if (divisor <= 4)
567 val = TMIO_SD_CLKCTL_DIV4;
568 else if (divisor <= 8)
569 val = TMIO_SD_CLKCTL_DIV8;
570 else if (divisor <= 16)
571 val = TMIO_SD_CLKCTL_DIV16;
572 else if (divisor <= 32)
573 val = TMIO_SD_CLKCTL_DIV32;
574 else if (divisor <= 64)
575 val = TMIO_SD_CLKCTL_DIV64;
576 else if (divisor <= 128)
577 val = TMIO_SD_CLKCTL_DIV128;
578 else if (divisor <= 256)
579 val = TMIO_SD_CLKCTL_DIV256;
580 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
581 val = TMIO_SD_CLKCTL_DIV512;
582 else
583 val = TMIO_SD_CLKCTL_DIV1024;
584 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200585
586 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
Marek Vasuted427da2018-11-15 22:01:33 +0100587 if (mmc->clock &&
588 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
589 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
590 /*
591 * Stop the clock before changing its rate
592 * to avoid a glitch signal
593 */
594 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
595 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200596
Marek Vasuted427da2018-11-15 22:01:33 +0100597 /* Change the clock rate. */
598 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
599 tmp |= val;
600 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200601
Marek Vasuted427da2018-11-15 22:01:33 +0100602 /* Enable or Disable the clock */
603 if (mmc->clk_disable) {
Marek Vasut59d529a2018-06-13 08:02:55 +0200604 tmp |= TMIO_SD_CLKCTL_OFFEN;
605 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
Marek Vasuted427da2018-11-15 22:01:33 +0100606 } else {
607 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
608 tmp |= TMIO_SD_CLKCTL_SCLKEN;
Marek Vasut59d529a2018-06-13 08:02:55 +0200609 }
Marek Vasuted427da2018-11-15 22:01:33 +0100610
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200611 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
612
613 udelay(1000);
614}
615
616static void tmio_sd_set_pins(struct udevice *dev)
617{
618 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
619
620#ifdef CONFIG_DM_REGULATOR
621 struct tmio_sd_priv *priv = dev_get_priv(dev);
622
623 if (priv->vqmmc_dev) {
624 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
625 regulator_set_value(priv->vqmmc_dev, 1800000);
626 else
627 regulator_set_value(priv->vqmmc_dev, 3300000);
628 regulator_set_enable(priv->vqmmc_dev, true);
629 }
630#endif
631
632#ifdef CONFIG_PINCTRL
Marek Vasut645a5752018-10-28 13:54:10 +0100633 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200634 pinctrl_select_state(dev, "state_uhs");
Marek Vasut645a5752018-10-28 13:54:10 +0100635 else
636 pinctrl_select_state(dev, "default");
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200637#endif
638}
639
640int tmio_sd_set_ios(struct udevice *dev)
641{
642 struct tmio_sd_priv *priv = dev_get_priv(dev);
643 struct mmc *mmc = mmc_get_mmc_dev(dev);
644 int ret;
645
646 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
647 mmc->clock, mmc->ddr_mode, mmc->bus_width);
648
Marek Vasut8171f992018-06-13 08:02:55 +0200649 tmio_sd_set_clk_rate(priv, mmc);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200650 ret = tmio_sd_set_bus_width(priv, mmc);
651 if (ret)
652 return ret;
653 tmio_sd_set_ddr_mode(priv, mmc);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200654 tmio_sd_set_pins(dev);
655
656 return 0;
657}
658
659int tmio_sd_get_cd(struct udevice *dev)
660{
661 struct tmio_sd_priv *priv = dev_get_priv(dev);
662
663 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
664 return 1;
665
666 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
667 TMIO_SD_INFO1_CD);
668}
669
670static void tmio_sd_host_init(struct tmio_sd_priv *priv)
671{
672 u32 tmp;
673
674 /* soft reset of the host */
675 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
676 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
677 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
678 tmp |= TMIO_SD_SOFT_RST_RSTX;
679 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
680
681 /* FIXME: implement eMMC hw_reset */
682
683 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
684
685 /*
686 * Connected to 32bit AXI.
687 * This register dropped backward compatibility at version 0x10.
688 * Write an appropriate value depending on the IP version.
689 */
Marek Vasut4c80f112019-02-14 15:16:24 +0100690 if (priv->version >= 0x10) {
691 if (priv->caps & TMIO_SD_CAP_64BIT)
Marek Vasut5d688842019-02-19 19:20:14 +0100692 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
Marek Vasut4c80f112019-02-14 15:16:24 +0100693 else
694 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
695 } else {
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200696 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
Marek Vasut4c80f112019-02-14 15:16:24 +0100697 }
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200698
699 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
700 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
701 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
702 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
703 }
704}
705
706int tmio_sd_bind(struct udevice *dev)
707{
708 struct tmio_sd_plat *plat = dev_get_platdata(dev);
709
710 return mmc_bind(dev, &plat->mmc, &plat->cfg);
711}
712
713int tmio_sd_probe(struct udevice *dev, u32 quirks)
714{
715 struct tmio_sd_plat *plat = dev_get_platdata(dev);
716 struct tmio_sd_priv *priv = dev_get_priv(dev);
717 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
718 fdt_addr_t base;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200719 ulong mclk;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200720 int ret;
721
722 base = devfdt_get_addr(dev);
723 if (base == FDT_ADDR_T_NONE)
724 return -EINVAL;
725
726 priv->regbase = devm_ioremap(dev, base, SZ_2K);
727 if (!priv->regbase)
728 return -ENOMEM;
729
730#ifdef CONFIG_DM_REGULATOR
731 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
Marek Vasutc83da2e2018-06-13 08:02:55 +0200732 if (priv->vqmmc_dev)
733 regulator_set_value(priv->vqmmc_dev, 3300000);
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200734#endif
735
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200736 ret = mmc_of_parse(dev, &plat->cfg);
737 if (ret < 0) {
738 dev_err(dev, "failed to parse host caps\n");
739 return ret;
740 }
741
742 plat->cfg.name = dev->name;
743 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
744
745 if (quirks)
746 priv->caps = quirks;
747
748 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
749 TMIO_SD_VERSION_IP;
750 dev_dbg(dev, "version %x\n", priv->version);
751 if (priv->version >= 0x10) {
752 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
753 priv->caps |= TMIO_SD_CAP_DIV1024;
754 }
755
756 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
757 NULL))
758 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
759
760 tmio_sd_host_init(priv);
761
Marek Vasut8ec6a042018-06-13 08:02:55 +0200762 mclk = tmio_sd_clk_get_rate(priv);
763
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200764 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
Marek Vasut8ec6a042018-06-13 08:02:55 +0200765 plat->cfg.f_min = mclk /
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200766 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
Marek Vasut8ec6a042018-06-13 08:02:55 +0200767 plat->cfg.f_max = mclk;
Marek Vasutc453fe32019-03-18 23:43:10 +0100768 if (quirks & TMIO_SD_CAP_16BIT)
769 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
770 else
771 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200772
773 upriv->mmc = &plat->mmc;
774
775 return 0;
776}