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wdenke63c8ee2004-06-09 21:04:48 +00001/*
2 * (C) Copyright 2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
29/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
30 * U-BOOT port on RPXlite board
31 */
32
33/*
34 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
35 * U-BOOT port on RPXlite DW version board--RPXlite_DW
36 * June 8 ,2004
37 */
38
39#ifndef __CONFIG_H
40#define __CONFIG_H
41
42/*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46
47/* #define DEBUG 1 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010048/* #define DEPLOYMENT 1 */
wdenke63c8ee2004-06-09 21:04:48 +000049
50#undef CONFIG_MPC860
51#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
52#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
53
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054#define CONFIG_SYS_TEXT_BASE 0xff000000
55
wdenke63c8ee2004-06-09 21:04:48 +000056#ifdef CONFIG_LCD /* with LCD controller ? */
57#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
58#endif
59
60#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
61#undef CONFIG_8xx_CONS_SMC2
62#undef CONFIG_8xx_CONS_NONE
63#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
64
wdenk6225c5d2005-01-09 23:33:49 +000065#ifdef DEBUG
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010066#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenke63c8ee2004-06-09 21:04:48 +000067#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010068#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
wdenk6225c5d2005-01-09 23:33:49 +000069
70#ifdef DEPLOYMENT
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010071#define CONFIG_BOOT_RETRY_TIME -1
wdenk6225c5d2005-01-09 23:33:49 +000072#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +020073#define CONFIG_AUTOBOOT_PROMPT \
74 "autoboot in %d seconds (stop with 'st')...\n", bootdelay
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010075#define CONFIG_AUTOBOOT_STOP_STR "st"
wdenk6225c5d2005-01-09 23:33:49 +000076#define CONFIG_ZERO_BOOTDELAY_CHECK
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010077#define CONFIG_RESET_TO_RETRY 1
78#define CONFIG_BOOT_RETRY_MIN 1
wdenkc3d2b4b2005-01-22 18:13:04 +000079#endif /* DEPLOYMENT */
80#endif /* DEBUG */
wdenk6225c5d2005-01-09 23:33:49 +000081
82/* pre-boot commands */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010083#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
wdenke63c8ee2004-06-09 21:04:48 +000084
85#undef CONFIG_BOOTARGS
86#define CONFIG_EXTRA_ENV_SETTINGS \
87 "netdev=eth0\0" \
wdenk6225c5d2005-01-09 23:33:49 +000088 "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010089 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenk6225c5d2005-01-09 23:33:49 +000090 "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010091 "addip=setenv bootargs ${bootargs} " \
92 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
93 ":${hostname}:${netdev}:off panic=1\0" \
wdenke63c8ee2004-06-09 21:04:48 +000094 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "bootm ${kernel_addr}\0" \
wdenke63c8ee2004-06-09 21:04:48 +000096 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010097 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
98 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenke63c8ee2004-06-09 21:04:48 +000099 "gatewayip=172.16.115.254\0" \
100 "netmask=255.255.255.0\0" \
wdenk6225c5d2005-01-09 23:33:49 +0000101 "kernel_addr=ff040000\0" \
102 "ramdisk_addr=ff200000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100103 "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
104 "${filesize};md ${kernel_addr};" \
wdenk6225c5d2005-01-09 23:33:49 +0000105 "echo kernel updating finished\0" \
106 "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100107 "${filesize};md ff000000;" \
wdenk6225c5d2005-01-09 23:33:49 +0000108 "echo u-boot updating finished\0" \
109 "eu=protect off 1:6;era 1:6;reset\0" \
110 "lcd=setenv stdout lcd;setenv stdin lcd\0" \
111 "ser=setenv stdout serial;setenv stdin serial\0" \
112 "verify=no"
wdenk082acfd2005-01-10 00:01:04 +0000113
wdenke63c8ee2004-06-09 21:04:48 +0000114#define CONFIG_BOOTCOMMAND "run flash_self"
115
116#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke63c8ee2004-06-09 21:04:48 +0000118#undef CONFIG_WATCHDOG /* watchdog disabled */
119#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
120
Jon Loeliger18225e82007-07-09 21:31:24 -0500121/*
122 * BOOTP options
123 */
124#define CONFIG_BOOTP_SUBNETMASK
125#define CONFIG_BOOTP_GATEWAY
126#define CONFIG_BOOTP_HOSTNAME
127#define CONFIG_BOOTP_BOOTPATH
128#define CONFIG_BOOTP_BOOTFILESIZE
129
wdenke63c8ee2004-06-09 21:04:48 +0000130
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100131#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
132 don't want the advanced function */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100133
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500134
135/*
136 * Command line configuration.
137 */
138#include <config_cmd_default.h>
139
140#define CONFIG_CMD_ASKENV
141#define CONFIG_CMD_JFFS2
142#define CONFIG_CMD_PING
143#define CONFIG_CMD_ELF
144#define CONFIG_CMD_REGINFO
145#define CONFIG_CMD_DHCP
146
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100147#ifdef CONFIG_SPLASH_SCREEN
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500148#define CONFIG_CMD_BMP
149#endif
150
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100151
152/* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
154#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100155
156#define CONFIG_NETCONSOLE
157
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100158#endif /* 1 */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100159
wdenke63c8ee2004-06-09 21:04:48 +0000160/*
161 * Miscellaneous configurable options
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_LONGHELP /* undef to save memory */
164#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */
wdenke63c8ee2004-06-09 21:04:48 +0000165
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500166#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000168#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000170#endif
wdenkc3d2b4b2005-01-22 18:13:04 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
173#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
177#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
178#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke63c8ee2004-06-09 21:04:48 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
181#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke63c8ee2004-06-09 21:04:48 +0000182
183/*
184 * Low Level Configuration Settings
185 * (address mappings, register initial values, etc.)
186 * You should know what you are doing if you make changes here.
187 */
188/*-----------------------------------------------------------------------
189 * Internal Memory Mapped Register
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_IMMR 0xFA200000
wdenke63c8ee2004-06-09 21:04:48 +0000192
193/*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200198#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke63c8ee2004-06-09 21:04:48 +0000200
201/*-----------------------------------------------------------------------
202 * Start addresses for the final memory configuration
203 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke63c8ee2004-06-09 21:04:48 +0000205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenke63c8ee2004-06-09 21:04:48 +0000208
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500209#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenke63c8ee2004-06-09 21:04:48 +0000211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke63c8ee2004-06-09 21:04:48 +0000213#endif
wdenkc3d2b4b2005-01-22 18:13:04 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_BASE 0xFF000000
216#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke63c8ee2004-06-09 21:04:48 +0000217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke63c8ee2004-06-09 21:04:48 +0000224
225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
230#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke63c8ee2004-06-09 21:04:48 +0000232
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200233#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200234#define CONFIG_ENV_ADDR 0xFA000100
235#define CONFIG_ENV_SIZE 0x1000
wdenke63c8ee2004-06-09 21:04:48 +0000236#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200237#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200238#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
239#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200240#endif /* CONFIG_ENV_IS_IN_NVRAM */
wdenke63c8ee2004-06-09 21:04:48 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
wdenk082acfd2005-01-10 00:01:04 +0000243
wdenke63c8ee2004-06-09 21:04:48 +0000244/*-----------------------------------------------------------------------
245 * Cache Configuration
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500248#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke63c8ee2004-06-09 21:04:48 +0000250#endif
251
252/*-----------------------------------------------------------------------
253 * SYPCR - System Protection Control 32-bit 12-35
254 * SYPCR can only be written once after reset!
255 *-----------------------------------------------------------------------
256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
257 */
258#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke63c8ee2004-06-09 21:04:48 +0000260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
261#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke63c8ee2004-06-09 21:04:48 +0000263#endif /* We can get SYPCR: 0xFFFF0689. */
264
265/*-----------------------------------------------------------------------
266 * SIUMCR - SIU Module Configuration 32-bit 12-30
267 *-----------------------------------------------------------------------
268 * PCMCIA config., multi-function pin tri-state
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
wdenke63c8ee2004-06-09 21:04:48 +0000271
272/*---------------------------------------------------------------------
273 * TBSCR - Time Base Status and Control 16-bit 12-16
274 *---------------------------------------------------------------------
275 * Clear Reference Interrupt Status, Timebase freezing enabled
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenke63c8ee2004-06-09 21:04:48 +0000278/* TBSCR: 0x00C3 [SAM] */
279
280/*-----------------------------------------------------------------------
281 * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
282 *-----------------------------------------------------------------------
283 * [RTC enabled but not stopped on FRZ]
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
wdenke63c8ee2004-06-09 21:04:48 +0000286
287/*-----------------------------------------------------------------------
288 * PISCR - Periodic Interrupt Status and Control 16-bit 12-23
289 *-----------------------------------------------------------------------
290 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
291 * [Periodic timer enabled,Periodic timer interrupt disable. ]
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
wdenke63c8ee2004-06-09 21:04:48 +0000294
295/*-----------------------------------------------------------------------
296 * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
297 *-----------------------------------------------------------------------
298 * Reset PLL lock status sticky bit, timer expired status bit and timer
299 * interrupt status bit
300 */
301/* up to 64 MHz we use a 1:2 clock */
302#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
wdenke63c8ee2004-06-09 21:04:48 +0000304#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
wdenke63c8ee2004-06-09 21:04:48 +0000306#endif
307
308/*-----------------------------------------------------------------------
309 * SCCR - System Clock and reset Control Register 5-3
310 *-----------------------------------------------------------------------
311 * Set clock output, timebase and RTC source and divider,
312 * power management and some other internal clocks
313 */
314#define SCCR_MASK SCCR_EBDF00
wdenk30d56fa2004-10-09 22:44:59 +0000315/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
316#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
wdenk6225c5d2005-01-09 23:33:49 +0000318#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
wdenk6225c5d2005-01-09 23:33:49 +0000320#endif
wdenke63c8ee2004-06-09 21:04:48 +0000321
wdenke63c8ee2004-06-09 21:04:48 +0000322/*-----------------------------------------------------------------------
323 * PCMCIA stuff
324 *-----------------------------------------------------------------------
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
327#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
328#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
329#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
330#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
331#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
333#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenke63c8ee2004-06-09 21:04:48 +0000334
335/*-----------------------------------------------------------------------
336 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
337 *-----------------------------------------------------------------------
338 */
339#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
340
341#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
342#undef CONFIG_IDE_LED /* LED for ide not supported */
343#undef CONFIG_IDE_RESET /* reset for ide not supported */
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
346#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenke63c8ee2004-06-09 21:04:48 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
349#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenke63c8ee2004-06-09 21:04:48 +0000350
351/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke63c8ee2004-06-09 21:04:48 +0000353
354/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke63c8ee2004-06-09 21:04:48 +0000356
357/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenke63c8ee2004-06-09 21:04:48 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_DER 0
wdenke63c8ee2004-06-09 21:04:48 +0000361
362/*
363 * Init Memory Controller:
364 *
365 * BR0 and OR0 (FLASH)
366 */
367#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
wdenke63c8ee2004-06-09 21:04:48 +0000369
370/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
372#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
373#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenke63c8ee2004-06-09 21:04:48 +0000374
375/*
376 * BR1 and OR1 (SDRAM)
377 *
378 */
379#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
380#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
381
382/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
384#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
385#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
386#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke63c8ee2004-06-09 21:04:48 +0000387
388/* RPXlite mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
390#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900
391#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
392#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040
wdenke63c8ee2004-06-09 21:04:48 +0000393
394/*
395 * Memory Periodic Timer Prescaler
396 */
397/* periodic timer for refresh */
398#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_MAMR_PTA 32
wdenke63c8ee2004-06-09 21:04:48 +0000400#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_MAMR_PTA 20
wdenke63c8ee2004-06-09 21:04:48 +0000402#endif
403
404/*
405 * Refresh clock Prescalar
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
wdenke63c8ee2004-06-09 21:04:48 +0000408
409/*
410 * MAMR settings for SDRAM
411 */
412
413/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke63c8ee2004-06-09 21:04:48 +0000415 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
wdenke63c8ee2004-06-09 21:04:48 +0000417
wdenke63c8ee2004-06-09 21:04:48 +0000418/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
419/* Configuration variable added by yooth. */
420/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
421/*
422 * BCSRx
423 *
424 * Board Status and Control Registers
425 *
426 */
427#define BCSR0 0xFA400000
428#define BCSR1 0xFA400001
429#define BCSR2 0xFA400002
430#define BCSR3 0xFA400003
431
432#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
433#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
434#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
435#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
436#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
437#define BCSR0_COLTEST 0x20
438#define BCSR0_ETHLPBK 0x40
439#define BCSR0_ETHEN 0x80
440
441#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
442#define BCSR1_PCVCTL6 0x02
443#define BCSR1_PCVCTL5 0x04
444#define BCSR1_PCVCTL4 0x08
445#define BCSR1_IPB5SEL 0x10
446
447#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
448#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
449
450#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
451#define BCSR2_ENBRG1 0x04 /* Added by SAM. */
452
453#define BCSR2_ENPA5HDR 0x08 /* USB Control */
454#define BCSR2_ENUSBCLK 0x10
455#define BCSR2_USBPWREN 0x20
456#define BCSR2_USBSPD 0x40
457#define BCSR2_USBSUSP 0x80
458
459#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
460#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
461#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
462#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
463
464#define BCSR3_D27 0x10 /* Dip Switch settings */
465#define BCSR3_D26 0x20
466#define BCSR3_D25 0x40
467#define BCSR3_D24 0x80
468
469/*
470 * Environment setting
471 */
472#define CONFIG_ETHADDR 00:10:EC:00:37:5B
473#define CONFIG_IPADDR 172.16.115.7
474#define CONFIG_SERVERIP 172.16.115.6
475#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
476#define CONFIG_BOOTFILE uImage.rpxusb
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100477#define CONFIG_HOSTNAME LITE_H1_DW
wdenke63c8ee2004-06-09 21:04:48 +0000478
479#endif /* __CONFIG_H */