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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8572ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* High Level Configuration Options */
31#define CONFIG_BOOKE 1 /* BOOKE */
32#define CONFIG_E500 1 /* BOOKE e500 family */
33#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34#define CONFIG_MPC8572 1
35#define CONFIG_MPC8572DS 1
36#define CONFIG_MP 1 /* support multiple processors */
37#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
38
Kumar Galac51fc5d2009-01-23 14:22:13 -060039#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050040#define CONFIG_PCI 1 /* Enable PCI/PCIE */
41#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
42#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
43#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
44#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
45#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050046#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050047
48#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
49
50#define CONFIG_TSEC_ENET /* tsec ethernet support */
51#define CONFIG_ENV_OVERWRITE
52
53/*
54 * When initializing flash, if we cannot find the manufacturer ID,
55 * assume this is the AMD flash associated with the CDS board.
56 * This allows booting from a promjet.
57 */
58#define CONFIG_ASSUME_AMD_FLASH
59
60#ifndef __ASSEMBLY__
61extern unsigned long get_board_sys_clk(unsigned long dummy);
62extern unsigned long get_board_ddr_clk(unsigned long dummy);
63#endif
64#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
65#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040066#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050067#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
68 from ICS307 instead of switches */
69
70/*
71 * These can be toggled for performance analysis, otherwise use default.
72 */
73#define CONFIG_L2_CACHE /* toggle L2 cache */
74#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050075
76#define CONFIG_ENABLE_36BIT_PHYS 1
77
Kumar Gala18af1c52009-01-23 14:22:14 -060078#ifdef CONFIG_PHYS_64BIT
79#define CONFIG_ADDR_MAP 1
80#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
81#endif
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
84#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -050085#define CONFIG_PANIC_HANG /* do not reset board on panic */
86
87/*
88 * Base addresses -- Note these are effective addresses where the
89 * actual resources get mapped (not physical addresses)
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
92#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -060093#ifdef CONFIG_PHYS_64BIT
94#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
95#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -060097#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Kumar Gala129ba612008-08-12 11:13:08 -050099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
101#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
102#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
Kumar Gala129ba612008-08-12 11:13:08 -0500103
104/* DDR Setup */
Haiying Wangb5f65df2009-01-13 16:29:28 -0500105#define CONFIG_SYS_DDR_TLB_START 9
Kumar Galaf8523cb2009-02-06 09:56:35 -0600106#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -0500107#define CONFIG_FSL_DDR2
108#undef CONFIG_FSL_DDR_INTERACTIVE
109#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
110#define CONFIG_DDR_SPD
111#undef CONFIG_DDR_DLL
112
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800113#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500114#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
117#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500118
119#define CONFIG_NUM_DDR_CONTROLLERS 2
120#define CONFIG_DIMM_SLOTS_PER_CTLR 1
121#define CONFIG_CHIP_SELECTS_PER_CTRL 2
122
123/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500125#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
126#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
127
128/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800129#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
130#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
131#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
132#define CONFIG_SYS_DDR_TIMING_3 0x00020000
133#define CONFIG_SYS_DDR_TIMING_0 0x00260802
134#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
135#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
136#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800138#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800140#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
141#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800143#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
144#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
147#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
148#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500149
150/*
Kumar Gala129ba612008-08-12 11:13:08 -0500151 * Make sure required options are set
152 */
153#ifndef CONFIG_SPD_EEPROM
154#error ("CONFIG_SPD_EEPROM is required")
155#endif
156
157#undef CONFIG_CLOCKS_IN_MHZ
158
159/*
160 * Memory map
161 *
162 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
163 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
164 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
165 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
166 *
167 * Localbus cacheable (TBD)
168 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
169 *
170 * Localbus non-cacheable
171 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
172 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100173 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500174 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
175 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
176 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
177 */
178
179/*
180 * Local Bus Definitions
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600183#ifdef CONFIG_PHYS_64BIT
184#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
185#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600186#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600187#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500188
Kumar Galac953ddf2008-12-02 14:19:34 -0600189#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
190#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500191
Kumar Galac953ddf2008-12-02 14:19:34 -0600192#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
193#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500194
Kumar Gala18af1c52009-01-23 14:22:14 -0600195#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500197#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
200#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
201#undef CONFIG_SYS_FLASH_CHECKSUM
202#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Kumar Gala129ba612008-08-12 11:13:08 -0500206
207#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_CFI
209#define CONFIG_SYS_FLASH_EMPTY_INFO
210#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500211
212#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
213
214#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
215#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600216#ifdef CONFIG_PHYS_64BIT
217#define PIXIS_BASE_PHYS 0xfffdf0000ull
218#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600219#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600220#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500221
Kumar Gala52b565f2008-12-02 14:19:33 -0600222#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500224
225#define PIXIS_ID 0x0 /* Board ID at offset 0 */
226#define PIXIS_VER 0x1 /* Board version at offset 1 */
227#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
228#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
229#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
230#define PIXIS_PWR 0x5 /* PIXIS Power status register */
231#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
232#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
233#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
234#define PIXIS_VCTL 0x10 /* VELA Control Register */
235#define PIXIS_VSTAT 0x11 /* VELA Status Register */
236#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
237#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
238#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
239#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
240#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
241#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
242#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
243#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
244#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
245#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
246#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
247#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
248#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
249#define PIXIS_VWATCH 0x24 /* Watchdog Register */
250#define PIXIS_LED 0x25 /* LED Register */
251
252/* old pixis referenced names */
253#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
254#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800256#define PIXIS_VSPEED2_TSEC1SER 0x8
257#define PIXIS_VSPEED2_TSEC2SER 0x4
258#define PIXIS_VSPEED2_TSEC3SER 0x2
259#define PIXIS_VSPEED2_TSEC4SER 0x1
260#define PIXIS_VCFGEN1_TSEC1SER 0x20
261#define PIXIS_VCFGEN1_TSEC2SER 0x20
262#define PIXIS_VCFGEN1_TSEC3SER 0x20
263#define PIXIS_VCFGEN1_TSEC4SER 0x20
264#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
265 | PIXIS_VSPEED2_TSEC2SER \
266 | PIXIS_VSPEED2_TSEC3SER \
267 | PIXIS_VSPEED2_TSEC4SER)
268#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
269 | PIXIS_VCFGEN1_TSEC2SER \
270 | PIXIS_VCFGEN1_TSEC3SER \
271 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_INIT_RAM_LOCK 1
274#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
275#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
278#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
279#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
282#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500283
Haiying Wangc013b742008-10-29 13:32:59 -0400284#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600285#ifdef CONFIG_PHYS_64BIT
286#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
287#else
Haiying Wangc013b742008-10-29 13:32:59 -0400288#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600289#endif
Haiying Wangc013b742008-10-29 13:32:59 -0400290#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
291 CONFIG_SYS_NAND_BASE + 0x40000, \
292 CONFIG_SYS_NAND_BASE + 0x80000,\
293 CONFIG_SYS_NAND_BASE + 0xC0000}
294#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wangc013b742008-10-29 13:32:59 -0400295#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100296#define CONFIG_CMD_NAND 1
297#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400298#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
299
300/* NAND flash config */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600301#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
303 | BR_PS_8 /* Port Size = 8 bit */ \
304 | BR_MS_FCM /* MSEL = FCM */ \
305 | BR_V) /* valid */
306#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
307 | OR_FCM_PGS /* Large Page*/ \
308 | OR_FCM_CSCT \
309 | OR_FCM_CST \
310 | OR_FCM_CHT \
311 | OR_FCM_SCY_1 \
312 | OR_FCM_TRLX \
313 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400314
315#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
316#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
317
Kumar Gala72a9414a2009-01-23 14:22:12 -0600318#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100319 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
320 | BR_PS_8 /* Port Size = 8 bit */ \
321 | BR_MS_FCM /* MSEL = FCM */ \
322 | BR_V) /* valid */
323#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600324#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
326 | BR_PS_8 /* Port Size = 8 bit */ \
327 | BR_MS_FCM /* MSEL = FCM */ \
328 | BR_V) /* valid */
329#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400330
Kumar Gala72a9414a2009-01-23 14:22:12 -0600331#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100332 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
333 | BR_PS_8 /* Port Size = 8 bit */ \
334 | BR_MS_FCM /* MSEL = FCM */ \
335 | BR_V) /* valid */
336#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400337
338
Kumar Gala129ba612008-08-12 11:13:08 -0500339/* Serial Port - controlled on board with jumper J8
340 * open - index 2
341 * shorted - index 1
342 */
343#define CONFIG_CONS_INDEX 1
344#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_NS16550
346#define CONFIG_SYS_NS16550_SERIAL
347#define CONFIG_SYS_NS16550_REG_SIZE 1
348#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala129ba612008-08-12 11:13:08 -0500349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
354#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500355
356/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_HUSH_PARSER
358#ifdef CONFIG_SYS_HUSH_PARSER
359#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala129ba612008-08-12 11:13:08 -0500360#endif
361
362/*
363 * Pass open firmware flat tree
364 */
365#define CONFIG_OF_LIBFDT 1
366#define CONFIG_OF_BOARD_SETUP 1
367#define CONFIG_OF_STDOUT_VIA_ALIAS 1
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_64BIT_VSPRINTF 1
370#define CONFIG_SYS_64BIT_STRTOUL 1
Kumar Gala129ba612008-08-12 11:13:08 -0500371
372/* new uImage format support */
373#define CONFIG_FIT 1
374#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
375
376/* I2C */
377#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
378#define CONFIG_HARD_I2C /* I2C with hardware support */
379#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wang1f3ba312008-10-03 11:46:59 -0400380#define CONFIG_I2C_MULTI_BUS
381#define CONFIG_I2C_CMD_TREE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
383#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
384#define CONFIG_SYS_I2C_SLAVE 0x7F
385#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
386#define CONFIG_SYS_I2C_OFFSET 0x3000
387#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala129ba612008-08-12 11:13:08 -0500388
389/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400390 * I2C2 EEPROM
391 */
392#define CONFIG_ID_EEPROM
393#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400395#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
397#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
398#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400399
400/*
Kumar Gala129ba612008-08-12 11:13:08 -0500401 * General PCI
402 * Memory space is mapped 1-1, but I/O space must start from 0.
403 */
404
Kumar Gala129ba612008-08-12 11:13:08 -0500405/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600406#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600407#ifdef CONFIG_PHYS_64BIT
Kumar Galaad97dce2009-02-09 22:03:05 -0600408#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600409#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
410#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600411#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600412#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600413#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600415#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600416#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600417#ifdef CONFIG_PHYS_64BIT
418#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
419#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600421#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500423
424/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600425#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600426#ifdef CONFIG_PHYS_64BIT
Kumar Galaad97dce2009-02-09 22:03:05 -0600427#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600428#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
429#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600430#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600431#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600432#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600434#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600435#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600436#ifdef CONFIG_PHYS_64BIT
437#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
438#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600440#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500442
443/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600444#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600445#ifdef CONFIG_PHYS_64BIT
Kumar Galaad97dce2009-02-09 22:03:05 -0600446#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600447#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
448#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600449#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600450#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600451#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600453#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600454#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
457#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600459#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500461
462#if defined(CONFIG_PCI)
463
464/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600465#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500466
467/* video */
468#define CONFIG_VIDEO
469
470#if defined(CONFIG_VIDEO)
471#define CONFIG_BIOSEMU
472#define CONFIG_CFB_CONSOLE
473#define CONFIG_VIDEO_SW_CURSOR
474#define CONFIG_VGA_AS_SINGLE_DEVICE
475#define CONFIG_ATI_RADEON_FB
476#define CONFIG_VIDEO_LOGO
477/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500479#endif
480
481#define CONFIG_NET_MULTI
482#define CONFIG_PCI_PNP /* do pci plug-and-play */
483
484#undef CONFIG_EEPRO100
485#undef CONFIG_TULIP
486#undef CONFIG_RTL8139
487
488#ifdef CONFIG_RTL8139
489/* This macro is used by RTL8139 but not defined in PPC architecture */
490#define KSEG1ADDR(x) (x)
491#define _IO_BASE 0x00000000
492#endif
493
494#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600495 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
496 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500497 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
498#endif
499
500#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
501#define CONFIG_DOS_PARTITION
502#define CONFIG_SCSI_AHCI
503
504#ifdef CONFIG_SCSI_AHCI
505#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
507#define CONFIG_SYS_SCSI_MAX_LUN 1
508#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
509#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500510#endif /* SCSI */
511
512#endif /* CONFIG_PCI */
513
514
515#if defined(CONFIG_TSEC_ENET)
516
517#ifndef CONFIG_NET_MULTI
518#define CONFIG_NET_MULTI 1
519#endif
520
521#define CONFIG_MII 1 /* MII PHY management */
522#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
523#define CONFIG_TSEC1 1
524#define CONFIG_TSEC1_NAME "eTSEC1"
525#define CONFIG_TSEC2 1
526#define CONFIG_TSEC2_NAME "eTSEC2"
527#define CONFIG_TSEC3 1
528#define CONFIG_TSEC3_NAME "eTSEC3"
529#define CONFIG_TSEC4 1
530#define CONFIG_TSEC4_NAME "eTSEC4"
531
Liu Yu7e183ca2008-10-10 11:40:59 +0800532#define CONFIG_PIXIS_SGMII_CMD
533#define CONFIG_FSL_SGMII_RISER 1
534#define SGMII_RISER_PHY_OFFSET 0x1c
535
536#ifdef CONFIG_FSL_SGMII_RISER
537#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
538#endif
539
Kumar Gala129ba612008-08-12 11:13:08 -0500540#define TSEC1_PHY_ADDR 0
541#define TSEC2_PHY_ADDR 1
542#define TSEC3_PHY_ADDR 2
543#define TSEC4_PHY_ADDR 3
544
545#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
546#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
547#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
548#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
549
550#define TSEC1_PHYIDX 0
551#define TSEC2_PHYIDX 0
552#define TSEC3_PHYIDX 0
553#define TSEC4_PHYIDX 0
554
555#define CONFIG_ETHPRIME "eTSEC1"
556
557#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
558#endif /* CONFIG_TSEC_ENET */
559
560/*
561 * Environment
562 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200563#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200565#define CONFIG_ENV_ADDR 0xfff80000
Kumar Gala129ba612008-08-12 11:13:08 -0500566#else
Haiying Wang6fc110b2008-10-31 05:06:14 -0500567#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Kumar Gala129ba612008-08-12 11:13:08 -0500568#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200569#define CONFIG_ENV_SIZE 0x2000
570#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Kumar Gala129ba612008-08-12 11:13:08 -0500571
572#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500574
575/*
576 * Command line configuration.
577 */
578#include <config_cmd_default.h>
579
580#define CONFIG_CMD_IRQ
581#define CONFIG_CMD_PING
582#define CONFIG_CMD_I2C
583#define CONFIG_CMD_MII
584#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500585#define CONFIG_CMD_IRQ
586#define CONFIG_CMD_SETEXPR
Kumar Gala129ba612008-08-12 11:13:08 -0500587
588#if defined(CONFIG_PCI)
589#define CONFIG_CMD_PCI
590#define CONFIG_CMD_BEDBUG
591#define CONFIG_CMD_NET
592#define CONFIG_CMD_SCSI
593#define CONFIG_CMD_EXT2
594#endif
595
596#undef CONFIG_WATCHDOG /* watchdog disabled */
597
598/*
599 * Miscellaneous configurable options
600 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala129ba612008-08-12 11:13:08 -0500602#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
604#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala129ba612008-08-12 11:13:08 -0500605#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500607#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500609#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200610#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
611#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
612#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
613#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala129ba612008-08-12 11:13:08 -0500614
615/*
616 * For booting Linux, the board info and command line data
617 * have to be in the first 8 MB of memory, since this is
618 * the maximum mapped by the Linux kernel during initialization.
619 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Kumar Gala129ba612008-08-12 11:13:08 -0500621
622/*
623 * Internal Definitions
624 *
625 * Boot Flags
626 */
627#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
628#define BOOTFLAG_WARM 0x02 /* Software reboot */
629
630#if defined(CONFIG_CMD_KGDB)
631#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
632#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
633#endif
634
635/*
636 * Environment Configuration
637 */
638
639/* The mac addresses for all ethernet interface */
640#if defined(CONFIG_TSEC_ENET)
641#define CONFIG_HAS_ETH0
642#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
643#define CONFIG_HAS_ETH1
644#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
645#define CONFIG_HAS_ETH2
646#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
647#define CONFIG_HAS_ETH3
648#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
649#endif
650
651#define CONFIG_IPADDR 192.168.1.254
652
653#define CONFIG_HOSTNAME unknown
654#define CONFIG_ROOTPATH /opt/nfsroot
655#define CONFIG_BOOTFILE uImage
656#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
657
658#define CONFIG_SERVERIP 192.168.1.1
659#define CONFIG_GATEWAYIP 192.168.1.1
660#define CONFIG_NETMASK 255.255.255.0
661
662/* default location for tftp and bootm */
663#define CONFIG_LOADADDR 1000000
664
665#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
666#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
667
668#define CONFIG_BAUDRATE 115200
669
670#define CONFIG_EXTRA_ENV_SETTINGS \
Haiying Wang4ca06602008-10-03 12:37:41 -0400671 "memctl_intlv_ctl=2\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500672 "netdev=eth0\0" \
673 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
674 "tftpflash=tftpboot $loadaddr $uboot; " \
675 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
676 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
677 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
678 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
679 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
680 "consoledev=ttyS0\0" \
681 "ramdiskaddr=2000000\0" \
682 "ramdiskfile=8572ds/ramdisk.uboot\0" \
683 "fdtaddr=c00000\0" \
684 "fdtfile=8572ds/mpc8572ds.dtb\0" \
685 "bdev=sda3\0"
686
687#define CONFIG_HDBOOT \
688 "setenv bootargs root=/dev/$bdev rw " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "tftp $loadaddr $bootfile;" \
691 "tftp $fdtaddr $fdtfile;" \
692 "bootm $loadaddr - $fdtaddr"
693
694#define CONFIG_NFSBOOTCOMMAND \
695 "setenv bootargs root=/dev/nfs rw " \
696 "nfsroot=$serverip:$rootpath " \
697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr - $fdtaddr"
702
703#define CONFIG_RAMBOOTCOMMAND \
704 "setenv bootargs root=/dev/ram rw " \
705 "console=$consoledev,$baudrate $othbootargs;" \
706 "tftp $ramdiskaddr $ramdiskfile;" \
707 "tftp $loadaddr $bootfile;" \
708 "tftp $fdtaddr $fdtfile;" \
709 "bootm $loadaddr $ramdiskaddr $fdtaddr"
710
711#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
712
713#endif /* __CONFIG_H */