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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020040#define CONFIG_SYS_SMC_RXBUFLEN 128
41#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000042#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
43
wdenkae3af052003-08-07 22:18:11 +000044#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000045
wdenkae3af052003-08-07 22:18:11 +000046#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000047
48#define CONFIG_BOARD_TYPES 1 /* support board types */
49
50#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010051 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000052 "echo"
53
54#undef CONFIG_BOOTARGS
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "netdev=eth0\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000060 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000064 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000066 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000069 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020070 "hostname=TQM855M\0" \
71 "bootfile=TQM855M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020072 "fdt_addr=40080000\0" \
73 "kernel_addr=400A0000\0" \
74 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020075 "u-boot=TQM855M/u-image.bin\0" \
76 "load=tftp 200000 ${u-boot}\0" \
77 "update=prot off 40000000 +${filesize};" \
78 "era 40000000 +${filesize};" \
79 "cp.b 200000 40000000 ${filesize};" \
80 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000081 ""
82#define CONFIG_BOOTCOMMAND "run flash_self"
83
84#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000086
87#undef CONFIG_WATCHDOG /* watchdog disabled */
88
89#define CONFIG_STATUS_LED 1 /* Status LED enabled */
90
91#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
92
wdenkd4ca31c2004-01-02 14:00:00 +000093/* enable I2C and select the hardware/software driver */
94#undef CONFIG_HARD_I2C /* I2C with hardware support */
95#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
98#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000099
100#ifdef CONFIG_SOFT_I2C
101/*
102 * Software (bit-bang) I2C driver configuration
103 */
104#define PB_SCL 0x00000020 /* PB 26 */
105#define PB_SDA 0x00000010 /* PB 27 */
106
107#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
108#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
109#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
110#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
111#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
112 else immr->im_cpm.cp_pbdat &= ~PB_SDA
113#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
114 else immr->im_cpm.cp_pbdat &= ~PB_SCL
115#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
116#endif /* CONFIG_SOFT_I2C */
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
119#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000120#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
122#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
123#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenkd4ca31c2004-01-02 14:00:00 +0000124#endif
125
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500126/*
127 * BOOTP options
128 */
129#define CONFIG_BOOTP_SUBNETMASK
130#define CONFIG_BOOTP_GATEWAY
131#define CONFIG_BOOTP_HOSTNAME
132#define CONFIG_BOOTP_BOOTPATH
133#define CONFIG_BOOTP_BOOTFILESIZE
134
wdenkf12e5682003-07-07 20:07:54 +0000135
136#define CONFIG_MAC_PARTITION
137#define CONFIG_DOS_PARTITION
138
139#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
140
wdenkf12e5682003-07-07 20:07:54 +0000141
Jon Loeliger26946902007-07-04 22:30:50 -0500142/*
143 * Command line configuration.
144 */
145#include <config_cmd_default.h>
146
147#define CONFIG_CMD_ASKENV
148#define CONFIG_CMD_DATE
149#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200150#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100151#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500152#define CONFIG_CMD_EEPROM
153#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200154#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500155#define CONFIG_CMD_NFS
156#define CONFIG_CMD_SNTP
157
wdenkf12e5682003-07-07 20:07:54 +0000158
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200159#define CONFIG_NETCONSOLE
160
161
wdenkf12e5682003-07-07 20:07:54 +0000162/*
163 * Miscellaneous configurable options
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LONGHELP /* undef to save memory */
166#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf12e5682003-07-07 20:07:54 +0000167
Wolfgang Denk2751a952006-10-28 02:29:14 +0200168#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
170#ifdef CONFIG_SYS_HUSH_PARSER
171#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkf12e5682003-07-07 20:07:54 +0000172#endif
173
Jon Loeliger26946902007-07-04 22:30:50 -0500174#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000176#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000178#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
180#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
181#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
184#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf12e5682003-07-07 20:07:54 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf12e5682003-07-07 20:07:54 +0000191
192/*
193 * Low Level Configuration Settings
194 * (address mappings, register initial values, etc.)
195 * You should know what you are doing if you make changes here.
196 */
197/*-----------------------------------------------------------------------
198 * Internal Memory Mapped Register
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000201
202/*-----------------------------------------------------------------------
203 * Definitions for initial stack pointer and data area (in DPRAM)
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
206#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
207#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
208#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
209#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000210
211/*-----------------------------------------------------------------------
212 * Start addresses for the final memory configuration
213 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_SDRAM_BASE 0x00000000
217#define CONFIG_SYS_FLASH_BASE 0x40000000
218#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
220#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000221
222/*
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000228
229/*-----------------------------------------------------------------------
230 * FLASH organization
231 */
wdenkf12e5682003-07-07 20:07:54 +0000232
Martin Krausee318d9e2007-09-27 11:10:08 +0200233/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200235#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
237#define CONFIG_SYS_FLASH_EMPTY_INFO
238#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
239#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
240#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000241
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200242#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200243#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
244#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
245#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000246
247/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200248#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
249#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200252
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200253#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
254
wdenkf12e5682003-07-07 20:07:54 +0000255/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200256 * Dynamic MTD partition support
257 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100258#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200259#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
260#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200261#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
262
263#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
264 "128k(dtb)," \
265 "1920k(kernel)," \
266 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200267 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200268
269/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000270 * Hardware Information Block
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
273#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
274#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000275
276/*-----------------------------------------------------------------------
277 * Cache Configuration
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500280#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000282#endif
283
284/*-----------------------------------------------------------------------
285 * SYPCR - System Protection Control 11-9
286 * SYPCR can only be written once after reset!
287 *-----------------------------------------------------------------------
288 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
289 */
290#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000292 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
293#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000295#endif
296
297/*-----------------------------------------------------------------------
298 * SIUMCR - SIU Module Configuration 11-6
299 *-----------------------------------------------------------------------
300 * PCMCIA config., multi-function pin tri-state
301 */
302#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000304#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000306#endif /* CONFIG_CAN_DRIVER */
307
308/*-----------------------------------------------------------------------
309 * TBSCR - Time Base Status and Control 11-26
310 *-----------------------------------------------------------------------
311 * Clear Reference Interrupt Status, Timebase freezing enabled
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000314
315/*-----------------------------------------------------------------------
316 * RTCSC - Real-Time Clock Status and Control Register 11-27
317 *-----------------------------------------------------------------------
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000320
321/*-----------------------------------------------------------------------
322 * PISCR - Periodic Interrupt Status and Control 11-31
323 *-----------------------------------------------------------------------
324 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000327
328/*-----------------------------------------------------------------------
329 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
330 *-----------------------------------------------------------------------
331 * Reset PLL lock status sticky bit, timer expired status bit and timer
332 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000335
336/*-----------------------------------------------------------------------
337 * SCCR - System Clock and reset Control Register 15-27
338 *-----------------------------------------------------------------------
339 * Set clock output, timebase and RTC source and divider,
340 * power management and some other internal clocks
341 */
342#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000344 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
345 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000346
347/*-----------------------------------------------------------------------
348 * PCMCIA stuff
349 *-----------------------------------------------------------------------
350 *
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
353#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
354#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
355#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
356#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
357#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
358#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
359#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000360
361/*-----------------------------------------------------------------------
362 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
363 *-----------------------------------------------------------------------
364 */
365
366#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
367
368#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
369#undef CONFIG_IDE_LED /* LED for ide not supported */
370#undef CONFIG_IDE_RESET /* reset for ide not supported */
371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
373#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000378
379/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000381
382/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000384
385/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000387
388/*-----------------------------------------------------------------------
389 *
390 *-----------------------------------------------------------------------
391 *
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000394
395/*
396 * Init Memory Controller:
397 *
398 * BR0/1 and OR0/1 (FLASH)
399 */
400
401#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
402#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
403
404/* used to re-map FLASH both when starting from SRAM or FLASH:
405 * restrict access enough to keep SRAM working (if any)
406 * but not too much to meddle with FLASH accesses
407 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
409#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000410
411/*
412 * FLASH timing:
413 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000415 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
418#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
419#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
422#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
423#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000424
425/*
426 * BR2/3 and OR2/3 (SDRAM)
427 *
428 */
429#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
430#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
431#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
432
433/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000435
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
437#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000438
439#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
441#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000442#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
444#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
445#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
446#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000447 BR_PS_8 | BR_MS_UPMB | BR_V )
448#endif /* CONFIG_CAN_DRIVER */
449
450/*
451 * Memory Periodic Timer Prescaler
452 *
453 * The Divider for PTA (refresh timer) configuration is based on an
454 * example SDRAM configuration (64 MBit, one bank). The adjustment to
455 * the number of chip selects (NCS) and the actually needed refresh
456 * rate is done by setting MPTPR.
457 *
458 * PTA is calculated from
459 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
460 *
461 * gclk CPU clock (not bus clock!)
462 * Trefresh Refresh cycle * 4 (four word bursts used)
463 *
464 * 4096 Rows from SDRAM example configuration
465 * 1000 factor s -> ms
466 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
467 * 4 Number of refresh cycles per period
468 * 64 Refresh cycle in ms per number of rows
469 * --------------------------------------------
470 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
471 *
472 * 50 MHz => 50.000.000 / Divider = 98
473 * 66 Mhz => 66.000.000 / Divider = 129
474 * 80 Mhz => 80.000.000 / Divider = 156
475 */
wdenke9132ea2004-04-24 23:23:30 +0000476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
478#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000479
480/*
481 * For 16 MBit, refresh rates could be 31.3 us
482 * (= 64 ms / 2K = 125 / quad bursts).
483 * For a simpler initialization, 15.6 us is used instead.
484 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
486 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000487 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
489#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000490
491/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
493#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000494
495/*
496 * MAMR settings for SDRAM
497 */
498
499/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000501 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
502 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
503/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000505 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
506 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
507
508
509/*
510 * Internal Definitions
511 *
512 * Boot Flags
513 */
514#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
515#define BOOTFLAG_WARM 0x02 /* Software reboot */
516
517#define CONFIG_SCC1_ENET
518#define CONFIG_FEC_ENET
519#define CONFIG_ETHPRIME "SCC ETHERNET"
520
521#endif /* __CONFIG_H */