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Stefan Roese99d4c6d2016-02-10 07:22:10 +01001/*
2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Marcin Wojtas <mw@semihalf.com>
7 *
8 * U-Boot version:
Stefan Roesec9607c92017-02-24 10:12:41 +01009 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010010 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <common.h>
17#include <dm.h>
18#include <dm/device-internal.h>
19#include <dm/lists.h>
20#include <net.h>
21#include <netdev.h>
22#include <config.h>
23#include <malloc.h>
24#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090025#include <linux/errno.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010026#include <phy.h>
27#include <miiphy.h>
28#include <watchdog.h>
29#include <asm/arch/cpu.h>
30#include <asm/arch/soc.h>
31#include <linux/compat.h>
32#include <linux/mbus.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36/* Some linux -> U-Boot compatibility stuff */
37#define netdev_err(dev, fmt, args...) \
38 printf(fmt, ##args)
39#define netdev_warn(dev, fmt, args...) \
40 printf(fmt, ##args)
41#define netdev_info(dev, fmt, args...) \
42 printf(fmt, ##args)
43#define netdev_dbg(dev, fmt, args...) \
44 printf(fmt, ##args)
45
46#define ETH_ALEN 6 /* Octets in one ethernet addr */
47
48#define __verify_pcpu_ptr(ptr) \
49do { \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
51 (void)__vpp_verify; \
52} while (0)
53
54#define VERIFY_PERCPU_PTR(__p) \
55({ \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
58})
59
60#define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61#define smp_processor_id() 0
62#define num_present_cpus() 1
63#define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
65
66#define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
67
68#define CONFIG_NR_CPUS 1
69#define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
70
71/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72#define WRAP (2 + ETH_HLEN + 4 + 32)
73#define MTU 1500
74#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
75
76#define MVPP2_SMI_TIMEOUT 10000
77
78/* RX Fifo Registers */
79#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82#define MVPP2_RX_FIFO_INIT_REG 0x64
83
84/* RX DMA Top Registers */
85#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89#define MVPP2_POOL_BUF_SIZE_OFFSET 5
90#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93#define MVPP2_RXQ_POOL_SHORT_OFFS 20
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +010094#define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
Stefan Roese99d4c6d2016-02-10 07:22:10 +010096#define MVPP2_RXQ_POOL_LONG_OFFS 24
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +010097#define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
Stefan Roese99d4c6d2016-02-10 07:22:10 +010099#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101#define MVPP2_RXQ_DISABLE_MASK BIT(31)
102
103/* Parser Registers */
104#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105#define MVPP2_PRS_PORT_LU_MAX 0xf
106#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114#define MVPP2_PRS_TCAM_IDX_REG 0x1100
115#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117#define MVPP2_PRS_SRAM_IDX_REG 0x1200
118#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119#define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
121
122/* Classifier Registers */
123#define MVPP2_CLS_MODE_REG 0x1800
124#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125#define MVPP2_CLS_PORT_WAY_REG 0x1810
126#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127#define MVPP2_CLS_LKP_INDEX_REG 0x1814
128#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129#define MVPP2_CLS_LKP_TBL_REG 0x1818
130#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132#define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133#define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135#define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
142
143/* Descriptor Manager Top Registers */
144#define MVPP2_RXQ_NUM_REG 0x2040
145#define MVPP2_RXQ_DESC_ADDR_REG 0x2044
Thomas Petazzoni80350f52017-02-20 11:36:57 +0100146#define MVPP22_DESC_ADDR_OFFS 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100147#define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151#define MVPP2_RXQ_NUM_NEW_OFFSET 16
152#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156#define MVPP2_RXQ_THRESH_REG 0x204c
157#define MVPP2_OCCUPIED_THRESH_OFFSET 0
158#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159#define MVPP2_RXQ_INDEX_REG 0x2050
160#define MVPP2_TXQ_NUM_REG 0x2080
161#define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162#define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165#define MVPP2_TXQ_THRESH_REG 0x2094
166#define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167#define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168#define MVPP2_TXQ_INDEX_REG 0x2098
169#define MVPP2_TXQ_PREF_BUF_REG 0x209c
170#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175#define MVPP2_TXQ_PENDING_REG 0x20a0
176#define MVPP2_TXQ_PENDING_MASK 0x3fff
177#define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179#define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186#define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
Thomas Petazzoni80350f52017-02-20 11:36:57 +0100188#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100189#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
194
195/* MBUS bridge registers */
196#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199#define MVPP2_BASE_ADDR_ENABLE 0x4060
200
Thomas Petazzonicdf77792017-02-16 08:41:07 +0100201/* AXI Bridge Registers */
202#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
214
215/* Values for AXI Bridge registers */
216#define MVPP22_AXI_ATTR_CACHE_OFFS 0
217#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
218
219#define MVPP22_AXI_CODE_CACHE_OFFS 0
220#define MVPP22_AXI_CODE_DOMAIN_OFFS 4
221
222#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
225
226#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
228
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100229/* Interrupt Cause and Mask registers */
230#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
Thomas Petazzonibc0bbf42017-02-16 08:46:37 +0100231#define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
232
233#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
237
238#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
240
241#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
245
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100246#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
264
265/* Buffer Manager registers */
266#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269#define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279#define MVPP2_BM_START_MASK BIT(0)
280#define MVPP2_BM_STOP_MASK BIT(1)
281#define MVPP2_BM_STATE_MASK BIT(4)
282#define MVPP2_BM_LOW_THRESH_OFFS 8
283#define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286#define MVPP2_BM_HIGH_THRESH_OFFS 16
287#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299#define MVPP2_BM_VIRT_ALLOC_REG 0x6440
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100300#define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301#define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302#define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303#define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100304#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308#define MVPP2_BM_VIRT_RLS_REG 0x64c0
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100309#define MVPP21_BM_MC_RLS_REG 0x64c4
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100310#define MVPP2_BM_MC_ID_MASK 0xfff
311#define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100312#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316#define MVPP22_BM_MC_RLS_REG 0x64d4
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100317
318/* TX Scheduler registers */
319#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325#define MVPP2_TXP_SCHED_MTU_REG 0x801c
326#define MVPP2_TXP_MTU_MAX 0x7FFFF
327#define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
341
342/* TX general registers */
343#define MVPP2_TX_SNOOP_REG 0x8800
344#define MVPP2_TX_PORT_FLUSH_REG 0x8810
345#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
346
347/* LMS registers */
348#define MVPP2_SRC_ADDR_MIDDLE 0x24
349#define MVPP2_SRC_ADDR_HIGH 0x28
350#define MVPP2_PHY_AN_CFG0_REG 0x34
351#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100352#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
Thomas Petazzoni6b28f422017-02-15 12:16:23 +0100353#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100354
355/* Per-port registers */
356#define MVPP2_GMAC_CTRL_0_REG 0x0
357#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100358#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100359#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
360#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
361#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
362#define MVPP2_GMAC_CTRL_1_REG 0x4
363#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
364#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
365#define MVPP2_GMAC_PCS_LB_EN_BIT 6
366#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
367#define MVPP2_GMAC_SA_LOW_OFFS 7
368#define MVPP2_GMAC_CTRL_2_REG 0x8
369#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100370#define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100371#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
372#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100373#define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100374#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100375#define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100376#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
377#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
378#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100379#define MVPP2_GMAC_EN_PCS_AN BIT(2)
380#define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100381#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
382#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
383#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
384#define MVPP2_GMAC_FC_ADV_EN BIT(9)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100385#define MVPP2_GMAC_EN_FC_AN BIT(11)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100386#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
387#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100388#define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100389#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
390#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
391#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
392#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
393 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100394#define MVPP2_GMAC_CTRL_4_REG 0x90
395#define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
396#define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
397#define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
398#define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100399
Stefan Roese31aa1e32017-03-22 15:07:30 +0100400/*
401 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
402 * relative to port->base.
403 */
404
405/* Port Mac Control0 */
406#define MVPP22_XLG_CTRL0_REG 0x100
407#define MVPP22_XLG_PORT_EN BIT(0)
408#define MVPP22_XLG_MAC_RESETN BIT(1)
409#define MVPP22_XLG_RX_FC_EN BIT(7)
410#define MVPP22_XLG_MIBCNT_DIS BIT(13)
411/* Port Mac Control1 */
412#define MVPP22_XLG_CTRL1_REG 0x104
413#define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
414#define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
415/* Port Interrupt Mask */
416#define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
417#define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
418/* Port Mac Control3 */
419#define MVPP22_XLG_CTRL3_REG 0x11c
420#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
421#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
422#define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
423/* Port Mac Control4 */
424#define MVPP22_XLG_CTRL4_REG 0x184
425#define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
426#define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
427#define MVPP22_XLG_MODE_DMA_1G BIT(12)
428#define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
429
430/* XPCS registers */
431
432/* Global Configuration 0 */
433#define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
434#define MVPP22_XPCS_PCSRESET BIT(0)
435#define MVPP22_XPCS_PCSMODE_OFFS 3
436#define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
437 MVPP22_XPCS_PCSMODE_OFFS)
438#define MVPP22_XPCS_LANEACTIVE_OFFS 5
439#define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
440 MVPP22_XPCS_LANEACTIVE_OFFS)
441
442/* MPCS registers */
443
444#define PCS40G_COMMON_CONTROL 0x14
Stefan Chulskie09d0c82017-04-06 15:39:08 +0200445#define FORWARD_ERROR_CORRECTION_MASK BIT(10)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100446
447#define PCS_CLOCK_RESET 0x14c
448#define TX_SD_CLK_RESET_MASK BIT(0)
449#define RX_SD_CLK_RESET_MASK BIT(1)
450#define MAC_CLK_RESET_MASK BIT(2)
451#define CLK_DIVISION_RATIO_OFFS 4
452#define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
453#define CLK_DIV_PHASE_SET_MASK BIT(11)
454
455/* System Soft Reset 1 */
456#define GOP_SOFT_RESET_1_REG 0x108
457#define NETC_GOP_SOFT_RESET_OFFS 6
458#define NETC_GOP_SOFT_RESET_MASK (0x1 << \
459 NETC_GOP_SOFT_RESET_OFFS)
460
461/* Ports Control 0 */
462#define NETCOMP_PORTS_CONTROL_0_REG 0x110
463#define NETC_BUS_WIDTH_SELECT_OFFS 1
464#define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
465 NETC_BUS_WIDTH_SELECT_OFFS)
466#define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
467#define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
468 NETC_GIG_RX_DATA_SAMPLE_OFFS)
469#define NETC_CLK_DIV_PHASE_OFFS 31
470#define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
471/* Ports Control 1 */
472#define NETCOMP_PORTS_CONTROL_1_REG 0x114
473#define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
474#define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
475 NETC_PORTS_ACTIVE_OFFSET(p))
476#define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
477#define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
478 NETC_PORT_GIG_RF_RESET_OFFS(p))
479#define NETCOMP_CONTROL_0_REG 0x120
480#define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
481#define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
482 NETC_GBE_PORT0_SGMII_MODE_OFFS)
483#define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
484#define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
485 NETC_GBE_PORT1_SGMII_MODE_OFFS)
486#define NETC_GBE_PORT1_MII_MODE_OFFS 2
487#define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
488 NETC_GBE_PORT1_MII_MODE_OFFS)
489
490#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +0100491#define MVPP22_SMI_POLLING_EN BIT(10)
492
Stefan Roese31aa1e32017-03-22 15:07:30 +0100493#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
494 (0x4 * (port)))
Thomas Petazzoni26a52782017-02-16 08:03:37 +0100495
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100496#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
497
498/* Descriptor ring Macros */
499#define MVPP2_QUEUE_NEXT_DESC(q, index) \
500 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
501
502/* SMI: 0xc0054 -> offset 0x54 to lms_base */
Stefan Roese0a61e9a2017-02-16 08:31:32 +0100503#define MVPP21_SMI 0x0054
504/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
505#define MVPP22_SMI 0x1200
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100506#define MVPP2_PHY_REG_MASK 0x1f
507/* SMI register fields */
508#define MVPP2_SMI_DATA_OFFS 0 /* Data */
509#define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
510#define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
511#define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
512#define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
513#define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
514#define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
515#define MVPP2_SMI_BUSY (1 << 28) /* Busy */
516
517#define MVPP2_PHY_ADDR_MASK 0x1f
518#define MVPP2_PHY_REG_MASK 0x1f
519
Stefan Roese31aa1e32017-03-22 15:07:30 +0100520/* Additional PPv2.2 offsets */
521#define MVPP22_MPCS 0x007000
522#define MVPP22_XPCS 0x007400
523#define MVPP22_PORT_BASE 0x007e00
524#define MVPP22_PORT_OFFSET 0x001000
525#define MVPP22_RFU1 0x318000
526
527/* Maximum number of ports */
528#define MVPP22_GOP_MAC_NUM 4
529
530/* Sets the field located at the specified in data */
531#define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
532#define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
533#define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
534
535/* Net Complex */
536enum mv_netc_topology {
537 MV_NETC_GE_MAC2_SGMII = BIT(0),
538 MV_NETC_GE_MAC3_SGMII = BIT(1),
539 MV_NETC_GE_MAC3_RGMII = BIT(2),
540};
541
542enum mv_netc_phase {
543 MV_NETC_FIRST_PHASE,
544 MV_NETC_SECOND_PHASE,
545};
546
547enum mv_netc_sgmii_xmi_mode {
548 MV_NETC_GBE_SGMII,
549 MV_NETC_GBE_XMII,
550};
551
552enum mv_netc_mii_mode {
553 MV_NETC_GBE_RGMII,
554 MV_NETC_GBE_MII,
555};
556
557enum mv_netc_lanes {
558 MV_NETC_LANE_23,
559 MV_NETC_LANE_45,
560};
561
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100562/* Various constants */
563
564/* Coalescing */
565#define MVPP2_TXDONE_COAL_PKTS_THRESH 15
566#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
567#define MVPP2_RX_COAL_PKTS 32
568#define MVPP2_RX_COAL_USEC 100
569
570/* The two bytes Marvell header. Either contains a special value used
571 * by Marvell switches when a specific hardware mode is enabled (not
572 * supported by this driver) or is filled automatically by zeroes on
573 * the RX side. Those two bytes being at the front of the Ethernet
574 * header, they allow to have the IP header aligned on a 4 bytes
575 * boundary automatically: the hardware skips those two bytes on its
576 * own.
577 */
578#define MVPP2_MH_SIZE 2
579#define MVPP2_ETH_TYPE_LEN 2
580#define MVPP2_PPPOE_HDR_SIZE 8
581#define MVPP2_VLAN_TAG_LEN 4
582
583/* Lbtd 802.3 type */
584#define MVPP2_IP_LBDT_TYPE 0xfffa
585
586#define MVPP2_CPU_D_CACHE_LINE_SIZE 32
587#define MVPP2_TX_CSUM_MAX_SIZE 9800
588
589/* Timeout constants */
590#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
591#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
592
593#define MVPP2_TX_MTU_MAX 0x7ffff
594
595/* Maximum number of T-CONTs of PON port */
596#define MVPP2_MAX_TCONT 16
597
598/* Maximum number of supported ports */
599#define MVPP2_MAX_PORTS 4
600
601/* Maximum number of TXQs used by single port */
602#define MVPP2_MAX_TXQ 8
603
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100604/* Default number of TXQs in use */
605#define MVPP2_DEFAULT_TXQ 1
606
607/* Dfault number of RXQs in use */
608#define MVPP2_DEFAULT_RXQ 1
609#define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
610
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100611/* Max number of Rx descriptors */
612#define MVPP2_MAX_RXD 16
613
614/* Max number of Tx descriptors */
615#define MVPP2_MAX_TXD 16
616
617/* Amount of Tx descriptors that can be reserved at once by CPU */
618#define MVPP2_CPU_DESC_CHUNK 64
619
620/* Max number of Tx descriptors in each aggregated queue */
621#define MVPP2_AGGR_TXQ_SIZE 256
622
623/* Descriptor aligned size */
624#define MVPP2_DESC_ALIGNED_SIZE 32
625
626/* Descriptor alignment mask */
627#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
628
629/* RX FIFO constants */
Stefan Roeseff572c62017-03-01 13:09:42 +0100630#define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
631#define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
632#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
633#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
634#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
635#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
636#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
637#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
638#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
639
640/* TX general registers */
641#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
642#define MVPP22_TX_FIFO_SIZE_MASK 0xf
643
644/* TX FIFO constants */
645#define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
646#define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100647
648/* RX buffer constants */
649#define MVPP2_SKB_SHINFO_SIZE \
650 0
651
652#define MVPP2_RX_PKT_SIZE(mtu) \
653 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
654 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
655
656#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
657#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
658#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
659 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
660
661#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
662
663/* IPv6 max L3 address size */
664#define MVPP2_MAX_L3_ADDR_SIZE 16
665
666/* Port flags */
667#define MVPP2_F_LOOPBACK BIT(0)
668
669/* Marvell tag types */
670enum mvpp2_tag_type {
671 MVPP2_TAG_TYPE_NONE = 0,
672 MVPP2_TAG_TYPE_MH = 1,
673 MVPP2_TAG_TYPE_DSA = 2,
674 MVPP2_TAG_TYPE_EDSA = 3,
675 MVPP2_TAG_TYPE_VLAN = 4,
676 MVPP2_TAG_TYPE_LAST = 5
677};
678
679/* Parser constants */
680#define MVPP2_PRS_TCAM_SRAM_SIZE 256
681#define MVPP2_PRS_TCAM_WORDS 6
682#define MVPP2_PRS_SRAM_WORDS 4
683#define MVPP2_PRS_FLOW_ID_SIZE 64
684#define MVPP2_PRS_FLOW_ID_MASK 0x3f
685#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
686#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
687#define MVPP2_PRS_IPV4_HEAD 0x40
688#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
689#define MVPP2_PRS_IPV4_MC 0xe0
690#define MVPP2_PRS_IPV4_MC_MASK 0xf0
691#define MVPP2_PRS_IPV4_BC_MASK 0xff
692#define MVPP2_PRS_IPV4_IHL 0x5
693#define MVPP2_PRS_IPV4_IHL_MASK 0xf
694#define MVPP2_PRS_IPV6_MC 0xff
695#define MVPP2_PRS_IPV6_MC_MASK 0xff
696#define MVPP2_PRS_IPV6_HOP_MASK 0xff
697#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
698#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
699#define MVPP2_PRS_DBL_VLANS_MAX 100
700
701/* Tcam structure:
702 * - lookup ID - 4 bits
703 * - port ID - 1 byte
704 * - additional information - 1 byte
705 * - header data - 8 bytes
706 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
707 */
708#define MVPP2_PRS_AI_BITS 8
709#define MVPP2_PRS_PORT_MASK 0xff
710#define MVPP2_PRS_LU_MASK 0xf
711#define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
712 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
713#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
714 (((offs) * 2) - ((offs) % 2) + 2)
715#define MVPP2_PRS_TCAM_AI_BYTE 16
716#define MVPP2_PRS_TCAM_PORT_BYTE 17
717#define MVPP2_PRS_TCAM_LU_BYTE 20
718#define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
719#define MVPP2_PRS_TCAM_INV_WORD 5
720/* Tcam entries ID */
721#define MVPP2_PE_DROP_ALL 0
722#define MVPP2_PE_FIRST_FREE_TID 1
723#define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
724#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
725#define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
726#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
727#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
728#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
729#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
730#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
731#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
732#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
733#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
734#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
735#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
736#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
737#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
738#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
739#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
740#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
741#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
742#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
743#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
744#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
745#define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
746#define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
747#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
748
749/* Sram structure
750 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
751 */
752#define MVPP2_PRS_SRAM_RI_OFFS 0
753#define MVPP2_PRS_SRAM_RI_WORD 0
754#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
755#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
756#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
757#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
758#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
759#define MVPP2_PRS_SRAM_UDF_OFFS 73
760#define MVPP2_PRS_SRAM_UDF_BITS 8
761#define MVPP2_PRS_SRAM_UDF_MASK 0xff
762#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
763#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
764#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
765#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
766#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
767#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
768#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
769#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
770#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
771#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
772#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
773#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
774#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
775#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
776#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
777#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
778#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
779#define MVPP2_PRS_SRAM_AI_OFFS 90
780#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
781#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
782#define MVPP2_PRS_SRAM_AI_MASK 0xff
783#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
784#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
785#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
786#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
787
788/* Sram result info bits assignment */
789#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
790#define MVPP2_PRS_RI_DSA_MASK 0x2
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100791#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
792#define MVPP2_PRS_RI_VLAN_NONE 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100793#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
794#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
795#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
796#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
797#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100798#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
799#define MVPP2_PRS_RI_L2_UCAST 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100800#define MVPP2_PRS_RI_L2_MCAST BIT(9)
801#define MVPP2_PRS_RI_L2_BCAST BIT(10)
802#define MVPP2_PRS_RI_PPPOE_MASK 0x800
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100803#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
804#define MVPP2_PRS_RI_L3_UN 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100805#define MVPP2_PRS_RI_L3_IP4 BIT(12)
806#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
807#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
808#define MVPP2_PRS_RI_L3_IP6 BIT(14)
809#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
810#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100811#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
812#define MVPP2_PRS_RI_L3_UCAST 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100813#define MVPP2_PRS_RI_L3_MCAST BIT(15)
814#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
815#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
816#define MVPP2_PRS_RI_UDF3_MASK 0x300000
817#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
818#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
819#define MVPP2_PRS_RI_L4_TCP BIT(22)
820#define MVPP2_PRS_RI_L4_UDP BIT(23)
821#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
822#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
823#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
824#define MVPP2_PRS_RI_DROP_MASK 0x80000000
825
826/* Sram additional info bits assignment */
827#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
828#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
829#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
830#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
831#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
832#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
833#define MVPP2_PRS_SINGLE_VLAN_AI 0
834#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
835
836/* DSA/EDSA type */
837#define MVPP2_PRS_TAGGED true
838#define MVPP2_PRS_UNTAGGED false
839#define MVPP2_PRS_EDSA true
840#define MVPP2_PRS_DSA false
841
842/* MAC entries, shadow udf */
843enum mvpp2_prs_udf {
844 MVPP2_PRS_UDF_MAC_DEF,
845 MVPP2_PRS_UDF_MAC_RANGE,
846 MVPP2_PRS_UDF_L2_DEF,
847 MVPP2_PRS_UDF_L2_DEF_COPY,
848 MVPP2_PRS_UDF_L2_USER,
849};
850
851/* Lookup ID */
852enum mvpp2_prs_lookup {
853 MVPP2_PRS_LU_MH,
854 MVPP2_PRS_LU_MAC,
855 MVPP2_PRS_LU_DSA,
856 MVPP2_PRS_LU_VLAN,
857 MVPP2_PRS_LU_L2,
858 MVPP2_PRS_LU_PPPOE,
859 MVPP2_PRS_LU_IP4,
860 MVPP2_PRS_LU_IP6,
861 MVPP2_PRS_LU_FLOWS,
862 MVPP2_PRS_LU_LAST,
863};
864
865/* L3 cast enum */
866enum mvpp2_prs_l3_cast {
867 MVPP2_PRS_L3_UNI_CAST,
868 MVPP2_PRS_L3_MULTI_CAST,
869 MVPP2_PRS_L3_BROAD_CAST
870};
871
872/* Classifier constants */
873#define MVPP2_CLS_FLOWS_TBL_SIZE 512
874#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
875#define MVPP2_CLS_LKP_TBL_SIZE 64
876
877/* BM constants */
878#define MVPP2_BM_POOLS_NUM 1
879#define MVPP2_BM_LONG_BUF_NUM 16
880#define MVPP2_BM_SHORT_BUF_NUM 16
881#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
882#define MVPP2_BM_POOL_PTR_ALIGN 128
883#define MVPP2_BM_SWF_LONG_POOL(port) 0
884
885/* BM cookie (32 bits) definition */
886#define MVPP2_BM_COOKIE_POOL_OFFS 8
887#define MVPP2_BM_COOKIE_CPU_OFFS 24
888
889/* BM short pool packet size
890 * These value assure that for SWF the total number
891 * of bytes allocated for each buffer will be 512
892 */
893#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
894
895enum mvpp2_bm_type {
896 MVPP2_BM_FREE,
897 MVPP2_BM_SWF_LONG,
898 MVPP2_BM_SWF_SHORT
899};
900
901/* Definitions */
902
903/* Shared Packet Processor resources */
904struct mvpp2 {
905 /* Shared registers' base addresses */
906 void __iomem *base;
907 void __iomem *lms_base;
Thomas Petazzoni26a52782017-02-16 08:03:37 +0100908 void __iomem *iface_base;
Stefan Roese0a61e9a2017-02-16 08:31:32 +0100909 void __iomem *mdio_base;
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100910
Stefan Roese31aa1e32017-03-22 15:07:30 +0100911 void __iomem *mpcs_base;
912 void __iomem *xpcs_base;
913 void __iomem *rfu1_base;
914
915 u32 netc_config;
916
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100917 /* List of pointers to port structures */
918 struct mvpp2_port **port_list;
919
920 /* Aggregated TXQs */
921 struct mvpp2_tx_queue *aggr_txqs;
922
923 /* BM pools */
924 struct mvpp2_bm_pool *bm_pools;
925
926 /* PRS shadow table */
927 struct mvpp2_prs_shadow *prs_shadow;
928 /* PRS auxiliary table for double vlan entries control */
929 bool *prs_double_vlans;
930
931 /* Tclk value */
932 u32 tclk;
933
Thomas Petazzoni16a98982017-02-15 14:08:59 +0100934 /* HW version */
935 enum { MVPP21, MVPP22 } hw_version;
936
Thomas Petazzoni09b3f942017-02-16 09:03:16 +0100937 /* Maximum number of RXQs per port */
938 unsigned int max_port_rxqs;
939
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100940 struct mii_dev *bus;
Stefan Roese1fabbd02017-02-16 15:26:06 +0100941
942 int probe_done;
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100943};
944
945struct mvpp2_pcpu_stats {
946 u64 rx_packets;
947 u64 rx_bytes;
948 u64 tx_packets;
949 u64 tx_bytes;
950};
951
952struct mvpp2_port {
953 u8 id;
954
Thomas Petazzoni26a52782017-02-16 08:03:37 +0100955 /* Index of the port from the "group of ports" complex point
956 * of view
957 */
958 int gop_id;
959
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100960 int irq;
961
962 struct mvpp2 *priv;
963
964 /* Per-port registers' base address */
965 void __iomem *base;
966
967 struct mvpp2_rx_queue **rxqs;
968 struct mvpp2_tx_queue **txqs;
969
970 int pkt_size;
971
972 u32 pending_cause_rx;
973
974 /* Per-CPU port control */
975 struct mvpp2_port_pcpu __percpu *pcpu;
976
977 /* Flags */
978 unsigned long flags;
979
980 u16 tx_ring_size;
981 u16 rx_ring_size;
982 struct mvpp2_pcpu_stats __percpu *stats;
983
984 struct phy_device *phy_dev;
985 phy_interface_t phy_interface;
986 int phy_node;
987 int phyaddr;
988 int init;
989 unsigned int link;
990 unsigned int duplex;
991 unsigned int speed;
992
Stefan Roese9acb7da2017-03-22 14:15:40 +0100993 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
994
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100995 struct mvpp2_bm_pool *pool_long;
996 struct mvpp2_bm_pool *pool_short;
997
998 /* Index of first port's physical RXQ */
999 u8 first_rxq;
1000
1001 u8 dev_addr[ETH_ALEN];
1002};
1003
1004/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
1005 * layout of the transmit and reception DMA descriptors, and their
1006 * layout is therefore defined by the hardware design
1007 */
1008
1009#define MVPP2_TXD_L3_OFF_SHIFT 0
1010#define MVPP2_TXD_IP_HLEN_SHIFT 8
1011#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
1012#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
1013#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
1014#define MVPP2_TXD_PADDING_DISABLE BIT(23)
1015#define MVPP2_TXD_L4_UDP BIT(24)
1016#define MVPP2_TXD_L3_IP6 BIT(26)
1017#define MVPP2_TXD_L_DESC BIT(28)
1018#define MVPP2_TXD_F_DESC BIT(29)
1019
1020#define MVPP2_RXD_ERR_SUMMARY BIT(15)
1021#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1022#define MVPP2_RXD_ERR_CRC 0x0
1023#define MVPP2_RXD_ERR_OVERRUN BIT(13)
1024#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1025#define MVPP2_RXD_BM_POOL_ID_OFFS 16
1026#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1027#define MVPP2_RXD_HWF_SYNC BIT(21)
1028#define MVPP2_RXD_L4_CSUM_OK BIT(22)
1029#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1030#define MVPP2_RXD_L4_TCP BIT(25)
1031#define MVPP2_RXD_L4_UDP BIT(26)
1032#define MVPP2_RXD_L3_IP4 BIT(28)
1033#define MVPP2_RXD_L3_IP6 BIT(30)
1034#define MVPP2_RXD_BUF_HDR BIT(31)
1035
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001036/* HW TX descriptor for PPv2.1 */
1037struct mvpp21_tx_desc {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001038 u32 command; /* Options used by HW for packet transmitting.*/
1039 u8 packet_offset; /* the offset from the buffer beginning */
1040 u8 phys_txq; /* destination queue ID */
1041 u16 data_size; /* data size of transmitted packet in bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001042 u32 buf_dma_addr; /* physical addr of transmitted buffer */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001043 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1044 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1045 u32 reserved2; /* reserved (for future use) */
1046};
1047
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001048/* HW RX descriptor for PPv2.1 */
1049struct mvpp21_rx_desc {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001050 u32 status; /* info about received packet */
1051 u16 reserved1; /* parser_info (for future use, PnC) */
1052 u16 data_size; /* size of received packet in bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001053 u32 buf_dma_addr; /* physical address of the buffer */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001054 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1055 u16 reserved2; /* gem_port_id (for future use, PON) */
1056 u16 reserved3; /* csum_l4 (for future use, PnC) */
1057 u8 reserved4; /* bm_qset (for future use, BM) */
1058 u8 reserved5;
1059 u16 reserved6; /* classify_info (for future use, PnC) */
1060 u32 reserved7; /* flow_id (for future use, PnC) */
1061 u32 reserved8;
1062};
1063
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001064/* HW TX descriptor for PPv2.2 */
1065struct mvpp22_tx_desc {
1066 u32 command;
1067 u8 packet_offset;
1068 u8 phys_txq;
1069 u16 data_size;
1070 u64 reserved1;
1071 u64 buf_dma_addr_ptp;
1072 u64 buf_cookie_misc;
1073};
1074
1075/* HW RX descriptor for PPv2.2 */
1076struct mvpp22_rx_desc {
1077 u32 status;
1078 u16 reserved1;
1079 u16 data_size;
1080 u32 reserved2;
1081 u32 reserved3;
1082 u64 buf_dma_addr_key_hash;
1083 u64 buf_cookie_misc;
1084};
1085
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001086/* Opaque type used by the driver to manipulate the HW TX and RX
1087 * descriptors
1088 */
1089struct mvpp2_tx_desc {
1090 union {
1091 struct mvpp21_tx_desc pp21;
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001092 struct mvpp22_tx_desc pp22;
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001093 };
1094};
1095
1096struct mvpp2_rx_desc {
1097 union {
1098 struct mvpp21_rx_desc pp21;
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001099 struct mvpp22_rx_desc pp22;
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001100 };
1101};
1102
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001103/* Per-CPU Tx queue control */
1104struct mvpp2_txq_pcpu {
1105 int cpu;
1106
1107 /* Number of Tx DMA descriptors in the descriptor ring */
1108 int size;
1109
1110 /* Number of currently used Tx DMA descriptor in the
1111 * descriptor ring
1112 */
1113 int count;
1114
1115 /* Number of Tx DMA descriptors reserved for each CPU */
1116 int reserved_num;
1117
1118 /* Index of last TX DMA descriptor that was inserted */
1119 int txq_put_index;
1120
1121 /* Index of the TX DMA descriptor to be cleaned up */
1122 int txq_get_index;
1123};
1124
1125struct mvpp2_tx_queue {
1126 /* Physical number of this Tx queue */
1127 u8 id;
1128
1129 /* Logical number of this Tx queue */
1130 u8 log_id;
1131
1132 /* Number of Tx DMA descriptors in the descriptor ring */
1133 int size;
1134
1135 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1136 int count;
1137
1138 /* Per-CPU control of physical Tx queues */
1139 struct mvpp2_txq_pcpu __percpu *pcpu;
1140
1141 u32 done_pkts_coal;
1142
1143 /* Virtual address of thex Tx DMA descriptors array */
1144 struct mvpp2_tx_desc *descs;
1145
1146 /* DMA address of the Tx DMA descriptors array */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001147 dma_addr_t descs_dma;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001148
1149 /* Index of the last Tx DMA descriptor */
1150 int last_desc;
1151
1152 /* Index of the next Tx DMA descriptor to process */
1153 int next_desc_to_proc;
1154};
1155
1156struct mvpp2_rx_queue {
1157 /* RX queue number, in the range 0-31 for physical RXQs */
1158 u8 id;
1159
1160 /* Num of rx descriptors in the rx descriptor ring */
1161 int size;
1162
1163 u32 pkts_coal;
1164 u32 time_coal;
1165
1166 /* Virtual address of the RX DMA descriptors array */
1167 struct mvpp2_rx_desc *descs;
1168
1169 /* DMA address of the RX DMA descriptors array */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001170 dma_addr_t descs_dma;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001171
1172 /* Index of the last RX DMA descriptor */
1173 int last_desc;
1174
1175 /* Index of the next RX DMA descriptor to process */
1176 int next_desc_to_proc;
1177
1178 /* ID of port to which physical RXQ is mapped */
1179 int port;
1180
1181 /* Port's logic RXQ number to which physical RXQ is mapped */
1182 int logic_rxq;
1183};
1184
1185union mvpp2_prs_tcam_entry {
1186 u32 word[MVPP2_PRS_TCAM_WORDS];
1187 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1188};
1189
1190union mvpp2_prs_sram_entry {
1191 u32 word[MVPP2_PRS_SRAM_WORDS];
1192 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1193};
1194
1195struct mvpp2_prs_entry {
1196 u32 index;
1197 union mvpp2_prs_tcam_entry tcam;
1198 union mvpp2_prs_sram_entry sram;
1199};
1200
1201struct mvpp2_prs_shadow {
1202 bool valid;
1203 bool finish;
1204
1205 /* Lookup ID */
1206 int lu;
1207
1208 /* User defined offset */
1209 int udf;
1210
1211 /* Result info */
1212 u32 ri;
1213 u32 ri_mask;
1214};
1215
1216struct mvpp2_cls_flow_entry {
1217 u32 index;
1218 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1219};
1220
1221struct mvpp2_cls_lookup_entry {
1222 u32 lkpid;
1223 u32 way;
1224 u32 data;
1225};
1226
1227struct mvpp2_bm_pool {
1228 /* Pool number in the range 0-7 */
1229 int id;
1230 enum mvpp2_bm_type type;
1231
1232 /* Buffer Pointers Pool External (BPPE) size */
1233 int size;
1234 /* Number of buffers for this pool */
1235 int buf_num;
1236 /* Pool buffer size */
1237 int buf_size;
1238 /* Packet size */
1239 int pkt_size;
1240
1241 /* BPPE virtual base address */
Stefan Roesea7c28ff2017-02-15 12:46:18 +01001242 unsigned long *virt_addr;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001243 /* BPPE DMA base address */
1244 dma_addr_t dma_addr;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001245
1246 /* Ports using BM pool */
1247 u32 port_map;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001248};
1249
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001250/* Static declaractions */
1251
1252/* Number of RXQs used by single port */
1253static int rxq_number = MVPP2_DEFAULT_RXQ;
1254/* Number of TXQs used by single port */
1255static int txq_number = MVPP2_DEFAULT_TXQ;
1256
Stefan Roesec9607c92017-02-24 10:12:41 +01001257static int base_id;
1258
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001259#define MVPP2_DRIVER_NAME "mvpp2"
1260#define MVPP2_DRIVER_VERSION "1.0"
1261
1262/*
1263 * U-Boot internal data, mostly uncached buffers for descriptors and data
1264 */
1265struct buffer_location {
1266 struct mvpp2_tx_desc *aggr_tx_descs;
1267 struct mvpp2_tx_desc *tx_descs;
1268 struct mvpp2_rx_desc *rx_descs;
Stefan Roesea7c28ff2017-02-15 12:46:18 +01001269 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1270 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001271 int first_rxq;
1272};
1273
1274/*
1275 * All 4 interfaces use the same global buffer, since only one interface
1276 * can be enabled at once
1277 */
1278static struct buffer_location buffer_loc;
1279
1280/*
1281 * Page table entries are set to 1MB, or multiples of 1MB
1282 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1283 */
1284#define BD_SPACE (1 << 20)
1285
1286/* Utility/helper methods */
1287
1288static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1289{
1290 writel(data, priv->base + offset);
1291}
1292
1293static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1294{
1295 return readl(priv->base + offset);
1296}
1297
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001298static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1299 struct mvpp2_tx_desc *tx_desc,
1300 dma_addr_t dma_addr)
1301{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001302 if (port->priv->hw_version == MVPP21) {
1303 tx_desc->pp21.buf_dma_addr = dma_addr;
1304 } else {
1305 u64 val = (u64)dma_addr;
1306
1307 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1308 tx_desc->pp22.buf_dma_addr_ptp |= val;
1309 }
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001310}
1311
1312static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1313 struct mvpp2_tx_desc *tx_desc,
1314 size_t size)
1315{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001316 if (port->priv->hw_version == MVPP21)
1317 tx_desc->pp21.data_size = size;
1318 else
1319 tx_desc->pp22.data_size = size;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001320}
1321
1322static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1323 struct mvpp2_tx_desc *tx_desc,
1324 unsigned int txq)
1325{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001326 if (port->priv->hw_version == MVPP21)
1327 tx_desc->pp21.phys_txq = txq;
1328 else
1329 tx_desc->pp22.phys_txq = txq;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001330}
1331
1332static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1333 struct mvpp2_tx_desc *tx_desc,
1334 unsigned int command)
1335{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001336 if (port->priv->hw_version == MVPP21)
1337 tx_desc->pp21.command = command;
1338 else
1339 tx_desc->pp22.command = command;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001340}
1341
1342static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1343 struct mvpp2_tx_desc *tx_desc,
1344 unsigned int offset)
1345{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001346 if (port->priv->hw_version == MVPP21)
1347 tx_desc->pp21.packet_offset = offset;
1348 else
1349 tx_desc->pp22.packet_offset = offset;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001350}
1351
1352static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1353 struct mvpp2_rx_desc *rx_desc)
1354{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001355 if (port->priv->hw_version == MVPP21)
1356 return rx_desc->pp21.buf_dma_addr;
1357 else
1358 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001359}
1360
1361static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1362 struct mvpp2_rx_desc *rx_desc)
1363{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001364 if (port->priv->hw_version == MVPP21)
1365 return rx_desc->pp21.buf_cookie;
1366 else
1367 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001368}
1369
1370static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1371 struct mvpp2_rx_desc *rx_desc)
1372{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001373 if (port->priv->hw_version == MVPP21)
1374 return rx_desc->pp21.data_size;
1375 else
1376 return rx_desc->pp22.data_size;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001377}
1378
1379static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1380 struct mvpp2_rx_desc *rx_desc)
1381{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001382 if (port->priv->hw_version == MVPP21)
1383 return rx_desc->pp21.status;
1384 else
1385 return rx_desc->pp22.status;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001386}
1387
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001388static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1389{
1390 txq_pcpu->txq_get_index++;
1391 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1392 txq_pcpu->txq_get_index = 0;
1393}
1394
1395/* Get number of physical egress port */
1396static inline int mvpp2_egress_port(struct mvpp2_port *port)
1397{
1398 return MVPP2_MAX_TCONT + port->id;
1399}
1400
1401/* Get number of physical TXQ */
1402static inline int mvpp2_txq_phys(int port, int txq)
1403{
1404 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1405}
1406
1407/* Parser configuration routines */
1408
1409/* Update parser tcam and sram hw entries */
1410static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1411{
1412 int i;
1413
1414 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1415 return -EINVAL;
1416
1417 /* Clear entry invalidation bit */
1418 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1419
1420 /* Write tcam index - indirect access */
1421 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1422 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1423 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1424
1425 /* Write sram index - indirect access */
1426 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1427 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1428 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1429
1430 return 0;
1431}
1432
1433/* Read tcam entry from hw */
1434static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1435{
1436 int i;
1437
1438 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1439 return -EINVAL;
1440
1441 /* Write tcam index - indirect access */
1442 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1443
1444 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1445 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1446 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1447 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1448
1449 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1450 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1451
1452 /* Write sram index - indirect access */
1453 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1454 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1455 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1456
1457 return 0;
1458}
1459
1460/* Invalidate tcam hw entry */
1461static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1462{
1463 /* Write index - indirect access */
1464 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1465 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1466 MVPP2_PRS_TCAM_INV_MASK);
1467}
1468
1469/* Enable shadow table entry and set its lookup ID */
1470static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1471{
1472 priv->prs_shadow[index].valid = true;
1473 priv->prs_shadow[index].lu = lu;
1474}
1475
1476/* Update ri fields in shadow table entry */
1477static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1478 unsigned int ri, unsigned int ri_mask)
1479{
1480 priv->prs_shadow[index].ri_mask = ri_mask;
1481 priv->prs_shadow[index].ri = ri;
1482}
1483
1484/* Update lookup field in tcam sw entry */
1485static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1486{
1487 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1488
1489 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1490 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1491}
1492
1493/* Update mask for single port in tcam sw entry */
1494static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1495 unsigned int port, bool add)
1496{
1497 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1498
1499 if (add)
1500 pe->tcam.byte[enable_off] &= ~(1 << port);
1501 else
1502 pe->tcam.byte[enable_off] |= 1 << port;
1503}
1504
1505/* Update port map in tcam sw entry */
1506static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1507 unsigned int ports)
1508{
1509 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1510 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1511
1512 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1513 pe->tcam.byte[enable_off] &= ~port_mask;
1514 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1515}
1516
1517/* Obtain port map from tcam sw entry */
1518static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1519{
1520 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1521
1522 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1523}
1524
1525/* Set byte of data and its enable bits in tcam sw entry */
1526static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1527 unsigned int offs, unsigned char byte,
1528 unsigned char enable)
1529{
1530 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1531 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1532}
1533
1534/* Get byte of data and its enable bits from tcam sw entry */
1535static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1536 unsigned int offs, unsigned char *byte,
1537 unsigned char *enable)
1538{
1539 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1540 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1541}
1542
1543/* Set ethertype in tcam sw entry */
1544static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1545 unsigned short ethertype)
1546{
1547 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1548 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1549}
1550
1551/* Set bits in sram sw entry */
1552static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1553 int val)
1554{
1555 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1556}
1557
1558/* Clear bits in sram sw entry */
1559static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1560 int val)
1561{
1562 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1563}
1564
1565/* Update ri bits in sram sw entry */
1566static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1567 unsigned int bits, unsigned int mask)
1568{
1569 unsigned int i;
1570
1571 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1572 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1573
1574 if (!(mask & BIT(i)))
1575 continue;
1576
1577 if (bits & BIT(i))
1578 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1579 else
1580 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1581
1582 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1583 }
1584}
1585
1586/* Update ai bits in sram sw entry */
1587static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1588 unsigned int bits, unsigned int mask)
1589{
1590 unsigned int i;
1591 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1592
1593 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1594
1595 if (!(mask & BIT(i)))
1596 continue;
1597
1598 if (bits & BIT(i))
1599 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1600 else
1601 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1602
1603 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1604 }
1605}
1606
1607/* Read ai bits from sram sw entry */
1608static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1609{
1610 u8 bits;
1611 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1612 int ai_en_off = ai_off + 1;
1613 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1614
1615 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1616 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1617
1618 return bits;
1619}
1620
1621/* In sram sw entry set lookup ID field of the tcam key to be used in the next
1622 * lookup interation
1623 */
1624static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1625 unsigned int lu)
1626{
1627 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1628
1629 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1630 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1631 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1632}
1633
1634/* In the sram sw entry set sign and value of the next lookup offset
1635 * and the offset value generated to the classifier
1636 */
1637static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1638 unsigned int op)
1639{
1640 /* Set sign */
1641 if (shift < 0) {
1642 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1643 shift = 0 - shift;
1644 } else {
1645 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1646 }
1647
1648 /* Set value */
1649 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1650 (unsigned char)shift;
1651
1652 /* Reset and set operation */
1653 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1654 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1655 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1656
1657 /* Set base offset as current */
1658 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1659}
1660
1661/* In the sram sw entry set sign and value of the user defined offset
1662 * generated to the classifier
1663 */
1664static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1665 unsigned int type, int offset,
1666 unsigned int op)
1667{
1668 /* Set sign */
1669 if (offset < 0) {
1670 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1671 offset = 0 - offset;
1672 } else {
1673 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1674 }
1675
1676 /* Set value */
1677 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1678 MVPP2_PRS_SRAM_UDF_MASK);
1679 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1680 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1681 MVPP2_PRS_SRAM_UDF_BITS)] &=
1682 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1683 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1684 MVPP2_PRS_SRAM_UDF_BITS)] |=
1685 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1686
1687 /* Set offset type */
1688 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1689 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1690 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1691
1692 /* Set offset operation */
1693 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1694 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1695 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1696
1697 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1698 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1699 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1700 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1701
1702 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1703 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1704 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1705
1706 /* Set base offset as current */
1707 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1708}
1709
1710/* Find parser flow entry */
1711static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1712{
1713 struct mvpp2_prs_entry *pe;
1714 int tid;
1715
1716 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1717 if (!pe)
1718 return NULL;
1719 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1720
1721 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1722 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1723 u8 bits;
1724
1725 if (!priv->prs_shadow[tid].valid ||
1726 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1727 continue;
1728
1729 pe->index = tid;
1730 mvpp2_prs_hw_read(priv, pe);
1731 bits = mvpp2_prs_sram_ai_get(pe);
1732
1733 /* Sram store classification lookup ID in AI bits [5:0] */
1734 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1735 return pe;
1736 }
1737 kfree(pe);
1738
1739 return NULL;
1740}
1741
1742/* Return first free tcam index, seeking from start to end */
1743static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1744 unsigned char end)
1745{
1746 int tid;
1747
1748 if (start > end)
1749 swap(start, end);
1750
1751 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1752 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1753
1754 for (tid = start; tid <= end; tid++) {
1755 if (!priv->prs_shadow[tid].valid)
1756 return tid;
1757 }
1758
1759 return -EINVAL;
1760}
1761
1762/* Enable/disable dropping all mac da's */
1763static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1764{
1765 struct mvpp2_prs_entry pe;
1766
1767 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1768 /* Entry exist - update port only */
1769 pe.index = MVPP2_PE_DROP_ALL;
1770 mvpp2_prs_hw_read(priv, &pe);
1771 } else {
1772 /* Entry doesn't exist - create new */
1773 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1774 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1775 pe.index = MVPP2_PE_DROP_ALL;
1776
1777 /* Non-promiscuous mode for all ports - DROP unknown packets */
1778 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1779 MVPP2_PRS_RI_DROP_MASK);
1780
1781 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1782 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1783
1784 /* Update shadow table */
1785 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1786
1787 /* Mask all ports */
1788 mvpp2_prs_tcam_port_map_set(&pe, 0);
1789 }
1790
1791 /* Update port mask */
1792 mvpp2_prs_tcam_port_set(&pe, port, add);
1793
1794 mvpp2_prs_hw_write(priv, &pe);
1795}
1796
1797/* Set port to promiscuous mode */
1798static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1799{
1800 struct mvpp2_prs_entry pe;
1801
1802 /* Promiscuous mode - Accept unknown packets */
1803
1804 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1805 /* Entry exist - update port only */
1806 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1807 mvpp2_prs_hw_read(priv, &pe);
1808 } else {
1809 /* Entry doesn't exist - create new */
1810 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1811 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1812 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1813
1814 /* Continue - set next lookup */
1815 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1816
1817 /* Set result info bits */
1818 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1819 MVPP2_PRS_RI_L2_CAST_MASK);
1820
1821 /* Shift to ethertype */
1822 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1823 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1824
1825 /* Mask all ports */
1826 mvpp2_prs_tcam_port_map_set(&pe, 0);
1827
1828 /* Update shadow table */
1829 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1830 }
1831
1832 /* Update port mask */
1833 mvpp2_prs_tcam_port_set(&pe, port, add);
1834
1835 mvpp2_prs_hw_write(priv, &pe);
1836}
1837
1838/* Accept multicast */
1839static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1840 bool add)
1841{
1842 struct mvpp2_prs_entry pe;
1843 unsigned char da_mc;
1844
1845 /* Ethernet multicast address first byte is
1846 * 0x01 for IPv4 and 0x33 for IPv6
1847 */
1848 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1849
1850 if (priv->prs_shadow[index].valid) {
1851 /* Entry exist - update port only */
1852 pe.index = index;
1853 mvpp2_prs_hw_read(priv, &pe);
1854 } else {
1855 /* Entry doesn't exist - create new */
1856 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1857 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1858 pe.index = index;
1859
1860 /* Continue - set next lookup */
1861 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1862
1863 /* Set result info bits */
1864 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1865 MVPP2_PRS_RI_L2_CAST_MASK);
1866
1867 /* Update tcam entry data first byte */
1868 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1869
1870 /* Shift to ethertype */
1871 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1872 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1873
1874 /* Mask all ports */
1875 mvpp2_prs_tcam_port_map_set(&pe, 0);
1876
1877 /* Update shadow table */
1878 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1879 }
1880
1881 /* Update port mask */
1882 mvpp2_prs_tcam_port_set(&pe, port, add);
1883
1884 mvpp2_prs_hw_write(priv, &pe);
1885}
1886
1887/* Parser per-port initialization */
1888static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1889 int lu_max, int offset)
1890{
1891 u32 val;
1892
1893 /* Set lookup ID */
1894 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1895 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1896 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1897 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1898
1899 /* Set maximum number of loops for packet received from port */
1900 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1901 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1902 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1903 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1904
1905 /* Set initial offset for packet header extraction for the first
1906 * searching loop
1907 */
1908 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1909 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1910 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1911 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1912}
1913
1914/* Default flow entries initialization for all ports */
1915static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1916{
1917 struct mvpp2_prs_entry pe;
1918 int port;
1919
1920 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1921 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1922 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1923 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1924
1925 /* Mask all ports */
1926 mvpp2_prs_tcam_port_map_set(&pe, 0);
1927
1928 /* Set flow ID*/
1929 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1930 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1931
1932 /* Update shadow table and hw entry */
1933 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1934 mvpp2_prs_hw_write(priv, &pe);
1935 }
1936}
1937
1938/* Set default entry for Marvell Header field */
1939static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1940{
1941 struct mvpp2_prs_entry pe;
1942
1943 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1944
1945 pe.index = MVPP2_PE_MH_DEFAULT;
1946 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1947 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1948 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1949 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1950
1951 /* Unmask all ports */
1952 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1953
1954 /* Update shadow table and hw entry */
1955 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1956 mvpp2_prs_hw_write(priv, &pe);
1957}
1958
1959/* Set default entires (place holder) for promiscuous, non-promiscuous and
1960 * multicast MAC addresses
1961 */
1962static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1963{
1964 struct mvpp2_prs_entry pe;
1965
1966 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1967
1968 /* Non-promiscuous mode for all ports - DROP unknown packets */
1969 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1970 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1971
1972 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1973 MVPP2_PRS_RI_DROP_MASK);
1974 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1975 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1976
1977 /* Unmask all ports */
1978 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1979
1980 /* Update shadow table and hw entry */
1981 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1982 mvpp2_prs_hw_write(priv, &pe);
1983
1984 /* place holders only - no ports */
1985 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1986 mvpp2_prs_mac_promisc_set(priv, 0, false);
1987 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1988 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1989}
1990
1991/* Match basic ethertypes */
1992static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1993{
1994 struct mvpp2_prs_entry pe;
1995 int tid;
1996
1997 /* Ethertype: PPPoE */
1998 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1999 MVPP2_PE_LAST_FREE_TID);
2000 if (tid < 0)
2001 return tid;
2002
2003 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2004 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2005 pe.index = tid;
2006
2007 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
2008
2009 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2010 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2011 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2012 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2013 MVPP2_PRS_RI_PPPOE_MASK);
2014
2015 /* Update shadow table and hw entry */
2016 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2017 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2018 priv->prs_shadow[pe.index].finish = false;
2019 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2020 MVPP2_PRS_RI_PPPOE_MASK);
2021 mvpp2_prs_hw_write(priv, &pe);
2022
2023 /* Ethertype: ARP */
2024 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2025 MVPP2_PE_LAST_FREE_TID);
2026 if (tid < 0)
2027 return tid;
2028
2029 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2030 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2031 pe.index = tid;
2032
2033 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2034
2035 /* Generate flow in the next iteration*/
2036 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2037 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2038 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2039 MVPP2_PRS_RI_L3_PROTO_MASK);
2040 /* Set L3 offset */
2041 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2042 MVPP2_ETH_TYPE_LEN,
2043 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2044
2045 /* Update shadow table and hw entry */
2046 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2047 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2048 priv->prs_shadow[pe.index].finish = true;
2049 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2050 MVPP2_PRS_RI_L3_PROTO_MASK);
2051 mvpp2_prs_hw_write(priv, &pe);
2052
2053 /* Ethertype: LBTD */
2054 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2055 MVPP2_PE_LAST_FREE_TID);
2056 if (tid < 0)
2057 return tid;
2058
2059 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2060 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2061 pe.index = tid;
2062
2063 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2064
2065 /* Generate flow in the next iteration*/
2066 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2067 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2068 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2069 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2070 MVPP2_PRS_RI_CPU_CODE_MASK |
2071 MVPP2_PRS_RI_UDF3_MASK);
2072 /* Set L3 offset */
2073 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2074 MVPP2_ETH_TYPE_LEN,
2075 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2076
2077 /* Update shadow table and hw entry */
2078 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2079 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2080 priv->prs_shadow[pe.index].finish = true;
2081 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2082 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2083 MVPP2_PRS_RI_CPU_CODE_MASK |
2084 MVPP2_PRS_RI_UDF3_MASK);
2085 mvpp2_prs_hw_write(priv, &pe);
2086
2087 /* Ethertype: IPv4 without options */
2088 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2089 MVPP2_PE_LAST_FREE_TID);
2090 if (tid < 0)
2091 return tid;
2092
2093 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2094 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2095 pe.index = tid;
2096
2097 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2098 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2099 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2100 MVPP2_PRS_IPV4_HEAD_MASK |
2101 MVPP2_PRS_IPV4_IHL_MASK);
2102
2103 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2104 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2105 MVPP2_PRS_RI_L3_PROTO_MASK);
2106 /* Skip eth_type + 4 bytes of IP header */
2107 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2108 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2109 /* Set L3 offset */
2110 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2111 MVPP2_ETH_TYPE_LEN,
2112 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2113
2114 /* Update shadow table and hw entry */
2115 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2116 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2117 priv->prs_shadow[pe.index].finish = false;
2118 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2119 MVPP2_PRS_RI_L3_PROTO_MASK);
2120 mvpp2_prs_hw_write(priv, &pe);
2121
2122 /* Ethertype: IPv4 with options */
2123 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2124 MVPP2_PE_LAST_FREE_TID);
2125 if (tid < 0)
2126 return tid;
2127
2128 pe.index = tid;
2129
2130 /* Clear tcam data before updating */
2131 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2132 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2133
2134 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2135 MVPP2_PRS_IPV4_HEAD,
2136 MVPP2_PRS_IPV4_HEAD_MASK);
2137
2138 /* Clear ri before updating */
2139 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2140 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2141 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2142 MVPP2_PRS_RI_L3_PROTO_MASK);
2143
2144 /* Update shadow table and hw entry */
2145 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2146 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2147 priv->prs_shadow[pe.index].finish = false;
2148 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2149 MVPP2_PRS_RI_L3_PROTO_MASK);
2150 mvpp2_prs_hw_write(priv, &pe);
2151
2152 /* Ethertype: IPv6 without options */
2153 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2154 MVPP2_PE_LAST_FREE_TID);
2155 if (tid < 0)
2156 return tid;
2157
2158 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2159 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2160 pe.index = tid;
2161
2162 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2163
2164 /* Skip DIP of IPV6 header */
2165 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2166 MVPP2_MAX_L3_ADDR_SIZE,
2167 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2168 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2169 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2170 MVPP2_PRS_RI_L3_PROTO_MASK);
2171 /* Set L3 offset */
2172 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2173 MVPP2_ETH_TYPE_LEN,
2174 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2175
2176 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2177 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2178 priv->prs_shadow[pe.index].finish = false;
2179 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2180 MVPP2_PRS_RI_L3_PROTO_MASK);
2181 mvpp2_prs_hw_write(priv, &pe);
2182
2183 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2184 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2185 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2186 pe.index = MVPP2_PE_ETH_TYPE_UN;
2187
2188 /* Unmask all ports */
2189 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2190
2191 /* Generate flow in the next iteration*/
2192 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2193 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2194 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2195 MVPP2_PRS_RI_L3_PROTO_MASK);
2196 /* Set L3 offset even it's unknown L3 */
2197 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2198 MVPP2_ETH_TYPE_LEN,
2199 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2200
2201 /* Update shadow table and hw entry */
2202 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2203 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2204 priv->prs_shadow[pe.index].finish = true;
2205 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2206 MVPP2_PRS_RI_L3_PROTO_MASK);
2207 mvpp2_prs_hw_write(priv, &pe);
2208
2209 return 0;
2210}
2211
2212/* Parser default initialization */
2213static int mvpp2_prs_default_init(struct udevice *dev,
2214 struct mvpp2 *priv)
2215{
2216 int err, index, i;
2217
2218 /* Enable tcam table */
2219 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2220
2221 /* Clear all tcam and sram entries */
2222 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2223 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2224 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2225 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2226
2227 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2228 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2229 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2230 }
2231
2232 /* Invalidate all tcam entries */
2233 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2234 mvpp2_prs_hw_inv(priv, index);
2235
2236 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2237 sizeof(struct mvpp2_prs_shadow),
2238 GFP_KERNEL);
2239 if (!priv->prs_shadow)
2240 return -ENOMEM;
2241
2242 /* Always start from lookup = 0 */
2243 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2244 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2245 MVPP2_PRS_PORT_LU_MAX, 0);
2246
2247 mvpp2_prs_def_flow_init(priv);
2248
2249 mvpp2_prs_mh_init(priv);
2250
2251 mvpp2_prs_mac_init(priv);
2252
2253 err = mvpp2_prs_etype_init(priv);
2254 if (err)
2255 return err;
2256
2257 return 0;
2258}
2259
2260/* Compare MAC DA with tcam entry data */
2261static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2262 const u8 *da, unsigned char *mask)
2263{
2264 unsigned char tcam_byte, tcam_mask;
2265 int index;
2266
2267 for (index = 0; index < ETH_ALEN; index++) {
2268 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2269 if (tcam_mask != mask[index])
2270 return false;
2271
2272 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2273 return false;
2274 }
2275
2276 return true;
2277}
2278
2279/* Find tcam entry with matched pair <MAC DA, port> */
2280static struct mvpp2_prs_entry *
2281mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2282 unsigned char *mask, int udf_type)
2283{
2284 struct mvpp2_prs_entry *pe;
2285 int tid;
2286
2287 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2288 if (!pe)
2289 return NULL;
2290 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2291
2292 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2293 for (tid = MVPP2_PE_FIRST_FREE_TID;
2294 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2295 unsigned int entry_pmap;
2296
2297 if (!priv->prs_shadow[tid].valid ||
2298 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2299 (priv->prs_shadow[tid].udf != udf_type))
2300 continue;
2301
2302 pe->index = tid;
2303 mvpp2_prs_hw_read(priv, pe);
2304 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2305
2306 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2307 entry_pmap == pmap)
2308 return pe;
2309 }
2310 kfree(pe);
2311
2312 return NULL;
2313}
2314
2315/* Update parser's mac da entry */
2316static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2317 const u8 *da, bool add)
2318{
2319 struct mvpp2_prs_entry *pe;
2320 unsigned int pmap, len, ri;
2321 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2322 int tid;
2323
2324 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2325 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2326 MVPP2_PRS_UDF_MAC_DEF);
2327
2328 /* No such entry */
2329 if (!pe) {
2330 if (!add)
2331 return 0;
2332
2333 /* Create new TCAM entry */
2334 /* Find first range mac entry*/
2335 for (tid = MVPP2_PE_FIRST_FREE_TID;
2336 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2337 if (priv->prs_shadow[tid].valid &&
2338 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2339 (priv->prs_shadow[tid].udf ==
2340 MVPP2_PRS_UDF_MAC_RANGE))
2341 break;
2342
2343 /* Go through the all entries from first to last */
2344 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2345 tid - 1);
2346 if (tid < 0)
2347 return tid;
2348
2349 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2350 if (!pe)
2351 return -1;
2352 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2353 pe->index = tid;
2354
2355 /* Mask all ports */
2356 mvpp2_prs_tcam_port_map_set(pe, 0);
2357 }
2358
2359 /* Update port mask */
2360 mvpp2_prs_tcam_port_set(pe, port, add);
2361
2362 /* Invalidate the entry if no ports are left enabled */
2363 pmap = mvpp2_prs_tcam_port_map_get(pe);
2364 if (pmap == 0) {
2365 if (add) {
2366 kfree(pe);
2367 return -1;
2368 }
2369 mvpp2_prs_hw_inv(priv, pe->index);
2370 priv->prs_shadow[pe->index].valid = false;
2371 kfree(pe);
2372 return 0;
2373 }
2374
2375 /* Continue - set next lookup */
2376 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2377
2378 /* Set match on DA */
2379 len = ETH_ALEN;
2380 while (len--)
2381 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2382
2383 /* Set result info bits */
2384 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2385
2386 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2387 MVPP2_PRS_RI_MAC_ME_MASK);
2388 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2389 MVPP2_PRS_RI_MAC_ME_MASK);
2390
2391 /* Shift to ethertype */
2392 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2393 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2394
2395 /* Update shadow table and hw entry */
2396 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2397 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2398 mvpp2_prs_hw_write(priv, pe);
2399
2400 kfree(pe);
2401
2402 return 0;
2403}
2404
2405static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2406{
2407 int err;
2408
2409 /* Remove old parser entry */
2410 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2411 false);
2412 if (err)
2413 return err;
2414
2415 /* Add new parser entry */
2416 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2417 if (err)
2418 return err;
2419
2420 /* Set addr in the device */
2421 memcpy(port->dev_addr, da, ETH_ALEN);
2422
2423 return 0;
2424}
2425
2426/* Set prs flow for the port */
2427static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2428{
2429 struct mvpp2_prs_entry *pe;
2430 int tid;
2431
2432 pe = mvpp2_prs_flow_find(port->priv, port->id);
2433
2434 /* Such entry not exist */
2435 if (!pe) {
2436 /* Go through the all entires from last to first */
2437 tid = mvpp2_prs_tcam_first_free(port->priv,
2438 MVPP2_PE_LAST_FREE_TID,
2439 MVPP2_PE_FIRST_FREE_TID);
2440 if (tid < 0)
2441 return tid;
2442
2443 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2444 if (!pe)
2445 return -ENOMEM;
2446
2447 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2448 pe->index = tid;
2449
2450 /* Set flow ID*/
2451 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2452 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2453
2454 /* Update shadow table */
2455 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2456 }
2457
2458 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2459 mvpp2_prs_hw_write(port->priv, pe);
2460 kfree(pe);
2461
2462 return 0;
2463}
2464
2465/* Classifier configuration routines */
2466
2467/* Update classification flow table registers */
2468static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2469 struct mvpp2_cls_flow_entry *fe)
2470{
2471 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2472 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2473 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2474 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2475}
2476
2477/* Update classification lookup table register */
2478static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2479 struct mvpp2_cls_lookup_entry *le)
2480{
2481 u32 val;
2482
2483 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2484 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2485 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2486}
2487
2488/* Classifier default initialization */
2489static void mvpp2_cls_init(struct mvpp2 *priv)
2490{
2491 struct mvpp2_cls_lookup_entry le;
2492 struct mvpp2_cls_flow_entry fe;
2493 int index;
2494
2495 /* Enable classifier */
2496 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2497
2498 /* Clear classifier flow table */
2499 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2500 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2501 fe.index = index;
2502 mvpp2_cls_flow_write(priv, &fe);
2503 }
2504
2505 /* Clear classifier lookup table */
2506 le.data = 0;
2507 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2508 le.lkpid = index;
2509 le.way = 0;
2510 mvpp2_cls_lookup_write(priv, &le);
2511
2512 le.way = 1;
2513 mvpp2_cls_lookup_write(priv, &le);
2514 }
2515}
2516
2517static void mvpp2_cls_port_config(struct mvpp2_port *port)
2518{
2519 struct mvpp2_cls_lookup_entry le;
2520 u32 val;
2521
2522 /* Set way for the port */
2523 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2524 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2525 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2526
2527 /* Pick the entry to be accessed in lookup ID decoding table
2528 * according to the way and lkpid.
2529 */
2530 le.lkpid = port->id;
2531 le.way = 0;
2532 le.data = 0;
2533
2534 /* Set initial CPU queue for receiving packets */
2535 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2536 le.data |= port->first_rxq;
2537
2538 /* Disable classification engines */
2539 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2540
2541 /* Update lookup ID table entry */
2542 mvpp2_cls_lookup_write(port->priv, &le);
2543}
2544
2545/* Set CPU queue number for oversize packets */
2546static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2547{
2548 u32 val;
2549
2550 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2551 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2552
2553 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2554 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2555
2556 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2557 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2558 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2559}
2560
2561/* Buffer Manager configuration routines */
2562
2563/* Create pool */
2564static int mvpp2_bm_pool_create(struct udevice *dev,
2565 struct mvpp2 *priv,
2566 struct mvpp2_bm_pool *bm_pool, int size)
2567{
2568 u32 val;
2569
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002570 /* Number of buffer pointers must be a multiple of 16, as per
2571 * hardware constraints
2572 */
2573 if (!IS_ALIGNED(size, 16))
2574 return -EINVAL;
2575
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002576 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002577 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002578 if (!bm_pool->virt_addr)
2579 return -ENOMEM;
2580
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002581 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2582 MVPP2_BM_POOL_PTR_ALIGN)) {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002583 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2584 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2585 return -ENOMEM;
2586 }
2587
2588 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002589 lower_32_bits(bm_pool->dma_addr));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002590 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2591
2592 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2593 val |= MVPP2_BM_START_MASK;
2594 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2595
2596 bm_pool->type = MVPP2_BM_FREE;
2597 bm_pool->size = size;
2598 bm_pool->pkt_size = 0;
2599 bm_pool->buf_num = 0;
2600
2601 return 0;
2602}
2603
2604/* Set pool buffer size */
2605static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2606 struct mvpp2_bm_pool *bm_pool,
2607 int buf_size)
2608{
2609 u32 val;
2610
2611 bm_pool->buf_size = buf_size;
2612
2613 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2614 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2615}
2616
2617/* Free all buffers from the pool */
2618static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2619 struct mvpp2_bm_pool *bm_pool)
2620{
Stefan Roese2f720f12017-03-23 17:01:59 +01002621 int i;
2622
2623 for (i = 0; i < bm_pool->buf_num; i++) {
2624 /* Allocate buffer back from the buffer manager */
2625 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2626 }
2627
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002628 bm_pool->buf_num = 0;
2629}
2630
2631/* Cleanup pool */
2632static int mvpp2_bm_pool_destroy(struct udevice *dev,
2633 struct mvpp2 *priv,
2634 struct mvpp2_bm_pool *bm_pool)
2635{
2636 u32 val;
2637
2638 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2639 if (bm_pool->buf_num) {
2640 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2641 return 0;
2642 }
2643
2644 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2645 val |= MVPP2_BM_STOP_MASK;
2646 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2647
2648 return 0;
2649}
2650
2651static int mvpp2_bm_pools_init(struct udevice *dev,
2652 struct mvpp2 *priv)
2653{
2654 int i, err, size;
2655 struct mvpp2_bm_pool *bm_pool;
2656
2657 /* Create all pools with maximum size */
2658 size = MVPP2_BM_POOL_SIZE_MAX;
2659 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2660 bm_pool = &priv->bm_pools[i];
2661 bm_pool->id = i;
2662 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2663 if (err)
2664 goto err_unroll_pools;
2665 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2666 }
2667 return 0;
2668
2669err_unroll_pools:
2670 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2671 for (i = i - 1; i >= 0; i--)
2672 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2673 return err;
2674}
2675
2676static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2677{
2678 int i, err;
2679
2680 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2681 /* Mask BM all interrupts */
2682 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2683 /* Clear BM cause register */
2684 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2685 }
2686
2687 /* Allocate and initialize BM pools */
2688 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2689 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2690 if (!priv->bm_pools)
2691 return -ENOMEM;
2692
2693 err = mvpp2_bm_pools_init(dev, priv);
2694 if (err < 0)
2695 return err;
2696 return 0;
2697}
2698
2699/* Attach long pool to rxq */
2700static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2701 int lrxq, int long_pool)
2702{
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002703 u32 val, mask;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002704 int prxq;
2705
2706 /* Get queue physical ID */
2707 prxq = port->rxqs[lrxq]->id;
2708
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002709 if (port->priv->hw_version == MVPP21)
2710 mask = MVPP21_RXQ_POOL_LONG_MASK;
2711 else
2712 mask = MVPP22_RXQ_POOL_LONG_MASK;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002713
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002714 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2715 val &= ~mask;
2716 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002717 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2718}
2719
2720/* Set pool number in a BM cookie */
2721static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2722{
2723 u32 bm;
2724
2725 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2726 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2727
2728 return bm;
2729}
2730
2731/* Get pool number from a BM cookie */
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002732static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002733{
2734 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2735}
2736
2737/* Release buffer to BM */
2738static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002739 dma_addr_t buf_dma_addr,
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002740 unsigned long buf_phys_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002741{
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002742 if (port->priv->hw_version == MVPP22) {
2743 u32 val = 0;
2744
2745 if (sizeof(dma_addr_t) == 8)
2746 val |= upper_32_bits(buf_dma_addr) &
2747 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2748
2749 if (sizeof(phys_addr_t) == 8)
2750 val |= (upper_32_bits(buf_phys_addr)
2751 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2752 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2753
2754 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2755 }
2756
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002757 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2758 * returned in the "cookie" field of the RX
2759 * descriptor. Instead of storing the virtual address, we
2760 * store the physical address
2761 */
2762 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002763 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002764}
2765
2766/* Refill BM pool */
2767static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002768 dma_addr_t dma_addr,
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002769 phys_addr_t phys_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002770{
2771 int pool = mvpp2_bm_cookie_pool_get(bm);
2772
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002773 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002774}
2775
2776/* Allocate buffers for the pool */
2777static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2778 struct mvpp2_bm_pool *bm_pool, int buf_num)
2779{
2780 int i;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002781
2782 if (buf_num < 0 ||
2783 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2784 netdev_err(port->dev,
2785 "cannot allocate %d buffers for pool %d\n",
2786 buf_num, bm_pool->id);
2787 return 0;
2788 }
2789
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002790 for (i = 0; i < buf_num; i++) {
Thomas Petazzonif1060f02017-02-15 12:13:43 +01002791 mvpp2_bm_pool_put(port, bm_pool->id,
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002792 (dma_addr_t)buffer_loc.rx_buffer[i],
2793 (unsigned long)buffer_loc.rx_buffer[i]);
Thomas Petazzonif1060f02017-02-15 12:13:43 +01002794
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002795 }
2796
2797 /* Update BM driver with number of buffers added to pool */
2798 bm_pool->buf_num += i;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002799
2800 return i;
2801}
2802
2803/* Notify the driver that BM pool is being used as specific type and return the
2804 * pool pointer on success
2805 */
2806static struct mvpp2_bm_pool *
2807mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2808 int pkt_size)
2809{
2810 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2811 int num;
2812
2813 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2814 netdev_err(port->dev, "mixing pool types is forbidden\n");
2815 return NULL;
2816 }
2817
2818 if (new_pool->type == MVPP2_BM_FREE)
2819 new_pool->type = type;
2820
2821 /* Allocate buffers in case BM pool is used as long pool, but packet
2822 * size doesn't match MTU or BM pool hasn't being used yet
2823 */
2824 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2825 (new_pool->pkt_size == 0)) {
2826 int pkts_num;
2827
2828 /* Set default buffer number or free all the buffers in case
2829 * the pool is not empty
2830 */
2831 pkts_num = new_pool->buf_num;
2832 if (pkts_num == 0)
2833 pkts_num = type == MVPP2_BM_SWF_LONG ?
2834 MVPP2_BM_LONG_BUF_NUM :
2835 MVPP2_BM_SHORT_BUF_NUM;
2836 else
2837 mvpp2_bm_bufs_free(NULL,
2838 port->priv, new_pool);
2839
2840 new_pool->pkt_size = pkt_size;
2841
2842 /* Allocate buffers for this pool */
2843 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2844 if (num != pkts_num) {
2845 dev_err(dev, "pool %d: %d of %d allocated\n",
2846 new_pool->id, num, pkts_num);
2847 return NULL;
2848 }
2849 }
2850
2851 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2852 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2853
2854 return new_pool;
2855}
2856
2857/* Initialize pools for swf */
2858static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2859{
2860 int rxq;
2861
2862 if (!port->pool_long) {
2863 port->pool_long =
2864 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2865 MVPP2_BM_SWF_LONG,
2866 port->pkt_size);
2867 if (!port->pool_long)
2868 return -ENOMEM;
2869
2870 port->pool_long->port_map |= (1 << port->id);
2871
2872 for (rxq = 0; rxq < rxq_number; rxq++)
2873 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2874 }
2875
2876 return 0;
2877}
2878
2879/* Port configuration routines */
2880
2881static void mvpp2_port_mii_set(struct mvpp2_port *port)
2882{
2883 u32 val;
2884
2885 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2886
2887 switch (port->phy_interface) {
2888 case PHY_INTERFACE_MODE_SGMII:
2889 val |= MVPP2_GMAC_INBAND_AN_MASK;
2890 break;
2891 case PHY_INTERFACE_MODE_RGMII:
Stefan Roese025e5922017-03-22 15:11:00 +01002892 case PHY_INTERFACE_MODE_RGMII_ID:
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002893 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2894 default:
2895 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2896 }
2897
2898 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2899}
2900
2901static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2902{
2903 u32 val;
2904
2905 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2906 val |= MVPP2_GMAC_FC_ADV_EN;
2907 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2908}
2909
2910static void mvpp2_port_enable(struct mvpp2_port *port)
2911{
2912 u32 val;
2913
2914 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2915 val |= MVPP2_GMAC_PORT_EN_MASK;
2916 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2917 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2918}
2919
2920static void mvpp2_port_disable(struct mvpp2_port *port)
2921{
2922 u32 val;
2923
2924 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2925 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2926 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2927}
2928
2929/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2930static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2931{
2932 u32 val;
2933
2934 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2935 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2936 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2937}
2938
2939/* Configure loopback port */
2940static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2941{
2942 u32 val;
2943
2944 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2945
2946 if (port->speed == 1000)
2947 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2948 else
2949 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2950
2951 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2952 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2953 else
2954 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2955
2956 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2957}
2958
2959static void mvpp2_port_reset(struct mvpp2_port *port)
2960{
2961 u32 val;
2962
2963 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2964 ~MVPP2_GMAC_PORT_RESET_MASK;
2965 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2966
2967 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2968 MVPP2_GMAC_PORT_RESET_MASK)
2969 continue;
2970}
2971
2972/* Change maximum receive size of the port */
2973static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2974{
2975 u32 val;
2976
2977 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2978 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2979 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2980 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2981 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2982}
2983
Stefan Roese31aa1e32017-03-22 15:07:30 +01002984/* PPv2.2 GoP/GMAC config */
2985
2986/* Set the MAC to reset or exit from reset */
2987static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2988{
2989 u32 val;
2990
2991 /* read - modify - write */
2992 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2993 if (reset)
2994 val |= MVPP2_GMAC_PORT_RESET_MASK;
2995 else
2996 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2997 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2998
2999 return 0;
3000}
3001
3002/*
3003 * gop_gpcs_mode_cfg
3004 *
3005 * Configure port to working with Gig PCS or don't.
3006 */
3007static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
3008{
3009 u32 val;
3010
3011 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3012 if (en)
3013 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
3014 else
3015 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3016 /* enable / disable PCS on this port */
3017 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3018
3019 return 0;
3020}
3021
3022static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3023{
3024 u32 val;
3025
3026 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3027 if (en)
3028 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3029 else
3030 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3031 /* enable / disable PCS on this port */
3032 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3033
3034 return 0;
3035}
3036
3037static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3038{
3039 u32 val, thresh;
3040
3041 /*
3042 * Configure minimal level of the Tx FIFO before the lower part
3043 * starts to read a packet
3044 */
3045 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3046 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3047 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3048 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3049 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3050
3051 /* Disable bypass of sync module */
3052 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3053 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3054 /* configure DP clock select according to mode */
3055 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3056 /* configure QSGMII bypass according to mode */
3057 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3058 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3059
3060 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3061 val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
3062 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3063
3064 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3065 /*
3066 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3067 * transceiver
3068 */
3069 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3070 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3071
3072 /* configure AN 0x9268 */
3073 val = MVPP2_GMAC_EN_PCS_AN |
3074 MVPP2_GMAC_AN_BYPASS_EN |
3075 MVPP2_GMAC_CONFIG_MII_SPEED |
3076 MVPP2_GMAC_CONFIG_GMII_SPEED |
3077 MVPP2_GMAC_FC_ADV_EN |
3078 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3079 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3080 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3081}
3082
3083static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3084{
3085 u32 val, thresh;
3086
3087 /*
3088 * Configure minimal level of the Tx FIFO before the lower part
3089 * starts to read a packet
3090 */
3091 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3092 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3093 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3094 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3095 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3096
3097 /* Disable bypass of sync module */
3098 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3099 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3100 /* configure DP clock select according to mode */
3101 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3102 /* configure QSGMII bypass according to mode */
3103 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3104 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3105
3106 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3107 val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
3108 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3109
3110 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3111 /* configure GIG MAC to SGMII mode */
3112 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3113 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3114
3115 /* configure AN */
3116 val = MVPP2_GMAC_EN_PCS_AN |
3117 MVPP2_GMAC_AN_BYPASS_EN |
3118 MVPP2_GMAC_AN_SPEED_EN |
3119 MVPP2_GMAC_EN_FC_AN |
3120 MVPP2_GMAC_AN_DUPLEX_EN |
3121 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3122 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3123}
3124
3125static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3126{
3127 u32 val, thresh;
3128
3129 /*
3130 * Configure minimal level of the Tx FIFO before the lower part
3131 * starts to read a packet
3132 */
3133 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3134 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3135 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3136 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3137 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3138
3139 /* Disable bypass of sync module */
3140 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3141 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3142 /* configure DP clock select according to mode */
3143 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3144 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3145 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3146 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3147
3148 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3149 val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
3150 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3151
3152 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3153 /* configure GIG MAC to SGMII mode */
3154 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3155 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3156
3157 /* configure AN 0xb8e8 */
3158 val = MVPP2_GMAC_AN_BYPASS_EN |
3159 MVPP2_GMAC_AN_SPEED_EN |
3160 MVPP2_GMAC_EN_FC_AN |
3161 MVPP2_GMAC_AN_DUPLEX_EN |
3162 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3163 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3164}
3165
3166/* Set the internal mux's to the required MAC in the GOP */
3167static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3168{
3169 u32 val;
3170
3171 /* Set TX FIFO thresholds */
3172 switch (port->phy_interface) {
3173 case PHY_INTERFACE_MODE_SGMII:
3174 if (port->phy_speed == 2500)
3175 gop_gmac_sgmii2_5_cfg(port);
3176 else
3177 gop_gmac_sgmii_cfg(port);
3178 break;
3179
3180 case PHY_INTERFACE_MODE_RGMII:
3181 case PHY_INTERFACE_MODE_RGMII_ID:
3182 gop_gmac_rgmii_cfg(port);
3183 break;
3184
3185 default:
3186 return -1;
3187 }
3188
3189 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3190 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3191 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3192 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3193 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3194
3195 /* PeriodicXonEn disable */
3196 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3197 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3198 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3199
3200 return 0;
3201}
3202
3203static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3204{
3205 u32 val;
3206
3207 /* relevant only for MAC0 (XLG0 and GMAC0) */
3208 if (port->gop_id > 0)
3209 return;
3210
3211 /* configure 1Gig MAC mode */
3212 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3213 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3214 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3215 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3216}
3217
3218static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3219{
3220 u32 val;
3221
3222 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3223 if (reset)
3224 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3225 else
3226 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3227 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3228
3229 return 0;
3230}
3231
Stefan Roese2fe23042017-03-22 15:09:38 +01003232/* Set the internal mux's to the required PCS in the PI */
3233static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3234{
3235 u32 val;
3236 int lane;
3237
3238 switch (num_of_lanes) {
3239 case 1:
3240 lane = 0;
3241 break;
3242 case 2:
3243 lane = 1;
3244 break;
3245 case 4:
3246 lane = 2;
3247 break;
3248 default:
3249 return -1;
3250 }
3251
3252 /* configure XG MAC mode */
3253 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
Stefan Chulskie09d0c82017-04-06 15:39:08 +02003254 val &= ~MVPP22_XPCS_PCSMODE_MASK;
Stefan Roese2fe23042017-03-22 15:09:38 +01003255 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3256 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3257 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3258
3259 return 0;
3260}
3261
3262static int gop_mpcs_mode(struct mvpp2_port *port)
3263{
3264 u32 val;
3265
3266 /* configure PCS40G COMMON CONTROL */
3267 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3268 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3269 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3270
3271 /* configure PCS CLOCK RESET */
3272 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3273 val &= ~CLK_DIVISION_RATIO_MASK;
3274 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3275 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3276
3277 val &= ~CLK_DIV_PHASE_SET_MASK;
3278 val |= MAC_CLK_RESET_MASK;
3279 val |= RX_SD_CLK_RESET_MASK;
3280 val |= TX_SD_CLK_RESET_MASK;
3281 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3282
3283 return 0;
3284}
3285
3286/* Set the internal mux's to the required MAC in the GOP */
3287static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3288{
3289 u32 val;
3290
3291 /* configure 10G MAC mode */
3292 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3293 val |= MVPP22_XLG_RX_FC_EN;
3294 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3295
3296 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3297 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3298 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3299 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3300
3301 /* read - modify - write */
3302 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3303 val &= ~MVPP22_XLG_MODE_DMA_1G;
3304 val |= MVPP22_XLG_FORWARD_PFC_EN;
3305 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3306 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3307 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3308
3309 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3310 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3311 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3312 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3313 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3314
3315 /* unmask link change interrupt */
3316 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3317 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3318 val |= 1; /* unmask summary bit */
3319 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3320
3321 return 0;
3322}
3323
3324/* Set PCS to reset or exit from reset */
3325static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3326{
3327 u32 val;
3328
3329 /* read - modify - write */
3330 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3331 if (reset)
3332 val &= ~MVPP22_XPCS_PCSRESET;
3333 else
3334 val |= MVPP22_XPCS_PCSRESET;
3335 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3336
3337 return 0;
3338}
3339
3340/* Set the MAC to reset or exit from reset */
3341static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3342{
3343 u32 val;
3344
3345 /* read - modify - write */
3346 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3347 if (reset)
3348 val &= ~MVPP22_XLG_MAC_RESETN;
3349 else
3350 val |= MVPP22_XLG_MAC_RESETN;
3351 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3352
3353 return 0;
3354}
3355
Stefan Roese31aa1e32017-03-22 15:07:30 +01003356/*
3357 * gop_port_init
3358 *
3359 * Init physical port. Configures the port mode and all it's elements
3360 * accordingly.
3361 * Does not verify that the selected mode/port number is valid at the
3362 * core level.
3363 */
3364static int gop_port_init(struct mvpp2_port *port)
3365{
3366 int mac_num = port->gop_id;
Stefan Roese2fe23042017-03-22 15:09:38 +01003367 int num_of_act_lanes;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003368
3369 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3370 netdev_err(NULL, "%s: illegal port number %d", __func__,
3371 mac_num);
3372 return -1;
3373 }
3374
3375 switch (port->phy_interface) {
3376 case PHY_INTERFACE_MODE_RGMII:
3377 case PHY_INTERFACE_MODE_RGMII_ID:
3378 gop_gmac_reset(port, 1);
3379
3380 /* configure PCS */
3381 gop_gpcs_mode_cfg(port, 0);
3382 gop_bypass_clk_cfg(port, 1);
3383
3384 /* configure MAC */
3385 gop_gmac_mode_cfg(port);
3386 /* pcs unreset */
3387 gop_gpcs_reset(port, 0);
3388
3389 /* mac unreset */
3390 gop_gmac_reset(port, 0);
3391 break;
3392
3393 case PHY_INTERFACE_MODE_SGMII:
3394 /* configure PCS */
3395 gop_gpcs_mode_cfg(port, 1);
3396
3397 /* configure MAC */
3398 gop_gmac_mode_cfg(port);
3399 /* select proper Mac mode */
3400 gop_xlg_2_gig_mac_cfg(port);
3401
3402 /* pcs unreset */
3403 gop_gpcs_reset(port, 0);
3404 /* mac unreset */
3405 gop_gmac_reset(port, 0);
3406 break;
3407
Stefan Roese2fe23042017-03-22 15:09:38 +01003408 case PHY_INTERFACE_MODE_SFI:
3409 num_of_act_lanes = 2;
3410 mac_num = 0;
3411 /* configure PCS */
3412 gop_xpcs_mode(port, num_of_act_lanes);
3413 gop_mpcs_mode(port);
3414 /* configure MAC */
3415 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3416
3417 /* pcs unreset */
3418 gop_xpcs_reset(port, 0);
3419
3420 /* mac unreset */
3421 gop_xlg_mac_reset(port, 0);
3422 break;
3423
Stefan Roese31aa1e32017-03-22 15:07:30 +01003424 default:
3425 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3426 __func__, port->phy_interface);
3427 return -1;
3428 }
3429
3430 return 0;
3431}
3432
Stefan Roese2fe23042017-03-22 15:09:38 +01003433static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3434{
3435 u32 val;
3436
3437 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3438 if (enable) {
3439 /* Enable port and MIB counters update */
3440 val |= MVPP22_XLG_PORT_EN;
3441 val &= ~MVPP22_XLG_MIBCNT_DIS;
3442 } else {
3443 /* Disable port */
3444 val &= ~MVPP22_XLG_PORT_EN;
3445 }
3446 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3447}
3448
Stefan Roese31aa1e32017-03-22 15:07:30 +01003449static void gop_port_enable(struct mvpp2_port *port, int enable)
3450{
3451 switch (port->phy_interface) {
3452 case PHY_INTERFACE_MODE_RGMII:
3453 case PHY_INTERFACE_MODE_RGMII_ID:
3454 case PHY_INTERFACE_MODE_SGMII:
3455 if (enable)
3456 mvpp2_port_enable(port);
3457 else
3458 mvpp2_port_disable(port);
3459 break;
3460
Stefan Roese2fe23042017-03-22 15:09:38 +01003461 case PHY_INTERFACE_MODE_SFI:
3462 gop_xlg_mac_port_enable(port, enable);
3463
3464 break;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003465 default:
3466 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3467 port->phy_interface);
3468 return;
3469 }
3470}
3471
3472/* RFU1 functions */
3473static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3474{
3475 return readl(priv->rfu1_base + offset);
3476}
3477
3478static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3479{
3480 writel(data, priv->rfu1_base + offset);
3481}
3482
3483static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3484{
3485 u32 val = 0;
3486
3487 if (gop_id == 2) {
3488 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3489 val |= MV_NETC_GE_MAC2_SGMII;
3490 }
3491
3492 if (gop_id == 3) {
3493 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3494 val |= MV_NETC_GE_MAC3_SGMII;
3495 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3496 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3497 val |= MV_NETC_GE_MAC3_RGMII;
3498 }
3499
3500 return val;
3501}
3502
3503static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3504{
3505 u32 reg;
3506
3507 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3508 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3509
3510 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3511 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3512
3513 reg |= val;
3514
3515 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3516}
3517
3518static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3519{
3520 u32 reg;
3521
3522 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3523 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3524
3525 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3526 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3527
3528 reg |= val;
3529
3530 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3531}
3532
3533static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3534{
3535 u32 reg;
3536
3537 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3538 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3539
3540 val <<= NETC_GOP_SOFT_RESET_OFFS;
3541 val &= NETC_GOP_SOFT_RESET_MASK;
3542
3543 reg |= val;
3544
3545 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3546}
3547
3548static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3549{
3550 u32 reg;
3551
3552 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3553 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3554
3555 val <<= NETC_CLK_DIV_PHASE_OFFS;
3556 val &= NETC_CLK_DIV_PHASE_MASK;
3557
3558 reg |= val;
3559
3560 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3561}
3562
3563static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3564{
3565 u32 reg;
3566
3567 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3568 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3569
3570 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3571 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3572
3573 reg |= val;
3574
3575 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3576}
3577
3578static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3579 u32 val)
3580{
3581 u32 reg, mask, offset;
3582
3583 if (gop_id == 2) {
3584 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3585 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3586 } else {
3587 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3588 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3589 }
3590 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3591 reg &= ~mask;
3592
3593 val <<= offset;
3594 val &= mask;
3595
3596 reg |= val;
3597
3598 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3599}
3600
3601static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3602{
3603 u32 reg;
3604
3605 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3606 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3607
3608 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3609 val &= NETC_BUS_WIDTH_SELECT_MASK;
3610
3611 reg |= val;
3612
3613 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3614}
3615
3616static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3617{
3618 u32 reg;
3619
3620 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3621 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3622
3623 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3624 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3625
3626 reg |= val;
3627
3628 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3629}
3630
3631static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3632 enum mv_netc_phase phase)
3633{
3634 switch (phase) {
3635 case MV_NETC_FIRST_PHASE:
3636 /* Set Bus Width to HB mode = 1 */
3637 gop_netc_bus_width_select(priv, 1);
3638 /* Select RGMII mode */
3639 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3640 break;
3641
3642 case MV_NETC_SECOND_PHASE:
3643 /* De-assert the relevant port HB reset */
3644 gop_netc_port_rf_reset(priv, gop_id, 1);
3645 break;
3646 }
3647}
3648
3649static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3650 enum mv_netc_phase phase)
3651{
3652 switch (phase) {
3653 case MV_NETC_FIRST_PHASE:
3654 /* Set Bus Width to HB mode = 1 */
3655 gop_netc_bus_width_select(priv, 1);
3656 /* Select SGMII mode */
3657 if (gop_id >= 1) {
3658 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3659 MV_NETC_GBE_SGMII);
3660 }
3661
3662 /* Configure the sample stages */
3663 gop_netc_sample_stages_timing(priv, 0);
3664 /* Configure the ComPhy Selector */
3665 /* gop_netc_com_phy_selector_config(netComplex); */
3666 break;
3667
3668 case MV_NETC_SECOND_PHASE:
3669 /* De-assert the relevant port HB reset */
3670 gop_netc_port_rf_reset(priv, gop_id, 1);
3671 break;
3672 }
3673}
3674
3675static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3676{
3677 u32 c = priv->netc_config;
3678
3679 if (c & MV_NETC_GE_MAC2_SGMII)
3680 gop_netc_mac_to_sgmii(priv, 2, phase);
3681 else
3682 gop_netc_mac_to_xgmii(priv, 2, phase);
3683
3684 if (c & MV_NETC_GE_MAC3_SGMII) {
3685 gop_netc_mac_to_sgmii(priv, 3, phase);
3686 } else {
3687 gop_netc_mac_to_xgmii(priv, 3, phase);
3688 if (c & MV_NETC_GE_MAC3_RGMII)
3689 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3690 else
3691 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3692 }
3693
3694 /* Activate gop ports 0, 2, 3 */
3695 gop_netc_active_port(priv, 0, 1);
3696 gop_netc_active_port(priv, 2, 1);
3697 gop_netc_active_port(priv, 3, 1);
3698
3699 if (phase == MV_NETC_SECOND_PHASE) {
3700 /* Enable the GOP internal clock logic */
3701 gop_netc_gop_clock_logic_set(priv, 1);
3702 /* De-assert GOP unit reset */
3703 gop_netc_gop_reset(priv, 1);
3704 }
3705
3706 return 0;
3707}
3708
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003709/* Set defaults to the MVPP2 port */
3710static void mvpp2_defaults_set(struct mvpp2_port *port)
3711{
3712 int tx_port_num, val, queue, ptxq, lrxq;
3713
Thomas Petazzonib8c8e6f2017-02-16 06:57:24 +01003714 if (port->priv->hw_version == MVPP21) {
3715 /* Configure port to loopback if needed */
3716 if (port->flags & MVPP2_F_LOOPBACK)
3717 mvpp2_port_loopback_set(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003718
Thomas Petazzonib8c8e6f2017-02-16 06:57:24 +01003719 /* Update TX FIFO MIN Threshold */
3720 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3721 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3722 /* Min. TX threshold must be less than minimal packet length */
3723 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3724 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3725 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003726
3727 /* Disable Legacy WRR, Disable EJP, Release from reset */
3728 tx_port_num = mvpp2_egress_port(port);
3729 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3730 tx_port_num);
3731 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3732
3733 /* Close bandwidth for all queues */
3734 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3735 ptxq = mvpp2_txq_phys(port->id, queue);
3736 mvpp2_write(port->priv,
3737 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3738 }
3739
3740 /* Set refill period to 1 usec, refill tokens
3741 * and bucket size to maximum
3742 */
3743 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3744 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3745 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3746 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3747 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3748 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3749 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3750 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3751
3752 /* Set MaximumLowLatencyPacketSize value to 256 */
3753 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3754 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3755 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3756
3757 /* Enable Rx cache snoop */
3758 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3759 queue = port->rxqs[lrxq]->id;
3760 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3761 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3762 MVPP2_SNOOP_BUF_HDR_MASK;
3763 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3764 }
3765}
3766
3767/* Enable/disable receiving packets */
3768static void mvpp2_ingress_enable(struct mvpp2_port *port)
3769{
3770 u32 val;
3771 int lrxq, queue;
3772
3773 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3774 queue = port->rxqs[lrxq]->id;
3775 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3776 val &= ~MVPP2_RXQ_DISABLE_MASK;
3777 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3778 }
3779}
3780
3781static void mvpp2_ingress_disable(struct mvpp2_port *port)
3782{
3783 u32 val;
3784 int lrxq, queue;
3785
3786 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3787 queue = port->rxqs[lrxq]->id;
3788 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3789 val |= MVPP2_RXQ_DISABLE_MASK;
3790 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3791 }
3792}
3793
3794/* Enable transmit via physical egress queue
3795 * - HW starts take descriptors from DRAM
3796 */
3797static void mvpp2_egress_enable(struct mvpp2_port *port)
3798{
3799 u32 qmap;
3800 int queue;
3801 int tx_port_num = mvpp2_egress_port(port);
3802
3803 /* Enable all initialized TXs. */
3804 qmap = 0;
3805 for (queue = 0; queue < txq_number; queue++) {
3806 struct mvpp2_tx_queue *txq = port->txqs[queue];
3807
3808 if (txq->descs != NULL)
3809 qmap |= (1 << queue);
3810 }
3811
3812 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3813 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3814}
3815
3816/* Disable transmit via physical egress queue
3817 * - HW doesn't take descriptors from DRAM
3818 */
3819static void mvpp2_egress_disable(struct mvpp2_port *port)
3820{
3821 u32 reg_data;
3822 int delay;
3823 int tx_port_num = mvpp2_egress_port(port);
3824
3825 /* Issue stop command for active channels only */
3826 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3827 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3828 MVPP2_TXP_SCHED_ENQ_MASK;
3829 if (reg_data != 0)
3830 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3831 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3832
3833 /* Wait for all Tx activity to terminate. */
3834 delay = 0;
3835 do {
3836 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3837 netdev_warn(port->dev,
3838 "Tx stop timed out, status=0x%08x\n",
3839 reg_data);
3840 break;
3841 }
3842 mdelay(1);
3843 delay++;
3844
3845 /* Check port TX Command register that all
3846 * Tx queues are stopped
3847 */
3848 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3849 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3850}
3851
3852/* Rx descriptors helper methods */
3853
3854/* Get number of Rx descriptors occupied by received packets */
3855static inline int
3856mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3857{
3858 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3859
3860 return val & MVPP2_RXQ_OCCUPIED_MASK;
3861}
3862
3863/* Update Rx queue status with the number of occupied and available
3864 * Rx descriptor slots.
3865 */
3866static inline void
3867mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3868 int used_count, int free_count)
3869{
3870 /* Decrement the number of used descriptors and increment count
3871 * increment the number of free descriptors.
3872 */
3873 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3874
3875 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3876}
3877
3878/* Get pointer to next RX descriptor to be processed by SW */
3879static inline struct mvpp2_rx_desc *
3880mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3881{
3882 int rx_desc = rxq->next_desc_to_proc;
3883
3884 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3885 prefetch(rxq->descs + rxq->next_desc_to_proc);
3886 return rxq->descs + rx_desc;
3887}
3888
3889/* Set rx queue offset */
3890static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3891 int prxq, int offset)
3892{
3893 u32 val;
3894
3895 /* Convert offset from bytes to units of 32 bytes */
3896 offset = offset >> 5;
3897
3898 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3899 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3900
3901 /* Offset is in */
3902 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3903 MVPP2_RXQ_PACKET_OFFSET_MASK);
3904
3905 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3906}
3907
3908/* Obtain BM cookie information from descriptor */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01003909static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3910 struct mvpp2_rx_desc *rx_desc)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003911{
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003912 int cpu = smp_processor_id();
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01003913 int pool;
3914
3915 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3916 MVPP2_RXD_BM_POOL_ID_MASK) >>
3917 MVPP2_RXD_BM_POOL_ID_OFFS;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003918
3919 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3920 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3921}
3922
3923/* Tx descriptors helper methods */
3924
3925/* Get number of Tx descriptors waiting to be transmitted by HW */
3926static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3927 struct mvpp2_tx_queue *txq)
3928{
3929 u32 val;
3930
3931 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3932 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3933
3934 return val & MVPP2_TXQ_PENDING_MASK;
3935}
3936
3937/* Get pointer to next Tx descriptor to be processed (send) by HW */
3938static struct mvpp2_tx_desc *
3939mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3940{
3941 int tx_desc = txq->next_desc_to_proc;
3942
3943 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3944 return txq->descs + tx_desc;
3945}
3946
3947/* Update HW with number of aggregated Tx descriptors to be sent */
3948static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3949{
3950 /* aggregated access - relevant TXQ number is written in TX desc */
3951 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3952}
3953
3954/* Get number of sent descriptors and decrement counter.
3955 * The number of sent descriptors is returned.
3956 * Per-CPU access
3957 */
3958static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3959 struct mvpp2_tx_queue *txq)
3960{
3961 u32 val;
3962
3963 /* Reading status reg resets transmitted descriptor counter */
3964 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3965
3966 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3967 MVPP2_TRANSMITTED_COUNT_OFFSET;
3968}
3969
3970static void mvpp2_txq_sent_counter_clear(void *arg)
3971{
3972 struct mvpp2_port *port = arg;
3973 int queue;
3974
3975 for (queue = 0; queue < txq_number; queue++) {
3976 int id = port->txqs[queue]->id;
3977
3978 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3979 }
3980}
3981
3982/* Set max sizes for Tx queues */
3983static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3984{
3985 u32 val, size, mtu;
3986 int txq, tx_port_num;
3987
3988 mtu = port->pkt_size * 8;
3989 if (mtu > MVPP2_TXP_MTU_MAX)
3990 mtu = MVPP2_TXP_MTU_MAX;
3991
3992 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3993 mtu = 3 * mtu;
3994
3995 /* Indirect access to registers */
3996 tx_port_num = mvpp2_egress_port(port);
3997 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3998
3999 /* Set MTU */
4000 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4001 val &= ~MVPP2_TXP_MTU_MAX;
4002 val |= mtu;
4003 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4004
4005 /* TXP token size and all TXQs token size must be larger that MTU */
4006 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4007 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4008 if (size < mtu) {
4009 size = mtu;
4010 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4011 val |= size;
4012 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4013 }
4014
4015 for (txq = 0; txq < txq_number; txq++) {
4016 val = mvpp2_read(port->priv,
4017 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4018 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4019
4020 if (size < mtu) {
4021 size = mtu;
4022 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4023 val |= size;
4024 mvpp2_write(port->priv,
4025 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4026 val);
4027 }
4028 }
4029}
4030
4031/* Free Tx queue skbuffs */
4032static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4033 struct mvpp2_tx_queue *txq,
4034 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4035{
4036 int i;
4037
4038 for (i = 0; i < num; i++)
4039 mvpp2_txq_inc_get(txq_pcpu);
4040}
4041
4042static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4043 u32 cause)
4044{
4045 int queue = fls(cause) - 1;
4046
4047 return port->rxqs[queue];
4048}
4049
4050static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4051 u32 cause)
4052{
4053 int queue = fls(cause) - 1;
4054
4055 return port->txqs[queue];
4056}
4057
4058/* Rx/Tx queue initialization/cleanup methods */
4059
4060/* Allocate and initialize descriptors for aggr TXQ */
4061static int mvpp2_aggr_txq_init(struct udevice *dev,
4062 struct mvpp2_tx_queue *aggr_txq,
4063 int desc_num, int cpu,
4064 struct mvpp2 *priv)
4065{
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004066 u32 txq_dma;
4067
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004068 /* Allocate memory for TX descriptors */
4069 aggr_txq->descs = buffer_loc.aggr_tx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004070 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004071 if (!aggr_txq->descs)
4072 return -ENOMEM;
4073
4074 /* Make sure descriptor address is cache line size aligned */
4075 BUG_ON(aggr_txq->descs !=
4076 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4077
4078 aggr_txq->last_desc = aggr_txq->size - 1;
4079
4080 /* Aggr TXQ no reset WA */
4081 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4082 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4083
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004084 /* Set Tx descriptors queue starting address indirect
4085 * access
4086 */
4087 if (priv->hw_version == MVPP21)
4088 txq_dma = aggr_txq->descs_dma;
4089 else
4090 txq_dma = aggr_txq->descs_dma >>
4091 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4092
4093 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004094 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4095
4096 return 0;
4097}
4098
4099/* Create a specified Rx queue */
4100static int mvpp2_rxq_init(struct mvpp2_port *port,
4101 struct mvpp2_rx_queue *rxq)
4102
4103{
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004104 u32 rxq_dma;
4105
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004106 rxq->size = port->rx_ring_size;
4107
4108 /* Allocate memory for RX descriptors */
4109 rxq->descs = buffer_loc.rx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004110 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004111 if (!rxq->descs)
4112 return -ENOMEM;
4113
4114 BUG_ON(rxq->descs !=
4115 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4116
4117 rxq->last_desc = rxq->size - 1;
4118
4119 /* Zero occupied and non-occupied counters - direct access */
4120 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4121
4122 /* Set Rx descriptors queue starting address - indirect access */
4123 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004124 if (port->priv->hw_version == MVPP21)
4125 rxq_dma = rxq->descs_dma;
4126 else
4127 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4128 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004129 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4130 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4131
4132 /* Set Offset */
4133 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4134
4135 /* Add number of descriptors ready for receiving packets */
4136 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4137
4138 return 0;
4139}
4140
4141/* Push packets received by the RXQ to BM pool */
4142static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4143 struct mvpp2_rx_queue *rxq)
4144{
4145 int rx_received, i;
4146
4147 rx_received = mvpp2_rxq_received(port, rxq->id);
4148 if (!rx_received)
4149 return;
4150
4151 for (i = 0; i < rx_received; i++) {
4152 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004153 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004154
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004155 mvpp2_pool_refill(port, bm,
4156 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4157 mvpp2_rxdesc_cookie_get(port, rx_desc));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004158 }
4159 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4160}
4161
4162/* Cleanup Rx queue */
4163static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4164 struct mvpp2_rx_queue *rxq)
4165{
4166 mvpp2_rxq_drop_pkts(port, rxq);
4167
4168 rxq->descs = NULL;
4169 rxq->last_desc = 0;
4170 rxq->next_desc_to_proc = 0;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004171 rxq->descs_dma = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004172
4173 /* Clear Rx descriptors queue starting address and size;
4174 * free descriptor number
4175 */
4176 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4177 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4178 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4179 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4180}
4181
4182/* Create and initialize a Tx queue */
4183static int mvpp2_txq_init(struct mvpp2_port *port,
4184 struct mvpp2_tx_queue *txq)
4185{
4186 u32 val;
4187 int cpu, desc, desc_per_txq, tx_port_num;
4188 struct mvpp2_txq_pcpu *txq_pcpu;
4189
4190 txq->size = port->tx_ring_size;
4191
4192 /* Allocate memory for Tx descriptors */
4193 txq->descs = buffer_loc.tx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004194 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004195 if (!txq->descs)
4196 return -ENOMEM;
4197
4198 /* Make sure descriptor address is cache line size aligned */
4199 BUG_ON(txq->descs !=
4200 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4201
4202 txq->last_desc = txq->size - 1;
4203
4204 /* Set Tx descriptors queue starting address - indirect access */
4205 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004206 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004207 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4208 MVPP2_TXQ_DESC_SIZE_MASK);
4209 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4210 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4211 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4212 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4213 val &= ~MVPP2_TXQ_PENDING_MASK;
4214 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4215
4216 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4217 * for each existing TXQ.
4218 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4219 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4220 */
4221 desc_per_txq = 16;
4222 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4223 (txq->log_id * desc_per_txq);
4224
4225 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4226 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
Thomas Petazzoni26a52782017-02-16 08:03:37 +01004227 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004228
4229 /* WRR / EJP configuration - indirect access */
4230 tx_port_num = mvpp2_egress_port(port);
4231 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4232
4233 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4234 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4235 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4236 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4237 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4238
4239 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4240 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4241 val);
4242
4243 for_each_present_cpu(cpu) {
4244 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4245 txq_pcpu->size = txq->size;
4246 }
4247
4248 return 0;
4249}
4250
4251/* Free allocated TXQ resources */
4252static void mvpp2_txq_deinit(struct mvpp2_port *port,
4253 struct mvpp2_tx_queue *txq)
4254{
4255 txq->descs = NULL;
4256 txq->last_desc = 0;
4257 txq->next_desc_to_proc = 0;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004258 txq->descs_dma = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004259
4260 /* Set minimum bandwidth for disabled TXQs */
4261 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4262
4263 /* Set Tx descriptors queue starting address and size */
4264 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4265 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4266 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4267}
4268
4269/* Cleanup Tx ports */
4270static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4271{
4272 struct mvpp2_txq_pcpu *txq_pcpu;
4273 int delay, pending, cpu;
4274 u32 val;
4275
4276 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4277 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4278 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4279 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4280
4281 /* The napi queue has been stopped so wait for all packets
4282 * to be transmitted.
4283 */
4284 delay = 0;
4285 do {
4286 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4287 netdev_warn(port->dev,
4288 "port %d: cleaning queue %d timed out\n",
4289 port->id, txq->log_id);
4290 break;
4291 }
4292 mdelay(1);
4293 delay++;
4294
4295 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4296 } while (pending);
4297
4298 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4299 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4300
4301 for_each_present_cpu(cpu) {
4302 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4303
4304 /* Release all packets */
4305 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4306
4307 /* Reset queue */
4308 txq_pcpu->count = 0;
4309 txq_pcpu->txq_put_index = 0;
4310 txq_pcpu->txq_get_index = 0;
4311 }
4312}
4313
4314/* Cleanup all Tx queues */
4315static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4316{
4317 struct mvpp2_tx_queue *txq;
4318 int queue;
4319 u32 val;
4320
4321 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4322
4323 /* Reset Tx ports and delete Tx queues */
4324 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4325 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4326
4327 for (queue = 0; queue < txq_number; queue++) {
4328 txq = port->txqs[queue];
4329 mvpp2_txq_clean(port, txq);
4330 mvpp2_txq_deinit(port, txq);
4331 }
4332
4333 mvpp2_txq_sent_counter_clear(port);
4334
4335 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4336 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4337}
4338
4339/* Cleanup all Rx queues */
4340static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4341{
4342 int queue;
4343
4344 for (queue = 0; queue < rxq_number; queue++)
4345 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4346}
4347
4348/* Init all Rx queues for port */
4349static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4350{
4351 int queue, err;
4352
4353 for (queue = 0; queue < rxq_number; queue++) {
4354 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4355 if (err)
4356 goto err_cleanup;
4357 }
4358 return 0;
4359
4360err_cleanup:
4361 mvpp2_cleanup_rxqs(port);
4362 return err;
4363}
4364
4365/* Init all tx queues for port */
4366static int mvpp2_setup_txqs(struct mvpp2_port *port)
4367{
4368 struct mvpp2_tx_queue *txq;
4369 int queue, err;
4370
4371 for (queue = 0; queue < txq_number; queue++) {
4372 txq = port->txqs[queue];
4373 err = mvpp2_txq_init(port, txq);
4374 if (err)
4375 goto err_cleanup;
4376 }
4377
4378 mvpp2_txq_sent_counter_clear(port);
4379 return 0;
4380
4381err_cleanup:
4382 mvpp2_cleanup_txqs(port);
4383 return err;
4384}
4385
4386/* Adjust link */
4387static void mvpp2_link_event(struct mvpp2_port *port)
4388{
4389 struct phy_device *phydev = port->phy_dev;
4390 int status_change = 0;
4391 u32 val;
4392
4393 if (phydev->link) {
4394 if ((port->speed != phydev->speed) ||
4395 (port->duplex != phydev->duplex)) {
4396 u32 val;
4397
4398 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4399 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4400 MVPP2_GMAC_CONFIG_GMII_SPEED |
4401 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4402 MVPP2_GMAC_AN_SPEED_EN |
4403 MVPP2_GMAC_AN_DUPLEX_EN);
4404
4405 if (phydev->duplex)
4406 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4407
4408 if (phydev->speed == SPEED_1000)
4409 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4410 else if (phydev->speed == SPEED_100)
4411 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4412
4413 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4414
4415 port->duplex = phydev->duplex;
4416 port->speed = phydev->speed;
4417 }
4418 }
4419
4420 if (phydev->link != port->link) {
4421 if (!phydev->link) {
4422 port->duplex = -1;
4423 port->speed = 0;
4424 }
4425
4426 port->link = phydev->link;
4427 status_change = 1;
4428 }
4429
4430 if (status_change) {
4431 if (phydev->link) {
4432 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4433 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4434 MVPP2_GMAC_FORCE_LINK_DOWN);
4435 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4436 mvpp2_egress_enable(port);
4437 mvpp2_ingress_enable(port);
4438 } else {
4439 mvpp2_ingress_disable(port);
4440 mvpp2_egress_disable(port);
4441 }
4442 }
4443}
4444
4445/* Main RX/TX processing routines */
4446
4447/* Display more error info */
4448static void mvpp2_rx_error(struct mvpp2_port *port,
4449 struct mvpp2_rx_desc *rx_desc)
4450{
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004451 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4452 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004453
4454 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4455 case MVPP2_RXD_ERR_CRC:
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004456 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4457 status, sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004458 break;
4459 case MVPP2_RXD_ERR_OVERRUN:
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004460 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4461 status, sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004462 break;
4463 case MVPP2_RXD_ERR_RESOURCE:
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004464 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4465 status, sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004466 break;
4467 }
4468}
4469
4470/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4471static int mvpp2_rx_refill(struct mvpp2_port *port,
4472 struct mvpp2_bm_pool *bm_pool,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004473 u32 bm, dma_addr_t dma_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004474{
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004475 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004476 return 0;
4477}
4478
4479/* Set hw internals when starting port */
4480static void mvpp2_start_dev(struct mvpp2_port *port)
4481{
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004482 switch (port->phy_interface) {
4483 case PHY_INTERFACE_MODE_RGMII:
4484 case PHY_INTERFACE_MODE_RGMII_ID:
4485 case PHY_INTERFACE_MODE_SGMII:
4486 mvpp2_gmac_max_rx_size_set(port);
4487 default:
4488 break;
4489 }
4490
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004491 mvpp2_txp_max_tx_size_set(port);
4492
Stefan Roese31aa1e32017-03-22 15:07:30 +01004493 if (port->priv->hw_version == MVPP21)
4494 mvpp2_port_enable(port);
4495 else
4496 gop_port_enable(port, 1);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004497}
4498
4499/* Set hw internals when stopping port */
4500static void mvpp2_stop_dev(struct mvpp2_port *port)
4501{
4502 /* Stop new packets from arriving to RXQs */
4503 mvpp2_ingress_disable(port);
4504
4505 mvpp2_egress_disable(port);
Stefan Roese31aa1e32017-03-22 15:07:30 +01004506
4507 if (port->priv->hw_version == MVPP21)
4508 mvpp2_port_disable(port);
4509 else
4510 gop_port_enable(port, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004511}
4512
4513static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4514{
4515 struct phy_device *phy_dev;
4516
4517 if (!port->init || port->link == 0) {
4518 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
4519 port->phy_interface);
4520 port->phy_dev = phy_dev;
4521 if (!phy_dev) {
4522 netdev_err(port->dev, "cannot connect to phy\n");
4523 return -ENODEV;
4524 }
4525 phy_dev->supported &= PHY_GBIT_FEATURES;
4526 phy_dev->advertising = phy_dev->supported;
4527
4528 port->phy_dev = phy_dev;
4529 port->link = 0;
4530 port->duplex = 0;
4531 port->speed = 0;
4532
4533 phy_config(phy_dev);
4534 phy_startup(phy_dev);
4535 if (!phy_dev->link) {
4536 printf("%s: No link\n", phy_dev->dev->name);
4537 return -1;
4538 }
4539
4540 port->init = 1;
4541 } else {
4542 mvpp2_egress_enable(port);
4543 mvpp2_ingress_enable(port);
4544 }
4545
4546 return 0;
4547}
4548
4549static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4550{
4551 unsigned char mac_bcast[ETH_ALEN] = {
4552 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4553 int err;
4554
4555 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4556 if (err) {
4557 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4558 return err;
4559 }
4560 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4561 port->dev_addr, true);
4562 if (err) {
4563 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4564 return err;
4565 }
4566 err = mvpp2_prs_def_flow(port);
4567 if (err) {
4568 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4569 return err;
4570 }
4571
4572 /* Allocate the Rx/Tx queues */
4573 err = mvpp2_setup_rxqs(port);
4574 if (err) {
4575 netdev_err(port->dev, "cannot allocate Rx queues\n");
4576 return err;
4577 }
4578
4579 err = mvpp2_setup_txqs(port);
4580 if (err) {
4581 netdev_err(port->dev, "cannot allocate Tx queues\n");
4582 return err;
4583 }
4584
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004585 if (port->phy_node) {
4586 err = mvpp2_phy_connect(dev, port);
4587 if (err < 0)
4588 return err;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004589
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004590 mvpp2_link_event(port);
4591 } else {
4592 mvpp2_egress_enable(port);
4593 mvpp2_ingress_enable(port);
4594 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004595
4596 mvpp2_start_dev(port);
4597
4598 return 0;
4599}
4600
4601/* No Device ops here in U-Boot */
4602
4603/* Driver initialization */
4604
4605static void mvpp2_port_power_up(struct mvpp2_port *port)
4606{
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004607 struct mvpp2 *priv = port->priv;
4608
Stefan Roese31aa1e32017-03-22 15:07:30 +01004609 /* On PPv2.2 the GoP / interface configuration has already been done */
4610 if (priv->hw_version == MVPP21)
4611 mvpp2_port_mii_set(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004612 mvpp2_port_periodic_xon_disable(port);
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004613 if (priv->hw_version == MVPP21)
4614 mvpp2_port_fc_adv_enable(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004615 mvpp2_port_reset(port);
4616}
4617
4618/* Initialize port HW */
4619static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4620{
4621 struct mvpp2 *priv = port->priv;
4622 struct mvpp2_txq_pcpu *txq_pcpu;
4623 int queue, cpu, err;
4624
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01004625 if (port->first_rxq + rxq_number >
4626 MVPP2_MAX_PORTS * priv->max_port_rxqs)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004627 return -EINVAL;
4628
4629 /* Disable port */
4630 mvpp2_egress_disable(port);
Stefan Roese31aa1e32017-03-22 15:07:30 +01004631 if (priv->hw_version == MVPP21)
4632 mvpp2_port_disable(port);
4633 else
4634 gop_port_enable(port, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004635
4636 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4637 GFP_KERNEL);
4638 if (!port->txqs)
4639 return -ENOMEM;
4640
4641 /* Associate physical Tx queues to this port and initialize.
4642 * The mapping is predefined.
4643 */
4644 for (queue = 0; queue < txq_number; queue++) {
4645 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4646 struct mvpp2_tx_queue *txq;
4647
4648 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4649 if (!txq)
4650 return -ENOMEM;
4651
4652 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4653 GFP_KERNEL);
4654 if (!txq->pcpu)
4655 return -ENOMEM;
4656
4657 txq->id = queue_phy_id;
4658 txq->log_id = queue;
4659 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4660 for_each_present_cpu(cpu) {
4661 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4662 txq_pcpu->cpu = cpu;
4663 }
4664
4665 port->txqs[queue] = txq;
4666 }
4667
4668 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4669 GFP_KERNEL);
4670 if (!port->rxqs)
4671 return -ENOMEM;
4672
4673 /* Allocate and initialize Rx queue for this port */
4674 for (queue = 0; queue < rxq_number; queue++) {
4675 struct mvpp2_rx_queue *rxq;
4676
4677 /* Map physical Rx queue to port's logical Rx queue */
4678 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4679 if (!rxq)
4680 return -ENOMEM;
4681 /* Map this Rx queue to a physical queue */
4682 rxq->id = port->first_rxq + queue;
4683 rxq->port = port->id;
4684 rxq->logic_rxq = queue;
4685
4686 port->rxqs[queue] = rxq;
4687 }
4688
4689 /* Configure Rx queue group interrupt for this port */
Thomas Petazzonibc0bbf42017-02-16 08:46:37 +01004690 if (priv->hw_version == MVPP21) {
4691 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4692 CONFIG_MV_ETH_RXQ);
4693 } else {
4694 u32 val;
4695
4696 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4697 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4698
4699 val = (CONFIG_MV_ETH_RXQ <<
4700 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4701 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4702 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004703
4704 /* Create Rx descriptor rings */
4705 for (queue = 0; queue < rxq_number; queue++) {
4706 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4707
4708 rxq->size = port->rx_ring_size;
4709 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4710 rxq->time_coal = MVPP2_RX_COAL_USEC;
4711 }
4712
4713 mvpp2_ingress_disable(port);
4714
4715 /* Port default configuration */
4716 mvpp2_defaults_set(port);
4717
4718 /* Port's classifier configuration */
4719 mvpp2_cls_oversize_rxq_set(port);
4720 mvpp2_cls_port_config(port);
4721
4722 /* Provide an initial Rx packet size */
4723 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4724
4725 /* Initialize pools for swf */
4726 err = mvpp2_swf_bm_pool_init(port);
4727 if (err)
4728 return err;
4729
4730 return 0;
4731}
4732
Stefan Roese66b11cc2017-03-22 14:11:16 +01004733static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004734{
Stefan Roese66b11cc2017-03-22 14:11:16 +01004735 int port_node = dev_of_offset(dev);
4736 const char *phy_mode_str;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004737 int phy_node;
4738 u32 id;
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004739 u32 phyaddr = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004740 int phy_mode = -1;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004741
4742 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004743
4744 if (phy_node > 0) {
4745 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4746 if (phyaddr < 0) {
4747 dev_err(&pdev->dev, "could not find phy address\n");
4748 return -1;
4749 }
4750 } else {
4751 phy_node = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004752 }
4753
4754 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4755 if (phy_mode_str)
4756 phy_mode = phy_get_interface_by_name(phy_mode_str);
4757 if (phy_mode == -1) {
4758 dev_err(&pdev->dev, "incorrect phy mode\n");
4759 return -EINVAL;
4760 }
4761
4762 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4763 if (id == -1) {
4764 dev_err(&pdev->dev, "missing port-id value\n");
4765 return -EINVAL;
4766 }
4767
Stefan Roese9acb7da2017-03-22 14:15:40 +01004768 /*
4769 * ToDo:
4770 * Not sure if this DT property "phy-speed" will get accepted, so
4771 * this might change later
4772 */
4773 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4774 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4775 "phy-speed", 1000);
4776
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004777 port->id = id;
Stefan Roese66b11cc2017-03-22 14:11:16 +01004778 if (port->priv->hw_version == MVPP21)
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01004779 port->first_rxq = port->id * rxq_number;
4780 else
Stefan Roese66b11cc2017-03-22 14:11:16 +01004781 port->first_rxq = port->id * port->priv->max_port_rxqs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004782 port->phy_node = phy_node;
4783 port->phy_interface = phy_mode;
4784 port->phyaddr = phyaddr;
4785
Stefan Roese66b11cc2017-03-22 14:11:16 +01004786 return 0;
4787}
Thomas Petazzoni26a52782017-02-16 08:03:37 +01004788
Stefan Roese66b11cc2017-03-22 14:11:16 +01004789/* Ports initialization */
4790static int mvpp2_port_probe(struct udevice *dev,
4791 struct mvpp2_port *port,
4792 int port_node,
4793 struct mvpp2 *priv)
4794{
4795 int err;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004796
4797 port->tx_ring_size = MVPP2_MAX_TXD;
4798 port->rx_ring_size = MVPP2_MAX_RXD;
4799
4800 err = mvpp2_port_init(dev, port);
4801 if (err < 0) {
Stefan Roese66b11cc2017-03-22 14:11:16 +01004802 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004803 return err;
4804 }
4805 mvpp2_port_power_up(port);
4806
Stefan Roese66b11cc2017-03-22 14:11:16 +01004807 priv->port_list[port->id] = port;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004808 return 0;
4809}
4810
4811/* Initialize decoding windows */
4812static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4813 struct mvpp2 *priv)
4814{
4815 u32 win_enable;
4816 int i;
4817
4818 for (i = 0; i < 6; i++) {
4819 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4820 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4821
4822 if (i < 4)
4823 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4824 }
4825
4826 win_enable = 0;
4827
4828 for (i = 0; i < dram->num_cs; i++) {
4829 const struct mbus_dram_window *cs = dram->cs + i;
4830
4831 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4832 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4833 dram->mbus_dram_target_id);
4834
4835 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4836 (cs->size - 1) & 0xffff0000);
4837
4838 win_enable |= (1 << i);
4839 }
4840
4841 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4842}
4843
4844/* Initialize Rx FIFO's */
4845static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4846{
4847 int port;
4848
4849 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
Stefan Roeseff572c62017-03-01 13:09:42 +01004850 if (priv->hw_version == MVPP22) {
4851 if (port == 0) {
4852 mvpp2_write(priv,
4853 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4854 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4855 mvpp2_write(priv,
4856 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4857 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4858 } else if (port == 1) {
4859 mvpp2_write(priv,
4860 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4861 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4862 mvpp2_write(priv,
4863 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4864 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4865 } else {
4866 mvpp2_write(priv,
4867 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4868 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4869 mvpp2_write(priv,
4870 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4871 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4872 }
4873 } else {
4874 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4875 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4876 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4877 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4878 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004879 }
4880
4881 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4882 MVPP2_RX_FIFO_PORT_MIN_PKT);
4883 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4884}
4885
Stefan Roeseff572c62017-03-01 13:09:42 +01004886/* Initialize Tx FIFO's */
4887static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4888{
4889 int port, val;
4890
4891 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4892 /* Port 0 supports 10KB TX FIFO */
4893 if (port == 0) {
4894 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4895 MVPP22_TX_FIFO_SIZE_MASK;
4896 } else {
4897 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4898 MVPP22_TX_FIFO_SIZE_MASK;
4899 }
4900 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4901 }
4902}
4903
Thomas Petazzonicdf77792017-02-16 08:41:07 +01004904static void mvpp2_axi_init(struct mvpp2 *priv)
4905{
4906 u32 val, rdval, wrval;
4907
4908 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4909
4910 /* AXI Bridge Configuration */
4911
4912 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4913 << MVPP22_AXI_ATTR_CACHE_OFFS;
4914 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4915 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4916
4917 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4918 << MVPP22_AXI_ATTR_CACHE_OFFS;
4919 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4920 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4921
4922 /* BM */
4923 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4924 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4925
4926 /* Descriptors */
4927 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4928 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4929 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4930 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4931
4932 /* Buffer Data */
4933 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4934 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4935
4936 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4937 << MVPP22_AXI_CODE_CACHE_OFFS;
4938 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4939 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4940 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4941 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4942
4943 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4944 << MVPP22_AXI_CODE_CACHE_OFFS;
4945 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4946 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4947
4948 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4949
4950 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4951 << MVPP22_AXI_CODE_CACHE_OFFS;
4952 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4953 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4954
4955 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4956}
4957
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004958/* Initialize network controller common part HW */
4959static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4960{
4961 const struct mbus_dram_target_info *dram_target_info;
4962 int err, i;
4963 u32 val;
4964
4965 /* Checks for hardware constraints (U-Boot uses only one rxq) */
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01004966 if ((rxq_number > priv->max_port_rxqs) ||
4967 (txq_number > MVPP2_MAX_TXQ)) {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004968 dev_err(&pdev->dev, "invalid queue size parameter\n");
4969 return -EINVAL;
4970 }
4971
4972 /* MBUS windows configuration */
4973 dram_target_info = mvebu_mbus_dram_info();
4974 if (dram_target_info)
4975 mvpp2_conf_mbus_windows(dram_target_info, priv);
4976
Thomas Petazzonicdf77792017-02-16 08:41:07 +01004977 if (priv->hw_version == MVPP22)
4978 mvpp2_axi_init(priv);
4979
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004980 if (priv->hw_version == MVPP21) {
Stefan Roese3e3cbb42017-03-09 12:01:57 +01004981 /* Disable HW PHY polling */
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004982 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4983 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4984 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4985 } else {
Stefan Roese3e3cbb42017-03-09 12:01:57 +01004986 /* Enable HW PHY polling */
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004987 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
Stefan Roese3e3cbb42017-03-09 12:01:57 +01004988 val |= MVPP22_SMI_POLLING_EN;
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004989 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4990 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004991
4992 /* Allocate and initialize aggregated TXQs */
4993 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4994 sizeof(struct mvpp2_tx_queue),
4995 GFP_KERNEL);
4996 if (!priv->aggr_txqs)
4997 return -ENOMEM;
4998
4999 for_each_present_cpu(i) {
5000 priv->aggr_txqs[i].id = i;
5001 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5002 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5003 MVPP2_AGGR_TXQ_SIZE, i, priv);
5004 if (err < 0)
5005 return err;
5006 }
5007
5008 /* Rx Fifo Init */
5009 mvpp2_rx_fifo_init(priv);
5010
Stefan Roeseff572c62017-03-01 13:09:42 +01005011 /* Tx Fifo Init */
5012 if (priv->hw_version == MVPP22)
5013 mvpp2_tx_fifo_init(priv);
5014
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005015 /* Reset Rx queue group interrupt configuration */
Thomas Petazzonibc0bbf42017-02-16 08:46:37 +01005016 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
5017 if (priv->hw_version == MVPP21) {
5018 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
5019 CONFIG_MV_ETH_RXQ);
5020 continue;
5021 } else {
5022 u32 val;
5023
5024 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
5025 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5026
5027 val = (CONFIG_MV_ETH_RXQ <<
5028 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
5029 mvpp2_write(priv,
5030 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5031 }
5032 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005033
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005034 if (priv->hw_version == MVPP21)
5035 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5036 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005037
5038 /* Allow cache snoop when transmiting packets */
5039 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5040
5041 /* Buffer Manager initialization */
5042 err = mvpp2_bm_init(dev, priv);
5043 if (err < 0)
5044 return err;
5045
5046 /* Parser default initialization */
5047 err = mvpp2_prs_default_init(dev, priv);
5048 if (err < 0)
5049 return err;
5050
5051 /* Classifier default initialization */
5052 mvpp2_cls_init(priv);
5053
5054 return 0;
5055}
5056
5057/* SMI / MDIO functions */
5058
5059static int smi_wait_ready(struct mvpp2 *priv)
5060{
5061 u32 timeout = MVPP2_SMI_TIMEOUT;
5062 u32 smi_reg;
5063
5064 /* wait till the SMI is not busy */
5065 do {
5066 /* read smi register */
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005067 smi_reg = readl(priv->mdio_base);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005068 if (timeout-- == 0) {
5069 printf("Error: SMI busy timeout\n");
5070 return -EFAULT;
5071 }
5072 } while (smi_reg & MVPP2_SMI_BUSY);
5073
5074 return 0;
5075}
5076
5077/*
5078 * mpp2_mdio_read - miiphy_read callback function.
5079 *
5080 * Returns 16bit phy register value, or 0xffff on error
5081 */
5082static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
5083{
5084 struct mvpp2 *priv = bus->priv;
5085 u32 smi_reg;
5086 u32 timeout;
5087
5088 /* check parameters */
5089 if (addr > MVPP2_PHY_ADDR_MASK) {
5090 printf("Error: Invalid PHY address %d\n", addr);
5091 return -EFAULT;
5092 }
5093
5094 if (reg > MVPP2_PHY_REG_MASK) {
5095 printf("Err: Invalid register offset %d\n", reg);
5096 return -EFAULT;
5097 }
5098
5099 /* wait till the SMI is not busy */
5100 if (smi_wait_ready(priv) < 0)
5101 return -EFAULT;
5102
5103 /* fill the phy address and regiser offset and read opcode */
5104 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5105 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
5106 | MVPP2_SMI_OPCODE_READ;
5107
5108 /* write the smi register */
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005109 writel(smi_reg, priv->mdio_base);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005110
5111 /* wait till read value is ready */
5112 timeout = MVPP2_SMI_TIMEOUT;
5113
5114 do {
5115 /* read smi register */
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005116 smi_reg = readl(priv->mdio_base);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005117 if (timeout-- == 0) {
5118 printf("Err: SMI read ready timeout\n");
5119 return -EFAULT;
5120 }
5121 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
5122
5123 /* Wait for the data to update in the SMI register */
5124 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
5125 ;
5126
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005127 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005128}
5129
5130/*
5131 * mpp2_mdio_write - miiphy_write callback function.
5132 *
5133 * Returns 0 if write succeed, -EINVAL on bad parameters
5134 * -ETIME on timeout
5135 */
5136static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
5137 u16 value)
5138{
5139 struct mvpp2 *priv = bus->priv;
5140 u32 smi_reg;
5141
5142 /* check parameters */
5143 if (addr > MVPP2_PHY_ADDR_MASK) {
5144 printf("Error: Invalid PHY address %d\n", addr);
5145 return -EFAULT;
5146 }
5147
5148 if (reg > MVPP2_PHY_REG_MASK) {
5149 printf("Err: Invalid register offset %d\n", reg);
5150 return -EFAULT;
5151 }
5152
5153 /* wait till the SMI is not busy */
5154 if (smi_wait_ready(priv) < 0)
5155 return -EFAULT;
5156
5157 /* fill the phy addr and reg offset and write opcode and data */
5158 smi_reg = value << MVPP2_SMI_DATA_OFFS;
5159 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5160 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
5161 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
5162
5163 /* write the smi register */
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005164 writel(smi_reg, priv->mdio_base);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005165
5166 return 0;
5167}
5168
5169static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5170{
5171 struct mvpp2_port *port = dev_get_priv(dev);
5172 struct mvpp2_rx_desc *rx_desc;
5173 struct mvpp2_bm_pool *bm_pool;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005174 dma_addr_t dma_addr;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005175 u32 bm, rx_status;
5176 int pool, rx_bytes, err;
5177 int rx_received;
5178 struct mvpp2_rx_queue *rxq;
5179 u32 cause_rx_tx, cause_rx, cause_misc;
5180 u8 *data;
5181
5182 cause_rx_tx = mvpp2_read(port->priv,
5183 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5184 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5185 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5186 if (!cause_rx_tx && !cause_misc)
5187 return 0;
5188
5189 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5190
5191 /* Process RX packets */
5192 cause_rx |= port->pending_cause_rx;
5193 rxq = mvpp2_get_rx_queue(port, cause_rx);
5194
5195 /* Get number of received packets and clamp the to-do */
5196 rx_received = mvpp2_rxq_received(port, rxq->id);
5197
5198 /* Return if no packets are received */
5199 if (!rx_received)
5200 return 0;
5201
5202 rx_desc = mvpp2_rxq_next_desc_get(rxq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005203 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5204 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5205 rx_bytes -= MVPP2_MH_SIZE;
5206 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005207
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005208 bm = mvpp2_bm_cookie_build(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005209 pool = mvpp2_bm_cookie_pool_get(bm);
5210 bm_pool = &port->priv->bm_pools[pool];
5211
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005212 /* In case of an error, release the requested buffer pointer
5213 * to the Buffer Manager. This request process is controlled
5214 * by the hardware, and the information about the buffer is
5215 * comprised by the RX descriptor.
5216 */
5217 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5218 mvpp2_rx_error(port, rx_desc);
5219 /* Return the buffer to the pool */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005220 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005221 return 0;
5222 }
5223
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005224 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005225 if (err) {
5226 netdev_err(port->dev, "failed to refill BM pools\n");
5227 return 0;
5228 }
5229
5230 /* Update Rx queue management counters */
5231 mb();
5232 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5233
5234 /* give packet to stack - skip on first n bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005235 data = (u8 *)dma_addr + 2 + 32;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005236
5237 if (rx_bytes <= 0)
5238 return 0;
5239
5240 /*
5241 * No cache invalidation needed here, since the rx_buffer's are
5242 * located in a uncached memory region
5243 */
5244 *packetp = data;
5245
5246 return rx_bytes;
5247}
5248
5249/* Drain Txq */
5250static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
5251 int enable)
5252{
5253 u32 val;
5254
5255 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5256 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
5257 if (enable)
5258 val |= MVPP2_TXQ_DRAIN_EN_MASK;
5259 else
5260 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
5261 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
5262}
5263
5264static int mvpp2_send(struct udevice *dev, void *packet, int length)
5265{
5266 struct mvpp2_port *port = dev_get_priv(dev);
5267 struct mvpp2_tx_queue *txq, *aggr_txq;
5268 struct mvpp2_tx_desc *tx_desc;
5269 int tx_done;
5270 int timeout;
5271
5272 txq = port->txqs[0];
5273 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5274
5275 /* Get a descriptor for the first part of the packet */
5276 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005277 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5278 mvpp2_txdesc_size_set(port, tx_desc, length);
5279 mvpp2_txdesc_offset_set(port, tx_desc,
5280 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5281 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5282 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005283 /* First and Last descriptor */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005284 mvpp2_txdesc_cmd_set(port, tx_desc,
5285 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5286 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005287
5288 /* Flush tx data */
Stefan Roesef811e042017-02-16 13:58:37 +01005289 flush_dcache_range((unsigned long)packet,
5290 (unsigned long)packet + ALIGN(length, PKTALIGN));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005291
5292 /* Enable transmit */
5293 mb();
5294 mvpp2_aggr_txq_pend_desc_add(port, 1);
5295
5296 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5297
5298 timeout = 0;
5299 do {
5300 if (timeout++ > 10000) {
5301 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5302 return 0;
5303 }
5304 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5305 } while (tx_done);
5306
5307 /* Enable TXQ drain */
5308 mvpp2_txq_drain(port, txq, 1);
5309
5310 timeout = 0;
5311 do {
5312 if (timeout++ > 10000) {
5313 printf("timeout: packet not sent\n");
5314 return 0;
5315 }
5316 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5317 } while (!tx_done);
5318
5319 /* Disable TXQ drain */
5320 mvpp2_txq_drain(port, txq, 0);
5321
5322 return 0;
5323}
5324
5325static int mvpp2_start(struct udevice *dev)
5326{
5327 struct eth_pdata *pdata = dev_get_platdata(dev);
5328 struct mvpp2_port *port = dev_get_priv(dev);
5329
5330 /* Load current MAC address */
5331 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5332
5333 /* Reconfigure parser accept the original MAC address */
5334 mvpp2_prs_update_mac_da(port, port->dev_addr);
5335
Stefan Chulskie09d0c82017-04-06 15:39:08 +02005336 switch (port->phy_interface) {
5337 case PHY_INTERFACE_MODE_RGMII:
5338 case PHY_INTERFACE_MODE_RGMII_ID:
5339 case PHY_INTERFACE_MODE_SGMII:
5340 mvpp2_port_power_up(port);
5341 default:
5342 break;
5343 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005344
5345 mvpp2_open(dev, port);
5346
5347 return 0;
5348}
5349
5350static void mvpp2_stop(struct udevice *dev)
5351{
5352 struct mvpp2_port *port = dev_get_priv(dev);
5353
5354 mvpp2_stop_dev(port);
5355 mvpp2_cleanup_rxqs(port);
5356 mvpp2_cleanup_txqs(port);
5357}
5358
Stefan Roesefb640722017-03-10 06:07:45 +01005359static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5360{
5361 writel(port->phyaddr, port->priv->iface_base +
5362 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5363
5364 return 0;
5365}
5366
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005367static int mvpp2_base_probe(struct udevice *dev)
5368{
5369 struct mvpp2 *priv = dev_get_priv(dev);
5370 struct mii_dev *bus;
5371 void *bd_space;
5372 u32 size = 0;
5373 int i;
5374
Thomas Petazzoni16a98982017-02-15 14:08:59 +01005375 /* Save hw-version */
5376 priv->hw_version = dev_get_driver_data(dev);
5377
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005378 /*
5379 * U-Boot special buffer handling:
5380 *
5381 * Allocate buffer area for descs and rx_buffers. This is only
5382 * done once for all interfaces. As only one interface can
5383 * be active. Make this area DMA-safe by disabling the D-cache
5384 */
5385
5386 /* Align buffer area for descs and rx_buffers to 1MiB */
5387 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Stefan Roesea7c28ff2017-02-15 12:46:18 +01005388 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5389 BD_SPACE, DCACHE_OFF);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005390
5391 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5392 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5393
Stefan Roesea7c28ff2017-02-15 12:46:18 +01005394 buffer_loc.tx_descs =
5395 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005396 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5397
Stefan Roesea7c28ff2017-02-15 12:46:18 +01005398 buffer_loc.rx_descs =
5399 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005400 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5401
5402 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
Stefan Roesea7c28ff2017-02-15 12:46:18 +01005403 buffer_loc.bm_pool[i] =
5404 (unsigned long *)((unsigned long)bd_space + size);
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01005405 if (priv->hw_version == MVPP21)
5406 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5407 else
5408 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005409 }
5410
5411 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
Stefan Roesea7c28ff2017-02-15 12:46:18 +01005412 buffer_loc.rx_buffer[i] =
5413 (unsigned long *)((unsigned long)bd_space + size);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005414 size += RX_BUFFER_SIZE;
5415 }
5416
Stefan Roese30edc372017-02-16 13:29:08 +01005417 /* Clear the complete area so that all descriptors are cleared */
5418 memset(bd_space, 0, size);
5419
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005420 /* Save base addresses for later use */
Simon Glassa821c4a2017-05-17 17:18:05 -06005421 priv->base = (void *)devfdt_get_addr_index(dev, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005422 if (IS_ERR(priv->base))
5423 return PTR_ERR(priv->base);
5424
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005425 if (priv->hw_version == MVPP21) {
Simon Glassa821c4a2017-05-17 17:18:05 -06005426 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005427 if (IS_ERR(priv->lms_base))
5428 return PTR_ERR(priv->lms_base);
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005429
5430 priv->mdio_base = priv->lms_base + MVPP21_SMI;
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005431 } else {
Simon Glassa821c4a2017-05-17 17:18:05 -06005432 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005433 if (IS_ERR(priv->iface_base))
5434 return PTR_ERR(priv->iface_base);
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005435
5436 priv->mdio_base = priv->iface_base + MVPP22_SMI;
Stefan Roese31aa1e32017-03-22 15:07:30 +01005437
5438 /* Store common base addresses for all ports */
5439 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5440 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5441 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005442 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005443
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01005444 if (priv->hw_version == MVPP21)
5445 priv->max_port_rxqs = 8;
5446 else
5447 priv->max_port_rxqs = 32;
5448
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005449 /* Finally create and register the MDIO bus driver */
5450 bus = mdio_alloc();
5451 if (!bus) {
5452 printf("Failed to allocate MDIO bus\n");
5453 return -ENOMEM;
5454 }
5455
5456 bus->read = mpp2_mdio_read;
5457 bus->write = mpp2_mdio_write;
5458 snprintf(bus->name, sizeof(bus->name), dev->name);
5459 bus->priv = (void *)priv;
5460 priv->bus = bus;
5461
5462 return mdio_register(bus);
5463}
5464
Stefan Roese1fabbd02017-02-16 15:26:06 +01005465static int mvpp2_probe(struct udevice *dev)
5466{
5467 struct mvpp2_port *port = dev_get_priv(dev);
5468 struct mvpp2 *priv = dev_get_priv(dev->parent);
5469 int err;
5470
5471 /* Only call the probe function for the parent once */
5472 if (!priv->probe_done) {
5473 err = mvpp2_base_probe(dev->parent);
5474 priv->probe_done = 1;
5475 }
Stefan Roese66b11cc2017-03-22 14:11:16 +01005476
5477 port->priv = dev_get_priv(dev->parent);
5478
5479 err = phy_info_parse(dev, port);
5480 if (err)
5481 return err;
5482
5483 /*
5484 * We need the port specific io base addresses at this stage, since
5485 * gop_port_init() accesses these registers
5486 */
5487 if (priv->hw_version == MVPP21) {
5488 int priv_common_regs_num = 2;
5489
Simon Glassa821c4a2017-05-17 17:18:05 -06005490 port->base = (void __iomem *)devfdt_get_addr_index(
Stefan Roese66b11cc2017-03-22 14:11:16 +01005491 dev->parent, priv_common_regs_num + port->id);
5492 if (IS_ERR(port->base))
5493 return PTR_ERR(port->base);
5494 } else {
5495 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5496 "gop-port-id", -1);
5497 if (port->id == -1) {
5498 dev_err(&pdev->dev, "missing gop-port-id value\n");
5499 return -EINVAL;
5500 }
5501
5502 port->base = priv->iface_base + MVPP22_PORT_BASE +
5503 port->gop_id * MVPP22_PORT_OFFSET;
Stefan Roese31aa1e32017-03-22 15:07:30 +01005504
Stefan Roesefb640722017-03-10 06:07:45 +01005505 /* Set phy address of the port */
Stefan Chulskie09d0c82017-04-06 15:39:08 +02005506 if(port->phy_node)
5507 mvpp22_smi_phy_addr_cfg(port);
Stefan Roesefb640722017-03-10 06:07:45 +01005508
Stefan Roese31aa1e32017-03-22 15:07:30 +01005509 /* GoP Init */
5510 gop_port_init(port);
Stefan Roese66b11cc2017-03-22 14:11:16 +01005511 }
5512
Stefan Roese1fabbd02017-02-16 15:26:06 +01005513 /* Initialize network controller */
5514 err = mvpp2_init(dev, priv);
5515 if (err < 0) {
5516 dev_err(&pdev->dev, "failed to initialize controller\n");
5517 return err;
5518 }
5519
Stefan Roese31aa1e32017-03-22 15:07:30 +01005520 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5521 if (err)
5522 return err;
5523
5524 if (priv->hw_version == MVPP22) {
5525 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5526 port->phy_interface);
5527
5528 /* Netcomplex configurations for all ports */
5529 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5530 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5531 }
5532
5533 return 0;
Stefan Roese1fabbd02017-02-16 15:26:06 +01005534}
5535
Stefan Roese2f720f12017-03-23 17:01:59 +01005536/*
5537 * Empty BM pool and stop its activity before the OS is started
5538 */
5539static int mvpp2_remove(struct udevice *dev)
5540{
5541 struct mvpp2_port *port = dev_get_priv(dev);
5542 struct mvpp2 *priv = port->priv;
5543 int i;
5544
5545 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5546 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5547
5548 return 0;
5549}
5550
Stefan Roese1fabbd02017-02-16 15:26:06 +01005551static const struct eth_ops mvpp2_ops = {
5552 .start = mvpp2_start,
5553 .send = mvpp2_send,
5554 .recv = mvpp2_recv,
5555 .stop = mvpp2_stop,
5556};
5557
5558static struct driver mvpp2_driver = {
5559 .name = "mvpp2",
5560 .id = UCLASS_ETH,
5561 .probe = mvpp2_probe,
Stefan Roese2f720f12017-03-23 17:01:59 +01005562 .remove = mvpp2_remove,
Stefan Roese1fabbd02017-02-16 15:26:06 +01005563 .ops = &mvpp2_ops,
5564 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5565 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
Stefan Roese2f720f12017-03-23 17:01:59 +01005566 .flags = DM_FLAG_ACTIVE_DMA,
Stefan Roese1fabbd02017-02-16 15:26:06 +01005567};
5568
5569/*
5570 * Use a MISC device to bind the n instances (child nodes) of the
5571 * network base controller in UCLASS_ETH.
5572 */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005573static int mvpp2_base_bind(struct udevice *parent)
5574{
5575 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -07005576 int node = dev_of_offset(parent);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005577 struct uclass_driver *drv;
5578 struct udevice *dev;
5579 struct eth_pdata *plat;
5580 char *name;
5581 int subnode;
5582 u32 id;
Stefan Roesec9607c92017-02-24 10:12:41 +01005583 int base_id_add;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005584
5585 /* Lookup eth driver */
5586 drv = lists_uclass_lookup(UCLASS_ETH);
5587 if (!drv) {
5588 puts("Cannot find eth driver\n");
5589 return -ENOENT;
5590 }
5591
Stefan Roesec9607c92017-02-24 10:12:41 +01005592 base_id_add = base_id;
5593
Simon Glassdf87e6b2016-10-02 17:59:29 -06005594 fdt_for_each_subnode(subnode, blob, node) {
Stefan Roesec9607c92017-02-24 10:12:41 +01005595 /* Increment base_id for all subnodes, also the disabled ones */
5596 base_id++;
5597
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005598 /* Skip disabled ports */
5599 if (!fdtdec_get_is_enabled(blob, subnode))
5600 continue;
5601
5602 plat = calloc(1, sizeof(*plat));
5603 if (!plat)
5604 return -ENOMEM;
5605
5606 id = fdtdec_get_int(blob, subnode, "port-id", -1);
Stefan Roesec9607c92017-02-24 10:12:41 +01005607 id += base_id_add;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005608
5609 name = calloc(1, 16);
5610 sprintf(name, "mvpp2-%d", id);
5611
5612 /* Create child device UCLASS_ETH and bind it */
5613 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
Simon Glasse160f7d2017-01-17 16:52:55 -07005614 dev_set_of_offset(dev, subnode);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005615 }
5616
5617 return 0;
5618}
5619
5620static const struct udevice_id mvpp2_ids[] = {
Thomas Petazzoni16a98982017-02-15 14:08:59 +01005621 {
5622 .compatible = "marvell,armada-375-pp2",
5623 .data = MVPP21,
5624 },
Thomas Petazzonia83a6412017-02-20 11:54:31 +01005625 {
5626 .compatible = "marvell,armada-7k-pp22",
5627 .data = MVPP22,
5628 },
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005629 { }
5630};
5631
5632U_BOOT_DRIVER(mvpp2_base) = {
5633 .name = "mvpp2_base",
5634 .id = UCLASS_MISC,
5635 .of_match = mvpp2_ids,
5636 .bind = mvpp2_base_bind,
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005637 .priv_auto_alloc_size = sizeof(struct mvpp2),
5638};