wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * File: scc.c |
| 3 | * Description: |
| 4 | * Basic ET HW initialization and packet RX/TX routines |
| 5 | * |
| 6 | * NOTE <<<IMPORTANT: PLEASE READ>>>: |
| 7 | * Do not cache Rx/Tx buffers! |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * MPC823 <-> MC68160 Connections: |
| 12 | * |
| 13 | * Setup MPC823 to work with MC68160 Enhanced Ethernet |
| 14 | * Serial Tranceiver as follows: |
| 15 | * |
| 16 | * MPC823 Signal MC68160 Comments |
| 17 | * ------ ------ ------- -------- |
| 18 | * PA-12 ETHTX --------> TX Eth. Port Transmit Data |
| 19 | * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable |
| 20 | * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock |
| 21 | * PA-13 ETHRX <-------- RX Eth. Port Receive Data |
| 22 | * PC-8 E_RENA <-------- RENA Eth. Receive Enable |
| 23 | * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock |
| 24 | * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication |
| 25 | * |
| 26 | * FADS Board Signal MC68160 Comments |
| 27 | * ----------------- ------- -------- |
| 28 | * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable |
| 29 | * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable |
| 30 | * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex |
| 31 | * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <common.h> |
| 36 | #include <malloc.h> |
| 37 | #include <commproc.h> |
| 38 | #include <net.h> |
| 39 | #include <command.h> |
| 40 | |
| 41 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET) |
| 42 | |
| 43 | /* Ethernet Transmit and Receive Buffers */ |
| 44 | #define DBUF_LENGTH 1520 |
| 45 | |
| 46 | #define TX_BUF_CNT 2 |
| 47 | |
| 48 | #define TOUT_LOOP 100 |
| 49 | |
| 50 | static char txbuf[DBUF_LENGTH]; |
| 51 | |
| 52 | static uint rxIdx; /* index of the current RX buffer */ |
| 53 | static uint txIdx; /* index of the current TX buffer */ |
| 54 | |
| 55 | /* |
| 56 | * SCC Ethernet Tx and Rx buffer descriptors allocated at the |
| 57 | * immr->udata_bd address on Dual-Port RAM |
| 58 | * Provide for Double Buffering |
| 59 | */ |
| 60 | |
| 61 | typedef volatile struct CommonBufferDescriptor { |
| 62 | cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ |
| 63 | cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ |
| 64 | } RTXBD; |
| 65 | |
| 66 | static RTXBD *rtx; |
| 67 | |
| 68 | static int scc_send(struct eth_device* dev, volatile void *packet, int length); |
| 69 | static int scc_recv(struct eth_device* dev); |
| 70 | static int scc_init (struct eth_device* dev, bd_t * bd); |
| 71 | static void scc_halt(struct eth_device* dev); |
| 72 | |
| 73 | int scc_initialize(bd_t *bis) |
| 74 | { |
| 75 | struct eth_device* dev; |
| 76 | |
| 77 | dev = (struct eth_device*) malloc(sizeof *dev); |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 78 | memset(dev, 0, sizeof *dev); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 79 | |
| 80 | sprintf(dev->name, "SCC ETHERNET"); |
| 81 | dev->iobase = 0; |
| 82 | dev->priv = 0; |
| 83 | dev->init = scc_init; |
| 84 | dev->halt = scc_halt; |
| 85 | dev->send = scc_send; |
| 86 | dev->recv = scc_recv; |
| 87 | |
| 88 | eth_register(dev); |
| 89 | |
| 90 | return 1; |
| 91 | } |
| 92 | |
| 93 | static int scc_send(struct eth_device* dev, volatile void *packet, int length) |
| 94 | { |
| 95 | int i, j=0; |
| 96 | #if 0 |
| 97 | volatile char *in, *out; |
| 98 | #endif |
| 99 | |
| 100 | /* section 16.9.23.3 |
| 101 | * Wait for ready |
| 102 | */ |
| 103 | #if 0 |
| 104 | while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); |
| 105 | out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); |
| 106 | in = packet; |
| 107 | for(i = 0; i < length; i++) { |
| 108 | *out++ = *in++; |
| 109 | } |
| 110 | rtx->txbd[txIdx].cbd_datlen = length; |
| 111 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); |
| 112 | while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; |
| 113 | |
| 114 | #ifdef ET_DEBUG |
| 115 | printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); |
| 116 | #endif |
| 117 | i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; |
| 118 | |
| 119 | /* wrap around buffer index when necessary */ |
| 120 | if (txIdx >= TX_BUF_CNT) txIdx = 0; |
| 121 | #endif |
| 122 | |
| 123 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { |
| 124 | udelay (1); /* will also trigger Wd if needed */ |
| 125 | j++; |
| 126 | } |
| 127 | if (j>=TOUT_LOOP) printf("TX not ready\n"); |
| 128 | rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; |
| 129 | rtx->txbd[txIdx].cbd_datlen = length; |
| 130 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); |
| 131 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { |
| 132 | udelay (1); /* will also trigger Wd if needed */ |
| 133 | j++; |
| 134 | } |
| 135 | if (j>=TOUT_LOOP) printf("TX timeout\n"); |
| 136 | #ifdef ET_DEBUG |
| 137 | printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); |
| 138 | #endif |
| 139 | i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; |
| 140 | return i; |
| 141 | } |
| 142 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 143 | static int scc_recv (struct eth_device *dev) |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 144 | { |
| 145 | int length; |
| 146 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 147 | for (;;) { |
| 148 | /* section 16.9.23.2 */ |
| 149 | if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { |
| 150 | length = -1; |
| 151 | break; /* nothing received - leave for() loop */ |
| 152 | } |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 153 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 154 | length = rtx->rxbd[rxIdx].cbd_datlen; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 155 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 156 | if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 157 | #ifdef ET_DEBUG |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 158 | printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 159 | #endif |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 160 | } else { |
| 161 | /* Pass the packet up to the protocol layers. */ |
| 162 | NetReceive (NetRxPackets[rxIdx], length - 4); |
| 163 | } |
| 164 | |
| 165 | |
| 166 | /* Give the buffer back to the SCC. */ |
| 167 | rtx->rxbd[rxIdx].cbd_datlen = 0; |
| 168 | |
| 169 | /* wrap around buffer index when necessary */ |
| 170 | if ((rxIdx + 1) >= PKTBUFSRX) { |
| 171 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc = |
| 172 | (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); |
| 173 | rxIdx = 0; |
| 174 | } else { |
| 175 | rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; |
| 176 | rxIdx++; |
| 177 | } |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 178 | } |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 179 | return length; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | /************************************************************** |
| 183 | * |
| 184 | * SCC Ethernet Initialization Routine |
| 185 | * |
| 186 | *************************************************************/ |
| 187 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 188 | static int scc_init (struct eth_device *dev, bd_t * bis) |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 189 | { |
| 190 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 191 | int i; |
| 192 | scc_enet_t *pram_ptr; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 193 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 194 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 195 | |
wdenk | 2535d60 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 196 | #ifdef CONFIG_FADS |
| 197 | #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 198 | /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ |
| 199 | *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; |
| 200 | *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; |
| 201 | *((uint *) BCSR1) &= ~BCSR1_ETHEN; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 202 | #else |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 203 | *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); |
| 204 | *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; |
| 205 | *((uint *) BCSR1) &= ~BCSR1_ETHEN; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 206 | #endif |
| 207 | #endif |
| 208 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 209 | pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 210 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 211 | rxIdx = 0; |
| 212 | txIdx = 0; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 213 | |
| 214 | #ifdef CFG_ALLOC_DPRAM |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 215 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + |
| 216 | dpram_alloc_align (sizeof (RTXBD), 8)); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 217 | #else |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 218 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); |
| 219 | #endif /* 0 */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 220 | |
| 221 | #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 222 | /* Configure port A pins for Txd and Rxd. |
| 223 | */ |
| 224 | immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); |
| 225 | immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); |
| 226 | immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 227 | #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 228 | /* Configure port B pins for Txd and Rxd. |
| 229 | */ |
| 230 | immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); |
| 231 | immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); |
| 232 | immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 233 | #else |
| 234 | #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined |
| 235 | #endif |
| 236 | |
| 237 | #if defined(PC_ENET_LBK) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 238 | /* Configure port C pins to disable External Loopback |
| 239 | */ |
| 240 | immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; |
| 241 | immr->im_ioport.iop_pcdir |= PC_ENET_LBK; |
| 242 | immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; |
| 243 | immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ |
| 244 | #endif /* PC_ENET_LBK */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 245 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 246 | /* Configure port C pins to enable CLSN and RENA. |
| 247 | */ |
| 248 | immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); |
| 249 | immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); |
| 250 | immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 251 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 252 | /* Configure port A for TCLK and RCLK. |
| 253 | */ |
| 254 | immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); |
| 255 | immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 256 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 257 | /* |
| 258 | * Configure Serial Interface clock routing -- see section 16.7.5.3 |
| 259 | * First, clear all SCC bits to zero, then set the ones we want. |
| 260 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 261 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 262 | immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; |
| 263 | immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 264 | |
| 265 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 266 | /* |
| 267 | * Initialize SDCR -- see section 16.9.23.7 |
| 268 | * SDMA configuration register |
| 269 | */ |
| 270 | immr->im_siu_conf.sc_sdcr = 0x01; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 271 | |
| 272 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 273 | /* |
| 274 | * Setup SCC Ethernet Parameter RAM |
| 275 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 276 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 277 | pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ |
| 278 | pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 279 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 280 | pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 281 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 282 | pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ |
| 283 | pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 284 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 285 | /* |
| 286 | * Setup Receiver Buffer Descriptors (13.14.24.18) |
| 287 | * Settings: |
| 288 | * Empty, Wrap |
| 289 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 290 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 291 | for (i = 0; i < PKTBUFSRX; i++) { |
| 292 | rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
| 293 | rtx->rxbd[i].cbd_datlen = 0; /* Reset */ |
| 294 | rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; |
| 295 | } |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 296 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 297 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 298 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 299 | /* |
| 300 | * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) |
| 301 | * Settings: |
| 302 | * Add PADs to Short FRAMES, Wrap, Last, Tx CRC |
| 303 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 304 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 305 | for (i = 0; i < TX_BUF_CNT; i++) { |
| 306 | rtx->txbd[i].cbd_sc = |
| 307 | (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
| 308 | rtx->txbd[i].cbd_datlen = 0; /* Reset */ |
| 309 | rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); |
| 310 | } |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 311 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 312 | rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 313 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 314 | /* |
| 315 | * Enter Command: Initialize Rx Params for SCC |
| 316 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 317 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 318 | do { /* Spin until ready to issue command */ |
| 319 | __asm__ ("eieio"); |
| 320 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); |
| 321 | /* Issue command */ |
| 322 | immr->im_cpm.cp_cpcr = |
| 323 | ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); |
| 324 | do { /* Spin until command processed */ |
| 325 | __asm__ ("eieio"); |
| 326 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 327 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 328 | /* |
| 329 | * Ethernet Specific Parameter RAM |
| 330 | * see table 13-16, pg. 660, |
| 331 | * pg. 681 (example with suggested settings) |
| 332 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 333 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 334 | pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ |
| 335 | pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ |
| 336 | pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ |
| 337 | pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ |
| 338 | pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ |
| 339 | pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 340 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 341 | pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ |
| 342 | pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ |
| 343 | pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 344 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 345 | pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ |
| 346 | pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 347 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 348 | pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ |
| 349 | pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ |
| 350 | pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ |
| 351 | pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 352 | |
| 353 | #define ea eth_get_dev()->enetaddr |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 354 | pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; |
| 355 | pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; |
| 356 | pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 357 | #undef ea |
| 358 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 359 | pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ |
| 360 | pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ |
| 361 | pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ |
| 362 | pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ |
| 363 | pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ |
| 364 | pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ |
| 365 | pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ |
| 366 | pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 367 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 368 | /* |
| 369 | * Enter Command: Initialize Tx Params for SCC |
| 370 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 371 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 372 | do { /* Spin until ready to issue command */ |
| 373 | __asm__ ("eieio"); |
| 374 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); |
| 375 | /* Issue command */ |
| 376 | immr->im_cpm.cp_cpcr = |
| 377 | ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); |
| 378 | do { /* Spin until command processed */ |
| 379 | __asm__ ("eieio"); |
| 380 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 381 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 382 | /* |
| 383 | * Mask all Events in SCCM - we use polling mode |
| 384 | */ |
| 385 | immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 386 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 387 | /* |
| 388 | * Clear Events in SCCE -- Clear bits by writing 1's |
| 389 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 390 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 391 | immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 392 | |
| 393 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 394 | /* |
| 395 | * Initialize GSMR High 32-Bits |
| 396 | * Settings: Normal Mode |
| 397 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 398 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 399 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 400 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 401 | /* |
| 402 | * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive |
| 403 | * Settings: |
| 404 | * TCI = Invert |
| 405 | * TPL = 48 bits |
| 406 | * TPP = Repeating 10's |
| 407 | * MODE = Ethernet |
| 408 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 409 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 410 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | |
| 411 | SCC_GSMRL_TPL_48 | |
| 412 | SCC_GSMRL_TPP_10 | |
| 413 | SCC_GSMRL_MODE_ENET); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 414 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 415 | /* |
| 416 | * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 |
| 417 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 418 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 419 | immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 420 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 421 | /* |
| 422 | * Initialize the PSMR |
| 423 | * Settings: |
| 424 | * CRC = 32-Bit CCITT |
| 425 | * NIB = Begin searching for SFD 22 bits after RENA |
| 426 | * FDE = Full Duplex Enable |
| 427 | * LPB = Loopback Enable (Needed when FDE is set) |
| 428 | * BRO = Reject broadcast packets |
| 429 | * PROMISCOUS = Catch all packets regardless of dest. MAC adress |
| 430 | */ |
| 431 | immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | |
| 432 | SCC_PSMR_NIB22 | |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 433 | #if defined(CONFIG_SCC_ENET_FULL_DUPLEX) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 434 | SCC_PSMR_FDE | SCC_PSMR_LPB | |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 435 | #endif |
| 436 | #if defined(CONFIG_SCC_ENET_NO_BROADCAST) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 437 | SCC_PSMR_BRO | |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 438 | #endif |
| 439 | #if defined(CONFIG_SCC_ENET_PROMISCOUS) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 440 | SCC_PSMR_PRO | |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 441 | #endif |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 442 | 0; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 443 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 444 | /* |
| 445 | * Configure Ethernet TENA Signal |
| 446 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 447 | |
| 448 | #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 449 | immr->im_ioport.iop_pcpar |= PC_ENET_TENA; |
| 450 | immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 451 | #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 452 | immr->im_cpm.cp_pbpar |= PB_ENET_TENA; |
| 453 | immr->im_cpm.cp_pbdir |= PB_ENET_TENA; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 454 | #else |
| 455 | #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined |
| 456 | #endif |
| 457 | |
| 458 | #if defined(CONFIG_ADS) && defined(CONFIG_MPC860) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 459 | /* |
| 460 | * Port C is used to control the PHY,MC68160. |
| 461 | */ |
| 462 | immr->im_ioport.iop_pcdir |= |
| 463 | (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 464 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 465 | immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; |
| 466 | immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); |
| 467 | *((uint *) BCSR1) &= ~BCSR1_ETHEN; |
| 468 | #endif /* MPC860ADS */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 469 | |
| 470 | #if defined(CONFIG_AMX860) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 471 | /* |
| 472 | * Port B is used to control the PHY,MC68160. |
| 473 | */ |
| 474 | immr->im_cpm.cp_pbdir |= |
| 475 | (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 476 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 477 | immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; |
| 478 | immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 479 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 480 | immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; |
| 481 | immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; |
| 482 | #endif /* AMX860 */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 483 | |
| 484 | #ifdef CONFIG_RPXCLASSIC |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 485 | *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; |
| 486 | *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 487 | #endif |
| 488 | |
| 489 | #ifdef CONFIG_RPXLITE |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 490 | *((uchar *) BCSR0) |= BCSR0_ETHEN; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 491 | #endif |
| 492 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 493 | #if defined(CONFIG_QS860T) |
| 494 | /* |
| 495 | * PB27=FDE-, set output low for full duplex |
| 496 | * PB26=Link Test Enable, normally high output |
| 497 | */ |
| 498 | immr->im_cpm.cp_pbdir |= 0x00000030; |
| 499 | immr->im_cpm.cp_pbdat |= 0x00000020; |
| 500 | immr->im_cpm.cp_pbdat &= ~0x00000010; |
| 501 | #endif /* QS860T */ |
| 502 | |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 503 | #ifdef CONFIG_MBX |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 504 | board_ether_init (); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 505 | #endif |
| 506 | |
| 507 | #if defined(CONFIG_NETVIA) |
wdenk | 993cad9 | 2003-06-26 22:04:09 +0000 | [diff] [blame] | 508 | #if defined(PA_ENET_PDN) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 509 | immr->im_ioport.iop_papar &= ~PA_ENET_PDN; |
| 510 | immr->im_ioport.iop_padir |= PA_ENET_PDN; |
| 511 | immr->im_ioport.iop_padat |= PA_ENET_PDN; |
wdenk | 993cad9 | 2003-06-26 22:04:09 +0000 | [diff] [blame] | 512 | #elif defined(PB_ENET_PDN) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 513 | immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN; |
| 514 | immr->im_cpm.cp_pbdir |= PB_ENET_PDN; |
| 515 | immr->im_cpm.cp_pbdat |= PB_ENET_PDN; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 516 | #elif defined(PC_ENET_PDN) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 517 | immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN; |
| 518 | immr->im_ioport.iop_pcdir |= PC_ENET_PDN; |
| 519 | immr->im_ioport.iop_pcdat |= PC_ENET_PDN; |
wdenk | 993cad9 | 2003-06-26 22:04:09 +0000 | [diff] [blame] | 520 | #elif defined(PD_ENET_PDN) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 521 | immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN; |
| 522 | immr->im_ioport.iop_pddir |= PD_ENET_PDN; |
| 523 | immr->im_ioport.iop_pddat |= PD_ENET_PDN; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 524 | #endif |
| 525 | #endif |
| 526 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 527 | /* |
| 528 | * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive |
| 529 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 530 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 531 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= |
| 532 | (SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 533 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 534 | /* |
| 535 | * Work around transmit problem with first eth packet |
| 536 | */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 537 | #if defined (CONFIG_FADS) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 538 | udelay (10000); /* wait 10 ms */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 539 | #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 540 | udelay (100000); /* wait 100 ms */ |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 541 | #endif |
| 542 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 543 | return 1; |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 544 | } |
| 545 | |
| 546 | |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 547 | static void scc_halt (struct eth_device *dev) |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 548 | { |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 549 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 550 | |
| 551 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= |
| 552 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | #if 0 |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 556 | void restart (void) |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 557 | { |
wdenk | 3bbc899 | 2003-12-07 22:27:15 +0000 | [diff] [blame^] | 558 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 559 | |
| 560 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= |
| 561 | (SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 562 | } |
| 563 | #endif |
wdenk | ed247f4 | 2002-10-07 21:58:02 +0000 | [diff] [blame] | 564 | #endif /* CFG_CMD_NET, SCC_ENET */ |