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Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 * John Otken, jotken@softadvances.com
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01007 */
8
9/************************************************************************
10 * luan.h - configuration for LUAN board
11 ***********************************************************************/
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
18#define CONFIG_LUAN 1 /* Board is Luan */
19#define CONFIG_440SP 1 /* Specific PPC440SP support */
20#define CONFIG_4xx 1 /* PPC4xx family */
21#define CONFIG_440 1
22#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
25
Stefan Roese490f2042008-06-06 15:55:03 +020026/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME luan
30#include "amcc-common.h"
31
Stefan Roese00cdb4c2007-03-08 10:13:16 +010032#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010033#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
34
35/*-----------------------------------------------------------------------
36 * Base addresses -- Note these are effective addresses where the
37 * actual resources get mapped (not physical addresses)
38 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
40#define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
41#define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
Wolfgang Denkbf560802010-09-10 23:04:05 +020042#define CONFIG_SYS_SRAM_SIZE (1 << 20)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010044
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010046
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
48#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
49#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
52#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010053#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010055#endif
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#if CONFIG_SYS_SRAM_BASE
58#define CONFIG_SYS_KBYTES_SDRAM 1024*2
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010059#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_KBYTES_SDRAM 1024
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010061#endif
62
63/*-----------------------------------------------------------------------
64 * Initial RAM & stack pointer (placed in SDRAM)
65 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +020067#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020068#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010070
71/*-----------------------------------------------------------------------
72 * Serial Port
73 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020074#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010076
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010077/*-----------------------------------------------------------------------
78 * Environment
79 *----------------------------------------------------------------------*/
80/*
81 * Define here the location of the environment variables (FLASH or EEPROM).
82 * Note: DENX encourages to use redundant environment in FLASH.
83 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020084#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010085
86/*-----------------------------------------------------------------------
87 * FLASH related
88 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
90#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
93#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_ADDR0 0x555
98#define CONFIG_SYS_FLASH_ADDR1 0x2aa
99#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100100
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200101#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200102#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100105
106/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200107#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
108#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200109#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100110
111/*-----------------------------------------------------------------------
112 * DDR SDRAM
113 *----------------------------------------------------------------------*/
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100114#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
115#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
Stefan Roesee4bbed22007-06-01 13:45:24 +0200116#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100117
118/*-----------------------------------------------------------------------
119 * I2C
120 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000121#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_I2C_MULTI_EEPROMS
124#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
125#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
126#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4f92ed52006-08-07 14:33:32 +0200128
Stefan Roese490f2042008-06-06 15:55:03 +0200129/*
130 * Default environment variables
131 */
132#define CONFIG_EXTRA_ENV_SETTINGS \
133 CONFIG_AMCC_DEF_ENV \
134 CONFIG_AMCC_DEF_ENV_PPC \
135 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100136 "kernel_addr=fc000000\0" \
137 "ramdisk_addr=fc100000\0" \
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100138 ""
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100139
Stefan Roesea00eccf2008-05-08 11:05:15 +0200140#define CONFIG_HAS_ETH0
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100141#define CONFIG_PHY_ADDR 1
142#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
143#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
144
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100145#ifdef DEBUG
146#define CONFIG_PANIC_HANG
147#else
148#define CONFIG_HW_WATCHDOG /* watchdog */
149#endif
150
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500151/*
Stefan Roese490f2042008-06-06 15:55:03 +0200152 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500153 */
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500154#define CONFIG_CMD_PCI
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500155#define CONFIG_CMD_SDRAM
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100156
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100157/*-----------------------------------------------------------------------
158 * PCI stuff
159 *-----------------------------------------------------------------------
160 */
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500161#if defined(CONFIG_CMD_PCI)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100162
163/* General PCI */
164#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000165#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100166#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
167#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
168
169/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PCI_TARGET_INIT
171#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
174#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100175
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500176#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100177
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100178#endif /* __CONFIG_H */