Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2005 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * John Otken, jotken@softadvances.com |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /************************************************************************ |
| 10 | * luan.h - configuration for LUAN board |
| 11 | ***********************************************************************/ |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /*----------------------------------------------------------------------- |
| 16 | * High Level Configuration Options |
| 17 | *----------------------------------------------------------------------*/ |
| 18 | #define CONFIG_LUAN 1 /* Board is Luan */ |
| 19 | #define CONFIG_440SP 1 /* Specific PPC440SP support */ |
| 20 | #define CONFIG_4xx 1 /* PPC4xx family */ |
| 21 | #define CONFIG_440 1 |
| 22 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
| 23 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 |
| 25 | |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 26 | /* |
| 27 | * Include common defines/options for all AMCC eval boards |
| 28 | */ |
| 29 | #define CONFIG_HOSTNAME luan |
| 30 | #include "amcc-common.h" |
| 31 | |
Stefan Roese | 00cdb4c | 2007-03-08 10:13:16 +0100 | [diff] [blame] | 32 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 33 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
| 34 | |
| 35 | /*----------------------------------------------------------------------- |
| 36 | * Base addresses -- Note these are effective addresses where the |
| 37 | * actual resources get mapped (not physical addresses) |
| 38 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ |
| 40 | #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ |
| 41 | #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ |
Wolfgang Denk | bf56080 | 2010-09-10 23:04:05 +0200 | [diff] [blame] | 42 | #define CONFIG_SYS_SRAM_SIZE (1 << 20) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 46 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
| 48 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
| 49 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 50 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #if CONFIG_SYS_LARGE_FLASH == 0xffc00000 |
| 52 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 53 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 55 | #endif |
| 56 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #if CONFIG_SYS_SRAM_BASE |
| 58 | #define CONFIG_SYS_KBYTES_SDRAM 1024*2 |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 59 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | #define CONFIG_SYS_KBYTES_SDRAM 1024 |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 61 | #endif |
| 62 | |
| 63 | /*----------------------------------------------------------------------- |
| 64 | * Initial RAM & stack pointer (placed in SDRAM) |
| 65 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_INIT_RAM_SIZE (8 << 10) |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 70 | |
| 71 | /*----------------------------------------------------------------------- |
| 72 | * Serial Port |
| 73 | *----------------------------------------------------------------------*/ |
Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 74 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 76 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 77 | /*----------------------------------------------------------------------- |
| 78 | * Environment |
| 79 | *----------------------------------------------------------------------*/ |
| 80 | /* |
| 81 | * Define here the location of the environment variables (FLASH or EEPROM). |
| 82 | * Note: DENX encourages to use redundant environment in FLASH. |
| 83 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 84 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 85 | |
| 86 | /*----------------------------------------------------------------------- |
| 87 | * FLASH related |
| 88 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
| 90 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 91 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 93 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 94 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 96 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
| 98 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa |
| 99 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 100 | |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 101 | #ifdef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 102 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 104 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 105 | |
| 106 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 107 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 108 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 109 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 110 | |
| 111 | /*----------------------------------------------------------------------- |
| 112 | * DDR SDRAM |
| 113 | *----------------------------------------------------------------------*/ |
Stefan Roese | 00cdb4c | 2007-03-08 10:13:16 +0100 | [diff] [blame] | 114 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
| 115 | #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ |
Stefan Roese | e4bbed2 | 2007-06-01 13:45:24 +0200 | [diff] [blame] | 116 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 117 | |
| 118 | /*----------------------------------------------------------------------- |
| 119 | * I2C |
| 120 | *----------------------------------------------------------------------*/ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 121 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 122 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 124 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
| 125 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 126 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 127 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
Stefan Roese | 4f92ed5 | 2006-08-07 14:33:32 +0200 | [diff] [blame] | 128 | |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 129 | /* |
| 130 | * Default environment variables |
| 131 | */ |
| 132 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 133 | CONFIG_AMCC_DEF_ENV \ |
| 134 | CONFIG_AMCC_DEF_ENV_PPC \ |
| 135 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 136 | "kernel_addr=fc000000\0" \ |
| 137 | "ramdisk_addr=fc100000\0" \ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 138 | "" |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 139 | |
Stefan Roese | a00eccf | 2008-05-08 11:05:15 +0200 | [diff] [blame] | 140 | #define CONFIG_HAS_ETH0 |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 141 | #define CONFIG_PHY_ADDR 1 |
| 142 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
| 143 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 144 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 145 | #ifdef DEBUG |
| 146 | #define CONFIG_PANIC_HANG |
| 147 | #else |
| 148 | #define CONFIG_HW_WATCHDOG /* watchdog */ |
| 149 | #endif |
| 150 | |
Jon Loeliger | 9bbb1c0 | 2007-07-04 22:32:57 -0500 | [diff] [blame] | 151 | /* |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 152 | * Commands additional to the ones defined in amcc-common.h |
Jon Loeliger | 7f5c015 | 2007-07-10 09:38:02 -0500 | [diff] [blame] | 153 | */ |
Jon Loeliger | 9bbb1c0 | 2007-07-04 22:32:57 -0500 | [diff] [blame] | 154 | #define CONFIG_CMD_PCI |
Jon Loeliger | 9bbb1c0 | 2007-07-04 22:32:57 -0500 | [diff] [blame] | 155 | #define CONFIG_CMD_SDRAM |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 156 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 157 | /*----------------------------------------------------------------------- |
| 158 | * PCI stuff |
| 159 | *----------------------------------------------------------------------- |
| 160 | */ |
Jon Loeliger | 9bbb1c0 | 2007-07-04 22:32:57 -0500 | [diff] [blame] | 161 | #if defined(CONFIG_CMD_PCI) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 162 | |
| 163 | /* General PCI */ |
| 164 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 165 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 166 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
| 167 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 168 | |
| 169 | /* Board-specific PCI */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 171 | #undef CONFIG_SYS_PCI_MASTER_INIT |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 172 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 174 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 175 | |
Jon Loeliger | 9bbb1c0 | 2007-07-04 22:32:57 -0500 | [diff] [blame] | 176 | #endif |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 177 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 178 | #endif /* __CONFIG_H */ |