blob: 13f954d00edd2fede1c5e6ab7f762b9063fbb254 [file] [log] [blame]
Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillipsfdfaa292015-03-17 12:00:45 -050012#define CONFIG_DISPLAY_BOARDINFO
13
Kim Phillips1c274c42007-07-25 19:25:33 -050014/*
15 * High Level Configuration Options
16 */
17#define CONFIG_E300 1 /* E300 family */
18#define CONFIG_QE 1 /* Has QE */
Peter Tyser2c7920a2009-05-22 17:23:25 -050019#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Kim Phillips1c274c42007-07-25 19:25:33 -050020
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
Kim Phillips1c274c42007-07-25 19:25:33 -050023#define CONFIG_PCI 1
Kim Phillips1c274c42007-07-25 19:25:33 -050024
25/*
26 * System Clock Setup
27 */
28#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
29
30#ifndef CONFIG_SYS_CLK_FREQ
31#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
32#endif
33
34/*
35 * Hardware Reset Configuration Word
36 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips1c274c42007-07-25 19:25:33 -050038 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39 HRCWL_DDR_TO_SCB_CLK_2X1 |\
40 HRCWL_VCO_1X2 |\
41 HRCWL_CSB_TO_CLKIN_2X1 |\
42 HRCWL_CORE_TO_CSB_2_5X1 |\
43 HRCWL_CE_PLL_VCO_DIV_2 |\
44 HRCWL_CE_PLL_DIV_1X1 |\
45 HRCWL_CE_TO_PLL_1X3)
46
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips1c274c42007-07-25 19:25:33 -050048 HRCWH_PCI_HOST |\
49 HRCWH_PCI1_ARBITER_ENABLE |\
50 HRCWH_CORE_ENABLE |\
51 HRCWH_FROM_0X00000100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_BIG_ENDIAN |\
56 HRCWH_LALE_NORMAL)
57
58/*
59 * System IO Config
60 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -050062
Kim Phillips1c274c42007-07-25 19:25:33 -050063/*
64 * IMMR new address
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips1c274c42007-07-25 19:25:33 -050067
68/*
Michael Barkowski5bbeea82008-03-20 13:15:34 -040069 * System performance
70 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050072#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
73/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
74#define CONFIG_SYS_SPCR_OPT 1
Michael Barkowski5bbeea82008-03-20 13:15:34 -040075
76/*
Kim Phillips1c274c42007-07-25 19:25:33 -050077 * DDR Setup
78 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050079#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
80#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Kim Phillips1c274c42007-07-25 19:25:33 -050082
83#undef CONFIG_SPD_EEPROM
84#if defined(CONFIG_SPD_EEPROM)
85/* Determine DDR configuration from I2C interface
86 */
87#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
88#else
89/* Manually set up DDR parameters
90 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050091#define CONFIG_SYS_DDR_SIZE 64 /* MB */
92#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger4dde49d2011-10-11 23:57:12 -050093 | CSCONFIG_ROW_BIT_13 \
94 | CSCONFIG_COL_BIT_9)
Michael Barkowski5bbeea82008-03-20 13:15:34 -040095 /* 0x80010101 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050096#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
97 | (0 << TIMING_CFG0_WRT_SHIFT) \
98 | (0 << TIMING_CFG0_RRT_SHIFT) \
99 | (0 << TIMING_CFG0_WWT_SHIFT) \
100 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
101 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
102 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
103 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -0400104 /* 0x00220802 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500105#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
106 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
107 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
108 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
109 | (3 << TIMING_CFG1_REFREC_SHIFT) \
110 | (2 << TIMING_CFG1_WRREC_SHIFT) \
111 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
112 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400113 /* 0x26253222 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500114#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
115 | (31 << TIMING_CFG2_CPO_SHIFT) \
116 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
117 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
118 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
119 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
120 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400121 /* 0x1f9048c7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_DDR_TIMING_3 0x00000000
123#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Michael Barkowskifc549c82008-03-20 13:15:28 -0400124 /* 0x02000000 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500125#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
126 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400127 /* 0x44480232 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500128#define CONFIG_SYS_DDR_MODE2 0x8000c000
129#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
130 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -0400131 /* 0x03200064 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500133#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400134 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500135 | SDRAM_CFG_32_BE)
Michael Barkowskifc549c82008-03-20 13:15:28 -0400136 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Kim Phillips1c274c42007-07-25 19:25:33 -0500138#endif
139
140/*
141 * Memory test
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
144#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
145#define CONFIG_SYS_MEMTEST_END 0x03f00000
Kim Phillips1c274c42007-07-25 19:25:33 -0500146
147/*
148 * The reserved memory
149 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200150#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips1c274c42007-07-25 19:25:33 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
153#define CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500154#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#undef CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500156#endif
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500159#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500160#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Kim Phillips1c274c42007-07-25 19:25:33 -0500161
162/*
163 * Initial RAM Base Address Setup
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500166#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
167#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
168#define CONFIG_SYS_GBL_DATA_OFFSET \
169 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips1c274c42007-07-25 19:25:33 -0500170
171/*
172 * Local Bus Configuration & Clock Setup
173 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500174#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
175#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LBC_LBCR 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -0500177
178/*
179 * FLASH on the Local Bus
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200182#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500183#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500185#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Kim Phillips1c274c42007-07-25 19:25:33 -0500186
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500187 /* Window base at flash base */
188#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500189#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Kim Phillips1c274c42007-07-25 19:25:33 -0500190
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500191#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500192 | BR_PS_16 /* 16 bit port */ \
193 | BR_MS_GPCM /* MSEL = GPCM */ \
194 | BR_V) /* valid */
195#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
196 | OR_GPCM_XAM \
197 | OR_GPCM_CSNT \
198 | OR_GPCM_ACS_DIV2 \
199 | OR_GPCM_XACS \
200 | OR_GPCM_SCY_15 \
201 | OR_GPCM_TRLX_SET \
202 | OR_GPCM_EHTR_SET \
203 | OR_GPCM_EAD)
204 /* 0xFE006FF7 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500205
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Kim Phillips1c274c42007-07-25 19:25:33 -0500208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#undef CONFIG_SYS_FLASH_CHECKSUM
Kim Phillips1c274c42007-07-25 19:25:33 -0500210
211/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500212 * Serial Port
213 */
214#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_NS16550_SERIAL
216#define CONFIG_SYS_NS16550_REG_SIZE 1
217#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips1c274c42007-07-25 19:25:33 -0500218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips1c274c42007-07-25 19:25:33 -0500221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
223#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips1c274c42007-07-25 19:25:33 -0500224
225#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500226#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips1c274c42007-07-25 19:25:33 -0500227
Kim Phillips1c274c42007-07-25 19:25:33 -0500228/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200229#define CONFIG_SYS_I2C
230#define CONFIG_SYS_I2C_FSL
231#define CONFIG_SYS_FSL_I2C_SPEED 400000
232#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
234#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips1c274c42007-07-25 19:25:33 -0500235
236/*
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400237 * Config on-board EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
240#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
241#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
242#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Kim Phillips1c274c42007-07-25 19:25:33 -0500243
244/*
245 * General PCI
246 * Addresses are mapped 1-1.
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
249#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
250#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
251#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
252#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
253#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
254#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
255#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
256#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
Kim Phillips1c274c42007-07-25 19:25:33 -0500257
258#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000259#define CONFIG_PCI_INDIRECT_BRIDGE
Michael Barkowski8f325cf2008-03-28 15:15:38 -0400260#define CONFIG_PCI_SKIP_HOST_BRIDGE
Kim Phillips1c274c42007-07-25 19:25:33 -0500261#define CONFIG_PCI_PNP /* do pci plug-and-play */
262
263#undef CONFIG_EEPRO100
264#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips1c274c42007-07-25 19:25:33 -0500266
267#endif /* CONFIG_PCI */
268
Kim Phillips1c274c42007-07-25 19:25:33 -0500269/*
270 * QE UEC ethernet configuration
271 */
272#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500273#define CONFIG_ETHPRIME "UEC0"
Kim Phillips1c274c42007-07-25 19:25:33 -0500274
275#define CONFIG_UEC_ETH1 /* ETH3 */
276
277#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
279#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
280#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
281#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
282#define CONFIG_SYS_UEC1_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500283#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100284#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500285#endif
286
287#define CONFIG_UEC_ETH2 /* ETH4 */
288
289#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
291#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
292#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
293#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
294#define CONFIG_SYS_UEC2_PHY_ADDR 0
Andy Fleming865ff852011-04-13 00:37:12 -0500295#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100296#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500297#endif
298
299/*
300 * Environment
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200303 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500304 #define CONFIG_ENV_ADDR \
305 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200306 #define CONFIG_ENV_SECT_SIZE 0x20000
307 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500308#else
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500309 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200310 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200312 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500313#endif
314
315#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips1c274c42007-07-25 19:25:33 -0500317
318/*
319 * BOOTP options
320 */
321#define CONFIG_BOOTP_BOOTFILESIZE
322#define CONFIG_BOOTP_BOOTPATH
323#define CONFIG_BOOTP_GATEWAY
324#define CONFIG_BOOTP_HOSTNAME
325
326/*
327 * Command line configuration.
328 */
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400329#define CONFIG_CMD_EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500330
331#if defined(CONFIG_PCI)
332 #define CONFIG_CMD_PCI
333#endif
Kim Phillips1c274c42007-07-25 19:25:33 -0500334
335#undef CONFIG_WATCHDOG /* watchdog disabled */
336
337/*
338 * Miscellaneous configurable options
339 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500340#define CONFIG_SYS_LONGHELP /* undef to save memory */
341#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips1c274c42007-07-25 19:25:33 -0500342
343#if (CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500345#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500347#endif
348
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500349 /* Print Buffer Size */
350#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500352 /* Boot Argument Buffer Size */
353#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Kim Phillips1c274c42007-07-25 19:25:33 -0500354
355/*
356 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700357 * have to be in the first 256 MB of memory, since this is
Kim Phillips1c274c42007-07-25 19:25:33 -0500358 * the maximum mapped by the Linux kernel during initialization.
359 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500360 /* Initial Memory map for Linux */
361#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kim Phillips1c274c42007-07-25 19:25:33 -0500362
363/*
364 * Core HID Setup
365 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500366#define CONFIG_SYS_HID0_INIT 0x000000000
367#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
368 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips1c274c42007-07-25 19:25:33 -0500370
371/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500372 * MMU Setup
373 */
Becky Bruce31d82672008-05-08 19:02:12 -0500374#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Kim Phillips1c274c42007-07-25 19:25:33 -0500375
376/* DDR: cache cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500377#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500378 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500379 | BATL_MEMCOHERENCE)
380#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
381 | BATU_BL_256M \
382 | BATU_VS \
383 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
385#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips1c274c42007-07-25 19:25:33 -0500386
387/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500388#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500389 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500390 | BATL_CACHEINHIBIT \
391 | BATL_GUARDEDSTORAGE)
392#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
393 | BATU_BL_4M \
394 | BATU_VS \
395 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
397#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips1c274c42007-07-25 19:25:33 -0500398
399/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500400#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500401 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500402 | BATL_MEMCOHERENCE)
403#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
404 | BATU_BL_32M \
405 | BATU_VS \
406 | BATU_VP)
407#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500408 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500409 | BATL_CACHEINHIBIT \
410 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips1c274c42007-07-25 19:25:33 -0500412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_IBAT3L (0)
414#define CONFIG_SYS_IBAT3U (0)
415#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
416#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips1c274c42007-07-25 19:25:33 -0500417
418/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500419#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500420#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
421 | BATU_BL_128K \
422 | BATU_VS \
423 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
425#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips1c274c42007-07-25 19:25:33 -0500426
427#ifdef CONFIG_PCI
428/* PCI MEM space: cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500429#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500430 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500431 | BATL_MEMCOHERENCE)
432#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
433 | BATU_BL_256M \
434 | BATU_VS \
435 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
437#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips1c274c42007-07-25 19:25:33 -0500438/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500439#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500440 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500441 | BATL_CACHEINHIBIT \
442 | BATL_GUARDEDSTORAGE)
443#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
444 | BATU_BL_256M \
445 | BATU_VS \
446 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
448#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500449#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_IBAT5L (0)
451#define CONFIG_SYS_IBAT5U (0)
452#define CONFIG_SYS_IBAT6L (0)
453#define CONFIG_SYS_IBAT6U (0)
454#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
455#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
456#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
457#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500458#endif
459
460/* Nothing in BAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_IBAT7L (0)
462#define CONFIG_SYS_IBAT7U (0)
463#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
464#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips1c274c42007-07-25 19:25:33 -0500465
Kim Phillips1c274c42007-07-25 19:25:33 -0500466#if (CONFIG_CMD_KGDB)
467#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Kim Phillips1c274c42007-07-25 19:25:33 -0500468#endif
469
470/*
471 * Environment Configuration
472 */
473#define CONFIG_ENV_OVERWRITE
474
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500475#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
476#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500477
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500478/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
479 * (see CONFIG_SYS_I2C_EEPROM) */
480 /* MAC address offset in I2C EEPROM */
481#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400482
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500483#define CONFIG_NETDEV "eth1"
Kim Phillips1c274c42007-07-25 19:25:33 -0500484
485#define CONFIG_HOSTNAME mpc8323erdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000486#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000487#define CONFIG_BOOTFILE "uImage"
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500488 /* U-Boot image on TFTP server */
489#define CONFIG_UBOOTPATH "u-boot.bin"
490#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
491#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Kim Phillips1c274c42007-07-25 19:25:33 -0500492
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500493 /* default location for tftp and bootm */
494#define CONFIG_LOADADDR 800000
Kim Phillips1c274c42007-07-25 19:25:33 -0500495#define CONFIG_BAUDRATE 115200
496
Kim Phillips1c274c42007-07-25 19:25:33 -0500497#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500498 "netdev=" CONFIG_NETDEV "\0" \
499 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500500 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200501 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
502 " +$filesize; " \
503 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
504 " +$filesize; " \
505 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
506 " $filesize; " \
507 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
508 " +$filesize; " \
509 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
510 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500511 "fdtaddr=780000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500512 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500513 "ramdiskaddr=1000000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500514 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500515 "console=ttyS0\0" \
516 "setbootargs=setenv bootargs " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500517 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
Kim Phillips1c274c42007-07-25 19:25:33 -0500518 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500519 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
520 "$netdev:off "\
Kim Phillips1c274c42007-07-25 19:25:33 -0500521 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
522
523#define CONFIG_NFSBOOTCOMMAND \
524 "setenv rootdev /dev/nfs;" \
525 "run setbootargs;" \
526 "run setipargs;" \
527 "tftp $loadaddr $bootfile;" \
528 "tftp $fdtaddr $fdtfile;" \
529 "bootm $loadaddr - $fdtaddr"
530
531#define CONFIG_RAMBOOTCOMMAND \
532 "setenv rootdev /dev/ram;" \
533 "run setbootargs;" \
534 "tftp $ramdiskaddr $ramdiskfile;" \
535 "tftp $loadaddr $bootfile;" \
536 "tftp $fdtaddr $fdtfile;" \
537 "bootm $loadaddr $ramdiskaddr $fdtaddr"
538
Kim Phillips1c274c42007-07-25 19:25:33 -0500539#endif /* __CONFIG_H */