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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
wdenk42dfe7a2004-03-14 22:25:36 +000010 . Developed by Simple Network Magic Corporation (SNMC)
wdenkfe8c2802002-11-03 00:38:21 +000011 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
17 .
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk42dfe7a2004-03-14 22:25:36 +000020 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkfe8c2802002-11-03 00:38:21 +000021 . GNU General Public License for more details.
22 .
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
wdenk42dfe7a2004-03-14 22:25:36 +000025 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
wdenkfe8c2802002-11-03 00:38:21 +000026 .
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
30 .
31 .
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
37 .
38 . Arguments:
wdenk42dfe7a2004-03-14 22:25:36 +000039 . io = for the base address
wdenkfe8c2802002-11-03 00:38:21 +000040 . irq = for the IRQ
41 .
42 . author:
wdenk42dfe7a2004-03-14 22:25:36 +000043 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
wdenkfe8c2802002-11-03 00:38:21 +000045 .
46 .
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
48 .
49 . Sources:
wdenk42dfe7a2004-03-14 22:25:36 +000050 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
wdenkfe8c2802002-11-03 00:38:21 +000053 .
54 . History:
wdenk42dfe7a2004-03-14 22:25:36 +000055 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000056 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
wdenk42dfe7a2004-03-14 22:25:36 +000057 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
wdenkfe8c2802002-11-03 00:38:21 +000060 ----------------------------------------------------------------------------*/
61
62#include <common.h>
63#include <command.h>
wdenkf39748a2004-06-09 13:37:52 +000064#include <config.h>
Ben Warren7194ab82009-10-04 22:37:03 -070065#include <malloc.h>
wdenkfe8c2802002-11-03 00:38:21 +000066#include "smc91111.h"
67#include <net.h>
68
wdenkfe8c2802002-11-03 00:38:21 +000069/* Use power-down feature of the chip */
70#define POWER_DOWN 0
71
72#define NO_AUTOPROBE
73
Wolfgang Denk0be248f2006-03-07 00:22:36 +010074#define SMC_DEBUG 0
wdenk8bf3b002003-12-06 23:20:41 +000075
76#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000077static const char version[] =
78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000079#endif
wdenkfe8c2802002-11-03 00:38:21 +000080
wdenkf39748a2004-06-09 13:37:52 +000081/* Autonegotiation timeout in seconds */
82#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
83#define CONFIG_SMC_AUTONEG_TIMEOUT 10
84#endif
85
wdenkfe8c2802002-11-03 00:38:21 +000086/*------------------------------------------------------------------------
87 .
88 . Configuration options, for the experienced user to change.
89 .
90 -------------------------------------------------------------------------*/
91
92/*
93 . Wait time for memory to be free. This probably shouldn't be
94 . tuned that much, as waiting for this means nothing else happens
95 . in the system
96*/
97#define MEMORY_WAIT_TIME 16
98
99
100#if (SMC_DEBUG > 2 )
101#define PRINTK3(args...) printf(args)
102#else
103#define PRINTK3(args...)
104#endif
105
106#if SMC_DEBUG > 1
107#define PRINTK2(args...) printf(args)
108#else
109#define PRINTK2(args...)
110#endif
111
112#ifdef SMC_DEBUG
113#define PRINTK(args...) printf(args)
114#else
115#define PRINTK(args...)
116#endif
117
118
119/*------------------------------------------------------------------------
120 .
wdenk42dfe7a2004-03-14 22:25:36 +0000121 . The internal workings of the driver. If you are changing anything
wdenkfe8c2802002-11-03 00:38:21 +0000122 . here with the SMC stuff, you should have the datasheet and know
123 . what you are doing.
124 .
125 -------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000126
127/* Memory sizing constant */
128#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
129
130#ifndef CONFIG_SMC91111_BASE
Ben Warren7194ab82009-10-04 22:37:03 -0700131#error "SMC91111 Base address must be passed to initialization funciton"
132/* #define CONFIG_SMC91111_BASE 0x20000300 */
wdenkfe8c2802002-11-03 00:38:21 +0000133#endif
134
wdenkfe8c2802002-11-03 00:38:21 +0000135#define SMC_DEV_NAME "SMC91111"
136#define SMC_PHY_ADDR 0x0000
137#define SMC_ALLOC_MAX_TRY 5
138#define SMC_TX_TIMEOUT 30
139
140#define SMC_PHY_CLOCK_DELAY 1000
141
142#define ETH_ZLEN 60
143
wdenk42dfe7a2004-03-14 22:25:36 +0000144#ifdef CONFIG_SMC_USE_32_BIT
wdenkfe8c2802002-11-03 00:38:21 +0000145#define USE_32_BIT 1
146#else
147#undef USE_32_BIT
148#endif
wdenkfe8c2802002-11-03 00:38:21 +0000149
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100150#ifdef SHARED_RESOURCES
Ben Warren7194ab82009-10-04 22:37:03 -0700151extern void swap_to(int device_id);
152#else
153# define swap_to(x)
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100154#endif
wdenkfe8c2802002-11-03 00:38:21 +0000155
wdenkfe8c2802002-11-03 00:38:21 +0000156#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700157static void smc_phy_configure(struct eth_device *dev);
wdenkfe8c2802002-11-03 00:38:21 +0000158#endif /* !CONFIG_SMC91111_EXT_PHY */
159
160/*
wdenkfe8c2802002-11-03 00:38:21 +0000161 ------------------------------------------------------------
162 .
163 . Internal routines
164 .
165 ------------------------------------------------------------
166*/
167
wdenkc3c7f862004-06-09 14:47:54 +0000168#ifdef CONFIG_SMC_USE_IOFUNCS
169/*
170 * input and output functions
171 *
172 * Implemented due to inx,outx macros accessing the device improperly
173 * and putting the device into an unkown state.
174 *
175 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
176 * could not be free'd (hence the alloc failures), duplicate packets,
177 * packets being corrupt (shifted) on the wire, etc. Switching to the
178 * inx,outx functions fixed this problem.
179 */
wdenkc3c7f862004-06-09 14:47:54 +0000180
181#define barrier() __asm__ __volatile__("": : :"memory")
182
Ben Warren7194ab82009-10-04 22:37:03 -0700183static inline word SMC_inw(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000184{
185 word v;
Ben Warren7194ab82009-10-04 22:37:03 -0700186 v = *((volatile word*)(dev->iobase + offset));
wdenkc3c7f862004-06-09 14:47:54 +0000187 barrier(); *(volatile u32*)(0xc0000000);
188 return v;
189}
190
Ben Warren7194ab82009-10-04 22:37:03 -0700191static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000192{
Ben Warren7194ab82009-10-04 22:37:03 -0700193 *((volatile word*)(dev->iobase + offset)) = value;
wdenkc3c7f862004-06-09 14:47:54 +0000194 barrier(); *(volatile u32*)(0xc0000000);
195}
196
Ben Warren7194ab82009-10-04 22:37:03 -0700197static inline byte SMC_inb(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000198{
199 word _w;
200
Ben Warren7194ab82009-10-04 22:37:03 -0700201 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000202 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
203}
204
Ben Warren7194ab82009-10-04 22:37:03 -0700205static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000206{
207 word _w;
208
Ben Warren7194ab82009-10-04 22:37:03 -0700209 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000210 if (offset & 1)
Ben Warren7194ab82009-10-04 22:37:03 -0700211 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
212 (value<<8) | (_w & 0x00ff);
wdenkc3c7f862004-06-09 14:47:54 +0000213 else
Ben Warren7194ab82009-10-04 22:37:03 -0700214 *((volatile word*)(dev->iobase + offset)) =
215 value | (_w & 0xff00);
wdenkc3c7f862004-06-09 14:47:54 +0000216}
217
Ben Warren7194ab82009-10-04 22:37:03 -0700218static inline void SMC_insw(struct eth_device *dev, dword offset,
219 volatile uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000220{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100221 volatile word *p = (volatile word *)buf;
222
wdenkc3c7f862004-06-09 14:47:54 +0000223 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700224 *p++ = SMC_inw(dev, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100225 barrier();
226 *((volatile u32*)(0xc0000000));
wdenkc3c7f862004-06-09 14:47:54 +0000227 }
228}
229
Ben Warren7194ab82009-10-04 22:37:03 -0700230static inline void SMC_outsw(struct eth_device *dev, dword offset,
231 uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000232{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100233 volatile word *p = (volatile word *)buf;
234
wdenkc3c7f862004-06-09 14:47:54 +0000235 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700236 SMC_outw(dev, *p++, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100237 barrier();
238 *(volatile u32*)(0xc0000000);
wdenkc3c7f862004-06-09 14:47:54 +0000239 }
240}
241#endif /* CONFIG_SMC_USE_IOFUNCS */
242
wdenkfe8c2802002-11-03 00:38:21 +0000243/*
244 . A rather simple routine to print out a packet for debugging purposes.
245*/
246#if SMC_DEBUG > 2
247static void print_packet( byte *, int );
248#endif
249
250#define tx_done(dev) 1
251
Ben Warren7194ab82009-10-04 22:37:03 -0700252static int poll4int (struct eth_device *dev, byte mask, int timeout)
wdenkb56ddc62003-09-15 21:14:37 +0000253{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
wdenkb56ddc62003-09-15 21:14:37 +0000255 int is_timeout = 0;
Ben Warren7194ab82009-10-04 22:37:03 -0700256 word old_bank = SMC_inw (dev, BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000257
wdenkb56ddc62003-09-15 21:14:37 +0000258 PRINTK2 ("Polling...\n");
Ben Warren7194ab82009-10-04 22:37:03 -0700259 SMC_SELECT_BANK (dev, 2);
260 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
wdenkb56ddc62003-09-15 21:14:37 +0000261 if (get_timer (0) >= tmo) {
262 is_timeout = 1;
263 break;
264 }
wdenkfe8c2802002-11-03 00:38:21 +0000265 }
wdenkfe8c2802002-11-03 00:38:21 +0000266
wdenkb56ddc62003-09-15 21:14:37 +0000267 /* restore old bank selection */
Ben Warren7194ab82009-10-04 22:37:03 -0700268 SMC_SELECT_BANK (dev, old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000269
wdenkb56ddc62003-09-15 21:14:37 +0000270 if (is_timeout)
271 return 1;
272 else
273 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000274}
275
wdenk487778b2003-06-06 11:20:01 +0000276/* Only one release command at a time, please */
Ben Warren7194ab82009-10-04 22:37:03 -0700277static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
wdenk487778b2003-06-06 11:20:01 +0000278{
279 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000280
wdenk487778b2003-06-06 11:20:01 +0000281 /* assume bank 2 selected */
Ben Warren7194ab82009-10-04 22:37:03 -0700282 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000283 udelay (1); /* Wait until not busy */
284 if (++count > 200)
285 break;
wdenk487778b2003-06-06 11:20:01 +0000286 }
287}
288
wdenkfe8c2802002-11-03 00:38:21 +0000289/*
290 . Function: smc_reset( void )
291 . Purpose:
wdenk42dfe7a2004-03-14 22:25:36 +0000292 . This sets the SMC91111 chip to its normal state, hopefully from whatever
293 . mess that any other DOS driver has put it in.
wdenkfe8c2802002-11-03 00:38:21 +0000294 .
295 . Maybe I should reset more registers to defaults in here? SOFTRST should
296 . do that for me.
297 .
298 . Method:
299 . 1. send a SOFT RESET
300 . 2. wait for it to finish
301 . 3. enable autorelease mode
302 . 4. reset the memory management unit
303 . 5. clear all interrupts
304 .
305*/
Ben Warren7194ab82009-10-04 22:37:03 -0700306static void smc_reset (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000307{
wdenkf39748a2004-06-09 13:37:52 +0000308 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000309
310 /* This resets the registers mostly to defaults, but doesn't
311 affect EEPROM. That seems unnecessary */
Ben Warren7194ab82009-10-04 22:37:03 -0700312 SMC_SELECT_BANK (dev, 0);
313 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000314
315 /* Setup the Configuration Register */
316 /* This is necessary because the CONFIG_REG is not affected */
317 /* by a soft reset */
318
Ben Warren7194ab82009-10-04 22:37:03 -0700319 SMC_SELECT_BANK (dev, 1);
wdenkfe8c2802002-11-03 00:38:21 +0000320#if defined(CONFIG_SMC91111_EXT_PHY)
Ben Warren7194ab82009-10-04 22:37:03 -0700321 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000322#else
Ben Warren7194ab82009-10-04 22:37:03 -0700323 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000324#endif
325
326
327 /* Release from possible power-down state */
328 /* Configuration register is not affected by Soft Reset */
Ben Warren7194ab82009-10-04 22:37:03 -0700329 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
330 CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000331
Ben Warren7194ab82009-10-04 22:37:03 -0700332 SMC_SELECT_BANK (dev, 0);
wdenkfe8c2802002-11-03 00:38:21 +0000333
334 /* this should pause enough for the chip to be happy */
wdenkb56ddc62003-09-15 21:14:37 +0000335 udelay (10);
wdenkfe8c2802002-11-03 00:38:21 +0000336
337 /* Disable transmit and receive functionality */
Ben Warren7194ab82009-10-04 22:37:03 -0700338 SMC_outw (dev, RCR_CLEAR, RCR_REG);
339 SMC_outw (dev, TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000340
341 /* set the control register */
Ben Warren7194ab82009-10-04 22:37:03 -0700342 SMC_SELECT_BANK (dev, 1);
343 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000344
345 /* Reset the MMU */
Ben Warren7194ab82009-10-04 22:37:03 -0700346 SMC_SELECT_BANK (dev, 2);
347 smc_wait_mmu_release_complete (dev);
348 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
349 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
wdenkb56ddc62003-09-15 21:14:37 +0000350 udelay (1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000351
352 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
353 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000354 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000355
356 /* Disable all interrupts */
Ben Warren7194ab82009-10-04 22:37:03 -0700357 SMC_outb (dev, 0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000358}
359
360/*
361 . Function: smc_enable
362 . Purpose: let the chip talk to the outside work
363 . Method:
364 . 1. Enable the transmitter
365 . 2. Enable the receiver
366 . 3. Enable interrupts
367*/
Ben Warren7194ab82009-10-04 22:37:03 -0700368static void smc_enable(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000369{
wdenkf39748a2004-06-09 13:37:52 +0000370 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -0700371 SMC_SELECT_BANK( dev, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000372 /* see the header file for options in TCR/RCR DEFAULT*/
Ben Warren7194ab82009-10-04 22:37:03 -0700373 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
374 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000375
376 /* clear MII_DIS */
377/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
378}
379
380/*
Ben Warren7194ab82009-10-04 22:37:03 -0700381 . Function: smc_halt
wdenkfe8c2802002-11-03 00:38:21 +0000382 . Purpose: closes down the SMC91xxx chip.
383 . Method:
384 . 1. zero the interrupt mask
385 . 2. clear the enable receive flag
386 . 3. clear the enable xmit flags
387 .
388 . TODO:
389 . (1) maybe utilize power down mode.
390 . Why not yet? Because while the chip will go into power down mode,
391 . the manual says that it will wake up in response to any I/O requests
wdenk42dfe7a2004-03-14 22:25:36 +0000392 . in the register space. Empirical results do not show this working.
wdenkfe8c2802002-11-03 00:38:21 +0000393*/
Ben Warren7194ab82009-10-04 22:37:03 -0700394static void smc_halt(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000395{
Ben Warren7194ab82009-10-04 22:37:03 -0700396 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000397
398 /* no more interrupts for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700399 SMC_SELECT_BANK( dev, 2 );
400 SMC_outb( dev, 0, IM_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000401
402 /* and tell the card to stay away from that nasty outside world */
Ben Warren7194ab82009-10-04 22:37:03 -0700403 SMC_SELECT_BANK( dev, 0 );
404 SMC_outb( dev, RCR_CLEAR, RCR_REG );
405 SMC_outb( dev, TCR_CLEAR, TCR_REG );
406
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100407 swap_to(FLASH);
wdenkfe8c2802002-11-03 00:38:21 +0000408}
409
410
411/*
Ben Warren7194ab82009-10-04 22:37:03 -0700412 . Function: smc_send(struct net_device * )
wdenkfe8c2802002-11-03 00:38:21 +0000413 . Purpose:
414 . This sends the actual packet to the SMC9xxx chip.
415 .
416 . Algorithm:
wdenk42dfe7a2004-03-14 22:25:36 +0000417 . First, see if a saved_skb is available.
wdenkfe8c2802002-11-03 00:38:21 +0000418 . ( this should NOT be called if there is no 'saved_skb'
419 . Now, find the packet number that the chip allocated
420 . Point the data pointers at it in memory
421 . Set the length word in the chip's memory
422 . Dump the packet to chip memory
423 . Check if a last byte is needed ( odd length packet )
424 . if so, set the control flag right
wdenk42dfe7a2004-03-14 22:25:36 +0000425 . Tell the card to send it
wdenkfe8c2802002-11-03 00:38:21 +0000426 . Enable the transmit interrupt, so I know if it failed
wdenk42dfe7a2004-03-14 22:25:36 +0000427 . Free the kernel data if I actually sent it.
wdenkfe8c2802002-11-03 00:38:21 +0000428*/
Ben Warren7194ab82009-10-04 22:37:03 -0700429static int smc_send(struct eth_device *dev, volatile void *packet,
430 int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000431{
wdenkb56ddc62003-09-15 21:14:37 +0000432 byte packet_no;
wdenkb56ddc62003-09-15 21:14:37 +0000433 byte *buf;
434 int length;
435 int numPages;
436 int try = 0;
437 int time_out;
438 byte status;
wdenk518e2e12004-03-25 14:59:05 +0000439 byte saved_pnr;
440 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000441
wdenk518e2e12004-03-25 14:59:05 +0000442 /* save PTR and PNR registers before manipulation */
Ben Warren7194ab82009-10-04 22:37:03 -0700443 SMC_SELECT_BANK (dev, 2);
444 saved_pnr = SMC_inb( dev, PN_REG );
445 saved_ptr = SMC_inw( dev, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000446
wdenkf39748a2004-06-09 13:37:52 +0000447 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000448
449 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
450
451 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000452 ** The MMU wants the number of pages to be the number of 256 bytes
453 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
454 **
455 ** The 91C111 ignores the size bits, but the code is left intact
456 ** for backwards and future compatibility.
457 **
458 ** Pkt size for allocating is data length +6 (for additional status
459 ** words, length and ctl!)
460 **
461 ** If odd size then last byte is included in this header.
462 */
463 numPages = ((length & 0xfffe) + 6);
464 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000465
wdenkb56ddc62003-09-15 21:14:37 +0000466 if (numPages > 7) {
467 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000468 return 0;
469 }
470
471 /* now, try to allocate the memory */
Ben Warren7194ab82009-10-04 22:37:03 -0700472 SMC_SELECT_BANK (dev, 2);
473 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000474
wdenkdc7c9a12003-03-26 06:55:25 +0000475 /* FIXME: the ALLOC_INT bit never gets set *
wdenk42dfe7a2004-03-14 22:25:36 +0000476 * so the following will always give a *
477 * memory allocation error. *
478 * same code works in armboot though *
wdenkdc7c9a12003-03-26 06:55:25 +0000479 * -ro
480 */
481
wdenkfe8c2802002-11-03 00:38:21 +0000482again:
483 try++;
484 time_out = MEMORY_WAIT_TIME;
485 do {
Ben Warren7194ab82009-10-04 22:37:03 -0700486 status = SMC_inb (dev, SMC91111_INT_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000487 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000488 /* acknowledge the interrupt */
Ben Warren7194ab82009-10-04 22:37:03 -0700489 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000490 break;
wdenkfe8c2802002-11-03 00:38:21 +0000491 }
wdenkb56ddc62003-09-15 21:14:37 +0000492 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000493
wdenkb56ddc62003-09-15 21:14:37 +0000494 if (!time_out) {
495 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
496 SMC_DEV_NAME, try);
497 if (try < SMC_ALLOC_MAX_TRY)
498 goto again;
499 else
500 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000501 }
502
wdenkb56ddc62003-09-15 21:14:37 +0000503 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
504 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000505
wdenkb56ddc62003-09-15 21:14:37 +0000506 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000507
508 /* If I get here, I _know_ there is a packet slot waiting for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700509 packet_no = SMC_inb (dev, AR_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000510 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000511 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000512 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000513 return 0;
514 }
515
516 /* we have a packet address, so tell the card to use it */
wdenk1f6d4252004-11-02 13:00:33 +0000517#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700518 SMC_outb (dev, packet_no, PN_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000519#else
520 /* On Xaeniax board, we can't use SMC_outb here because that way
521 * the Allocate MMU command will end up written to the command register
522 * as well, which will lead to a problem.
523 */
Ben Warren7194ab82009-10-04 22:37:03 -0700524 SMC_outl (dev, packet_no << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000525#endif
wdenkb79a11c2004-03-25 15:14:43 +0000526 /* do not write new ptr value if Write data fifo not empty */
527 while ( saved_ptr & PTR_NOTEMPTY )
wdenk518e2e12004-03-25 14:59:05 +0000528 printf ("Write data fifo not empty!\n");
529
wdenkfe8c2802002-11-03 00:38:21 +0000530 /* point to the beginning of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700531 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000532
wdenkb56ddc62003-09-15 21:14:37 +0000533 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
534 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000535
536#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000537 printf ("Transmitting Packet\n");
538 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000539#endif
540
541 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000542 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000543#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700544 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000545#else
Ben Warren7194ab82009-10-04 22:37:03 -0700546 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000547 /* send the packet length ( +6 for status words, length, and ctl */
Ben Warren7194ab82009-10-04 22:37:03 -0700548 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000549#endif
550
551 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000552 . I _think_ it's faster to send the longs first, and then
553 . mop up by sending the last word. It depends heavily
wdenk42dfe7a2004-03-14 22:25:36 +0000554 . on alignment, at least on the 486. Maybe it would be
wdenkb56ddc62003-09-15 21:14:37 +0000555 . a good idea to check which is optimal? But that could take
556 . almost as much time as is saved?
557 */
wdenkfe8c2802002-11-03 00:38:21 +0000558#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700559 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
wdenkbb310d42004-11-22 22:20:07 +0000560#ifndef CONFIG_XAENIAX
wdenkb56ddc62003-09-15 21:14:37 +0000561 if (length & 0x2)
Ben Warren7194ab82009-10-04 22:37:03 -0700562 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
wdenkb56ddc62003-09-15 21:14:37 +0000563 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000564#else
wdenkbb310d42004-11-22 22:20:07 +0000565 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
566 * unaligned tail part specially. The standard code doesn't work.
567 */
568 if ((length & 3) == 3) {
569 u16 * ptr = (u16*) &buf[length-3];
Ben Warren7194ab82009-10-04 22:37:03 -0700570 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
wdenkbb310d42004-11-22 22:20:07 +0000571 SMC91111_DATA_REG);
572 } else if ((length & 2) == 2) {
573 u16 * ptr = (u16*) &buf[length-2];
Ben Warren7194ab82009-10-04 22:37:03 -0700574 SMC_outl(dev, *ptr, SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000575 } else if (length & 1) {
Ben Warren7194ab82009-10-04 22:37:03 -0700576 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000577 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700578 SMC_outl(dev, 0, SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000579 }
580#endif
581#else
Ben Warren7194ab82009-10-04 22:37:03 -0700582 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000583#endif /* USE_32_BIT */
584
wdenkbb310d42004-11-22 22:20:07 +0000585#ifndef CONFIG_XAENIAX
wdenk42dfe7a2004-03-14 22:25:36 +0000586 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000587 if ((length & 1) == 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700588 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000589 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700590 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000591 }
wdenkbb310d42004-11-22 22:20:07 +0000592#endif
wdenkfe8c2802002-11-03 00:38:21 +0000593
594 /* and let the chipset deal with it */
Ben Warren7194ab82009-10-04 22:37:03 -0700595 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000596
597 /* poll for TX INT */
Ben Warren7194ab82009-10-04 22:37:03 -0700598 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
wdenk518e2e12004-03-25 14:59:05 +0000599 /* poll for TX_EMPTY INT - autorelease enabled */
Ben Warren7194ab82009-10-04 22:37:03 -0700600 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000601 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000602 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000603
604 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000605 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000606#ifdef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700607 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000608#endif
wdenkfe8c2802002-11-03 00:38:21 +0000609
wdenk8bde7f72003-06-27 21:31:46 +0000610 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700611 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000612 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000613 }
wdenkfe8c2802002-11-03 00:38:21 +0000614
wdenkb56ddc62003-09-15 21:14:37 +0000615 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000616
617
618 return 0;
619 } else {
620 /* ack. int */
Ben Warren7194ab82009-10-04 22:37:03 -0700621 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
wdenk518e2e12004-03-25 14:59:05 +0000622 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000623 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
624 length);
wdenkfe8c2802002-11-03 00:38:21 +0000625
626 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000627 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000628#ifdef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700629 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000630#endif
wdenkfe8c2802002-11-03 00:38:21 +0000631
wdenk8bde7f72003-06-27 21:31:46 +0000632 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700633 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000634 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000635 }
wdenkfe8c2802002-11-03 00:38:21 +0000636
wdenkb56ddc62003-09-15 21:14:37 +0000637 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000638
639
640 }
641
wdenk518e2e12004-03-25 14:59:05 +0000642 /* restore previously saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000643#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700644 SMC_outb( dev, saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000645#else
646 /* On Xaeniax board, we can't use SMC_outb here because that way
647 * the Allocate MMU command will end up written to the command register
648 * as well, which will lead to a problem.
649 */
Ben Warren7194ab82009-10-04 22:37:03 -0700650 SMC_outl(dev, saved_pnr << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000651#endif
Ben Warren7194ab82009-10-04 22:37:03 -0700652 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000653
wdenkfe8c2802002-11-03 00:38:21 +0000654 return length;
655}
656
Thomas Chou1ca6d0d2010-10-06 09:16:10 +0800657static int smc_write_hwaddr(struct eth_device *dev)
658{
659 int i;
660
661 swap_to(ETHERNET);
662 SMC_SELECT_BANK (dev, 1);
663#ifdef USE_32_BIT
664 for (i = 0; i < 6; i += 2) {
665 word address;
666
667 address = dev->enetaddr[i + 1] << 8;
668 address |= dev->enetaddr[i];
669 SMC_outw(dev, address, (ADDR0_REG + i));
670 }
671#else
672 for (i = 0; i < 6; i++)
673 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
674#endif
675 swap_to(FLASH);
676 return 0;
677}
678
wdenkfe8c2802002-11-03 00:38:21 +0000679/*
680 * Open and Initialize the board
681 *
682 * Set up everything, reset the card, etc ..
683 *
684 */
Ben Warren7194ab82009-10-04 22:37:03 -0700685static int smc_init(struct eth_device *dev, bd_t *bd)
wdenkfe8c2802002-11-03 00:38:21 +0000686{
Ben Warren7194ab82009-10-04 22:37:03 -0700687 swap_to(ETHERNET);
688
689 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000690
691 /* reset the hardware */
Ben Warren7194ab82009-10-04 22:37:03 -0700692 smc_reset (dev);
693 smc_enable (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000694
695 /* Configure the PHY */
696#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700697 smc_phy_configure (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000698#endif
699
wdenkfe8c2802002-11-03 00:38:21 +0000700 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
Ben Warren7194ab82009-10-04 22:37:03 -0700701/* SMC_SELECT_BANK(dev, 0); */
702/* SMC_outw(dev, 0, RPC_REG); */
wdenkfe8c2802002-11-03 00:38:21 +0000703
Ben Warren7194ab82009-10-04 22:37:03 -0700704 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
705
wdenkfe8c2802002-11-03 00:38:21 +0000706 return 0;
707}
708
wdenkfe8c2802002-11-03 00:38:21 +0000709/*-------------------------------------------------------------
710 .
711 . smc_rcv - receive a packet from the card
712 .
713 . There is ( at least ) a packet waiting to be read from
714 . chip-memory.
715 .
716 . o Read the status
717 . o If an error, record it
718 . o otherwise, read in the packet
719 --------------------------------------------------------------
720*/
Ben Warren7194ab82009-10-04 22:37:03 -0700721static int smc_rcv(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000722{
wdenk42dfe7a2004-03-14 22:25:36 +0000723 int packet_number;
wdenkfe8c2802002-11-03 00:38:21 +0000724 word status;
725 word packet_length;
wdenk42dfe7a2004-03-14 22:25:36 +0000726 int is_error = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000727#ifdef USE_32_BIT
728 dword stat_len;
729#endif
wdenk518e2e12004-03-25 14:59:05 +0000730 byte saved_pnr;
731 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000732
Ben Warren7194ab82009-10-04 22:37:03 -0700733 SMC_SELECT_BANK(dev, 2);
wdenk518e2e12004-03-25 14:59:05 +0000734 /* save PTR and PTR registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700735 saved_pnr = SMC_inb( dev, PN_REG );
736 saved_ptr = SMC_inw( dev, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000737
Ben Warren7194ab82009-10-04 22:37:03 -0700738 packet_number = SMC_inw( dev, RXFIFO_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000739
740 if ( packet_number & RXFIFO_REMPTY ) {
741
742 return 0;
743 }
744
wdenkf39748a2004-06-09 13:37:52 +0000745 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000746 /* start reading from the start of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700747 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000748
749 /* First two words are status and packet_length */
750#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700751 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000752 status = stat_len & 0xffff;
753 packet_length = stat_len >> 16;
754#else
Ben Warren7194ab82009-10-04 22:37:03 -0700755 status = SMC_inw( dev, SMC91111_DATA_REG );
756 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000757#endif
758
759 packet_length &= 0x07ff; /* mask off top bits */
760
761 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
762
763 if ( !(status & RS_ERRORS ) ){
764 /* Adjust for having already read the first two words */
765 packet_length -= 4; /*4; */
766
767
wdenkfe8c2802002-11-03 00:38:21 +0000768 /* set odd length for bug in LAN91C111, */
769 /* which never sets RS_ODDFRAME */
770 /* TODO ? */
771
772
773#ifdef USE_32_BIT
774 PRINTK3(" Reading %d dwords (and %d bytes) \n",
775 packet_length >> 2, packet_length & 3 );
776 /* QUESTION: Like in the TX routine, do I want
777 to send the DWORDs or the bytes first, or some
778 mixture. A mixture might improve already slow PIO
wdenk42dfe7a2004-03-14 22:25:36 +0000779 performance */
Ben Warren7194ab82009-10-04 22:37:03 -0700780 SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
781 packet_length >> 2 );
wdenkfe8c2802002-11-03 00:38:21 +0000782 /* read the left over bytes */
783 if (packet_length & 3) {
784 int i;
785
Ben Warren7194ab82009-10-04 22:37:03 -0700786 byte *tail = (byte *)(NetRxPackets[0] +
787 (packet_length & ~3));
788 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000789 for (i=0; i<(packet_length & 3); i++)
790 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
791 }
792#else
793 PRINTK3(" Reading %d words and %d byte(s) \n",
794 (packet_length >> 1 ), packet_length & 1 );
Ben Warren7194ab82009-10-04 22:37:03 -0700795 SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
796 packet_length >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000797
798#endif /* USE_32_BIT */
799
800#if SMC_DEBUG > 2
801 printf("Receiving Packet\n");
802 print_packet( NetRxPackets[0], packet_length );
803#endif
804 } else {
805 /* error ... */
806 /* TODO ? */
807 is_error = 1;
808 }
809
Ben Warren7194ab82009-10-04 22:37:03 -0700810 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000811 udelay(1); /* Wait until not busy */
812
813 /* error or good, tell the card to get rid of this packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700814 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000815
Ben Warren7194ab82009-10-04 22:37:03 -0700816 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000817 udelay(1); /* Wait until not busy */
818
wdenk518e2e12004-03-25 14:59:05 +0000819 /* restore saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000820#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700821 SMC_outb( dev, saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000822#else
823 /* On Xaeniax board, we can't use SMC_outb here because that way
824 * the Allocate MMU command will end up written to the command register
825 * as well, which will lead to a problem.
826 */
Ben Warren7194ab82009-10-04 22:37:03 -0700827 SMC_outl( dev, saved_pnr << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000828#endif
Ben Warren7194ab82009-10-04 22:37:03 -0700829 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000830
wdenkfe8c2802002-11-03 00:38:21 +0000831 if (!is_error) {
832 /* Pass the packet up to the protocol layers. */
833 NetReceive(NetRxPackets[0], packet_length);
834 return packet_length;
835 } else {
836 return 0;
837 }
838
839}
840
841
wdenkfe8c2802002-11-03 00:38:21 +0000842#if 0
843/*------------------------------------------------------------
844 . Modify a bit in the LAN91C111 register set
845 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700846static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
wdenkfe8c2802002-11-03 00:38:21 +0000847 unsigned int bit, int val)
848{
849 word regval;
850
Ben Warren7194ab82009-10-04 22:37:03 -0700851 SMC_SELECT_BANK( dev, bank );
wdenkfe8c2802002-11-03 00:38:21 +0000852
Ben Warren7194ab82009-10-04 22:37:03 -0700853 regval = SMC_inw( dev, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000854 if (val)
855 regval |= bit;
856 else
857 regval &= ~bit;
858
Ben Warren7194ab82009-10-04 22:37:03 -0700859 SMC_outw( dev, regval, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000860 return(regval);
861}
862
863
864/*------------------------------------------------------------
865 . Retrieve a bit in the LAN91C111 register set
866 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700867static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
wdenkfe8c2802002-11-03 00:38:21 +0000868{
Ben Warren7194ab82009-10-04 22:37:03 -0700869 SMC_SELECT_BANK( dev, bank );
870 if ( SMC_inw( dev, reg ) & bit)
wdenkfe8c2802002-11-03 00:38:21 +0000871 return(1);
872 else
873 return(0);
874}
875
876
877/*------------------------------------------------------------
878 . Modify a LAN91C111 register (word access only)
879 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700880static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
wdenkfe8c2802002-11-03 00:38:21 +0000881{
Ben Warren7194ab82009-10-04 22:37:03 -0700882 SMC_SELECT_BANK( dev, bank );
883 SMC_outw( dev, val, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000884}
885
886
887/*------------------------------------------------------------
888 . Retrieve a LAN91C111 register (word access only)
889 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700890static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
wdenkfe8c2802002-11-03 00:38:21 +0000891{
Ben Warren7194ab82009-10-04 22:37:03 -0700892 SMC_SELECT_BANK( dev, bank );
893 return(SMC_inw( dev, reg ));
wdenkfe8c2802002-11-03 00:38:21 +0000894}
895
896#endif /* 0 */
897
898/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
899
900#if (SMC_DEBUG > 2 )
901
902/*------------------------------------------------------------
903 . Debugging function for viewing MII Management serial bitstream
904 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +0000905static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +0000906{
907 int i;
908
wdenkb56ddc62003-09-15 21:14:37 +0000909 printf ("BIT#:");
910 for (i = 0; i < size; ++i) {
911 printf ("%d", i % 10);
912 }
wdenkfe8c2802002-11-03 00:38:21 +0000913
wdenkb56ddc62003-09-15 21:14:37 +0000914 printf ("\nMDOE:");
915 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000916 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +0000917 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000918 else
wdenkb56ddc62003-09-15 21:14:37 +0000919 printf ("0");
920 }
wdenkfe8c2802002-11-03 00:38:21 +0000921
wdenkb56ddc62003-09-15 21:14:37 +0000922 printf ("\nMDO :");
923 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000924 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +0000925 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000926 else
wdenkb56ddc62003-09-15 21:14:37 +0000927 printf ("0");
928 }
wdenkfe8c2802002-11-03 00:38:21 +0000929
wdenkb56ddc62003-09-15 21:14:37 +0000930 printf ("\nMDI :");
931 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000932 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +0000933 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000934 else
wdenkb56ddc62003-09-15 21:14:37 +0000935 printf ("0");
936 }
wdenkfe8c2802002-11-03 00:38:21 +0000937
wdenkb56ddc62003-09-15 21:14:37 +0000938 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +0000939}
940#endif
941
942/*------------------------------------------------------------
943 . Reads a register from the MII Management serial interface
944 .-------------------------------------------------------------*/
945#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700946static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +0000947{
948 int oldBank;
949 int i;
950 byte mask;
951 word mii_reg;
952 byte bits[64];
953 int clk_idx = 0;
954 int input_idx;
955 word phydata;
956 byte phyaddr = SMC_PHY_ADDR;
957
958 /* 32 consecutive ones on MDO to establish sync */
959 for (i = 0; i < 32; ++i)
960 bits[clk_idx++] = MII_MDOE | MII_MDO;
961
962 /* Start code <01> */
963 bits[clk_idx++] = MII_MDOE;
964 bits[clk_idx++] = MII_MDOE | MII_MDO;
965
966 /* Read command <10> */
967 bits[clk_idx++] = MII_MDOE | MII_MDO;
968 bits[clk_idx++] = MII_MDOE;
969
970 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000971 mask = (byte) 0x10;
972 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000973 if (phyaddr & mask)
974 bits[clk_idx++] = MII_MDOE | MII_MDO;
975 else
976 bits[clk_idx++] = MII_MDOE;
977
978 /* Shift to next lowest bit */
979 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000980 }
wdenkfe8c2802002-11-03 00:38:21 +0000981
982 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000983 mask = (byte) 0x10;
984 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000985 if (phyreg & mask)
986 bits[clk_idx++] = MII_MDOE | MII_MDO;
987 else
988 bits[clk_idx++] = MII_MDOE;
989
990 /* Shift to next lowest bit */
991 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000992 }
wdenkfe8c2802002-11-03 00:38:21 +0000993
994 /* Tristate and turnaround (2 bit times) */
995 bits[clk_idx++] = 0;
996 /*bits[clk_idx++] = 0; */
997
998 /* Input starts at this bit time */
999 input_idx = clk_idx;
1000
1001 /* Will input 16 bits */
1002 for (i = 0; i < 16; ++i)
1003 bits[clk_idx++] = 0;
1004
1005 /* Final clock bit */
1006 bits[clk_idx++] = 0;
1007
1008 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -07001009 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001010
1011 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -07001012 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +00001013
1014 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001015 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001016
1017 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001018 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001019
1020 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001021 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001022 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001023 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001024 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001025
1026
1027 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001028 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001029 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001030 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001031 }
wdenkfe8c2802002-11-03 00:38:21 +00001032
1033 /* Return to idle state */
1034 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001035 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001036 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001037
1038 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001039 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001040
1041 /* Recover input data */
1042 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +00001043 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001044 phydata <<= 1;
1045
1046 if (bits[input_idx++] & MII_MDI)
1047 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +00001048 }
wdenkfe8c2802002-11-03 00:38:21 +00001049
1050#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001051 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001052 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001053 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001054#endif
1055
wdenkb56ddc62003-09-15 21:14:37 +00001056 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +00001057}
1058
1059
1060/*------------------------------------------------------------
1061 . Writes a register to the MII Management serial interface
1062 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -07001063static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1064 word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001065{
1066 int oldBank;
1067 int i;
1068 word mask;
1069 word mii_reg;
1070 byte bits[65];
1071 int clk_idx = 0;
1072 byte phyaddr = SMC_PHY_ADDR;
1073
1074 /* 32 consecutive ones on MDO to establish sync */
1075 for (i = 0; i < 32; ++i)
1076 bits[clk_idx++] = MII_MDOE | MII_MDO;
1077
1078 /* Start code <01> */
1079 bits[clk_idx++] = MII_MDOE;
1080 bits[clk_idx++] = MII_MDOE | MII_MDO;
1081
1082 /* Write command <01> */
1083 bits[clk_idx++] = MII_MDOE;
1084 bits[clk_idx++] = MII_MDOE | MII_MDO;
1085
1086 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001087 mask = (byte) 0x10;
1088 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001089 if (phyaddr & mask)
1090 bits[clk_idx++] = MII_MDOE | MII_MDO;
1091 else
1092 bits[clk_idx++] = MII_MDOE;
1093
1094 /* Shift to next lowest bit */
1095 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001096 }
wdenkfe8c2802002-11-03 00:38:21 +00001097
1098 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001099 mask = (byte) 0x10;
1100 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001101 if (phyreg & mask)
1102 bits[clk_idx++] = MII_MDOE | MII_MDO;
1103 else
1104 bits[clk_idx++] = MII_MDOE;
1105
1106 /* Shift to next lowest bit */
1107 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001108 }
wdenkfe8c2802002-11-03 00:38:21 +00001109
1110 /* Tristate and turnaround (2 bit times) */
1111 bits[clk_idx++] = 0;
1112 bits[clk_idx++] = 0;
1113
1114 /* Write out 16 bits of data, msb first */
1115 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001116 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001117 if (phydata & mask)
1118 bits[clk_idx++] = MII_MDOE | MII_MDO;
1119 else
1120 bits[clk_idx++] = MII_MDOE;
1121
1122 /* Shift to next lowest bit */
1123 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001124 }
wdenkfe8c2802002-11-03 00:38:21 +00001125
1126 /* Final clock bit (tristate) */
1127 bits[clk_idx++] = 0;
1128
1129 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -07001130 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001131
1132 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -07001133 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +00001134
1135 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001136 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001137
1138 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001139 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001140
1141 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001142 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001143 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001144 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001145 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001146
1147
1148 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001149 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001150 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001151 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001152 }
wdenkfe8c2802002-11-03 00:38:21 +00001153
1154 /* Return to idle state */
1155 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001156 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001157 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001158
1159 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001160 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001161
1162#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001163 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001164 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001165 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001166#endif
1167}
1168#endif /* !CONFIG_SMC91111_EXT_PHY */
1169
1170
wdenkfe8c2802002-11-03 00:38:21 +00001171/*------------------------------------------------------------
1172 . Waits the specified number of milliseconds - kernel friendly
1173 .-------------------------------------------------------------*/
1174#ifndef CONFIG_SMC91111_EXT_PHY
1175static void smc_wait_ms(unsigned int ms)
1176{
1177 udelay(ms*1000);
1178}
1179#endif /* !CONFIG_SMC91111_EXT_PHY */
1180
1181
wdenkfe8c2802002-11-03 00:38:21 +00001182/*------------------------------------------------------------
1183 . Configures the specified PHY using Autonegotiation. Calls
1184 . smc_phy_fixed() if the user has requested a certain config.
1185 .-------------------------------------------------------------*/
1186#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -07001187static void smc_phy_configure (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +00001188{
1189 int timeout;
1190 byte phyaddr;
wdenkb56ddc62003-09-15 21:14:37 +00001191 word my_phy_caps; /* My PHY capabilities */
1192 word my_ad_caps; /* My Advertised capabilities */
1193 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001194 int failed = 0;
1195
wdenkf39748a2004-06-09 13:37:52 +00001196 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001197
1198
wdenkfe8c2802002-11-03 00:38:21 +00001199 /* Get the detected phy address */
1200 phyaddr = SMC_PHY_ADDR;
1201
1202 /* Reset the PHY, setting all other bits to zero */
Ben Warren7194ab82009-10-04 22:37:03 -07001203 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001204
1205 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001206 timeout = 6; /* Wait up to 3 seconds */
1207 while (timeout--) {
Ben Warren7194ab82009-10-04 22:37:03 -07001208 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
wdenkb56ddc62003-09-15 21:14:37 +00001209 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001210 /* reset complete */
1211 break;
wdenkfe8c2802002-11-03 00:38:21 +00001212 }
1213
wdenkb56ddc62003-09-15 21:14:37 +00001214 smc_wait_ms (500); /* wait 500 millisecs */
1215 }
1216
1217 if (timeout < 1) {
1218 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001219 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001220 }
wdenkfe8c2802002-11-03 00:38:21 +00001221
1222 /* Read PHY Register 18, Status Output */
1223 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1224
1225 /* Enable PHY Interrupts (for register 18) */
1226 /* Interrupts listed here are disabled */
Ben Warren7194ab82009-10-04 22:37:03 -07001227 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001228
1229 /* Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001230 SMC_SELECT_BANK (dev, 0);
1231 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001232
1233 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
Ben Warren7194ab82009-10-04 22:37:03 -07001234 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001235 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001236
1237 if (my_phy_caps & PHY_STAT_CAP_T4)
1238 my_ad_caps |= PHY_AD_T4;
1239
1240 if (my_phy_caps & PHY_STAT_CAP_TXF)
1241 my_ad_caps |= PHY_AD_TX_FDX;
1242
1243 if (my_phy_caps & PHY_STAT_CAP_TXH)
1244 my_ad_caps |= PHY_AD_TX_HDX;
1245
1246 if (my_phy_caps & PHY_STAT_CAP_TF)
1247 my_ad_caps |= PHY_AD_10_FDX;
1248
1249 if (my_phy_caps & PHY_STAT_CAP_TH)
1250 my_ad_caps |= PHY_AD_10_HDX;
1251
1252 /* Update our Auto-Neg Advertisement Register */
Ben Warren7194ab82009-10-04 22:37:03 -07001253 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001254
wdenk518e2e12004-03-25 14:59:05 +00001255 /* Read the register back. Without this, it appears that when */
1256 /* auto-negotiation is restarted, sometimes it isn't ready and */
1257 /* the link does not come up. */
Ben Warren7194ab82009-10-04 22:37:03 -07001258 smc_read_phy_register(dev, PHY_AD_REG);
wdenk518e2e12004-03-25 14:59:05 +00001259
wdenkf39748a2004-06-09 13:37:52 +00001260 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1261 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001262
1263 /* Restart auto-negotiation process in order to advertise my caps */
Ben Warren7194ab82009-10-04 22:37:03 -07001264 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001265 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001266
1267 /* Wait for the auto-negotiation to complete. This may take from */
1268 /* 2 to 3 seconds. */
1269 /* Wait for the reset to complete, or time out */
wdenkf39748a2004-06-09 13:37:52 +00001270 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
wdenkb56ddc62003-09-15 21:14:37 +00001271 while (timeout--) {
wdenkf39748a2004-06-09 13:37:52 +00001272
Ben Warren7194ab82009-10-04 22:37:03 -07001273 status = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001274 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001275 /* auto-negotiate complete */
1276 break;
wdenkb56ddc62003-09-15 21:14:37 +00001277 }
wdenkfe8c2802002-11-03 00:38:21 +00001278
wdenkb56ddc62003-09-15 21:14:37 +00001279 smc_wait_ms (500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001280
1281 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001282 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001283 printf ("%s: PHY remote fault detected\n",
wdenkb56ddc62003-09-15 21:14:37 +00001284 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001285
1286 /* Restart auto-negotiation */
wdenkf39748a2004-06-09 13:37:52 +00001287 printf ("%s: PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001288 SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -07001289 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001290 PHY_CNTL_ANEG_EN |
1291 PHY_CNTL_ANEG_RST |
1292 PHY_CNTL_SPEED |
1293 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001294 }
wdenkb56ddc62003-09-15 21:14:37 +00001295 }
wdenkfe8c2802002-11-03 00:38:21 +00001296
wdenkb56ddc62003-09-15 21:14:37 +00001297 if (timeout < 1) {
wdenkf39748a2004-06-09 13:37:52 +00001298 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001299 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001300 }
wdenkfe8c2802002-11-03 00:38:21 +00001301
1302 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001303 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001304 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001305 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001306 }
wdenkfe8c2802002-11-03 00:38:21 +00001307
1308 /* Re-Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001309 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001310
wdenk26238132004-07-09 22:51:01 +00001311smc_phy_configure_exit: ;
wdenkfe8c2802002-11-03 00:38:21 +00001312
1313}
1314#endif /* !CONFIG_SMC91111_EXT_PHY */
1315
1316
1317#if SMC_DEBUG > 2
1318static void print_packet( byte * buf, int length )
1319{
wdenk8bde7f72003-06-27 21:31:46 +00001320 int i;
1321 int remainder;
1322 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001323
wdenk8bde7f72003-06-27 21:31:46 +00001324 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001325
1326#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001327 lines = length / 16;
1328 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001329
wdenk8bde7f72003-06-27 21:31:46 +00001330 for ( i = 0; i < lines ; i ++ ) {
1331 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001332
wdenk8bde7f72003-06-27 21:31:46 +00001333 for ( cur = 0; cur < 8; cur ++ ) {
1334 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001335
wdenk8bde7f72003-06-27 21:31:46 +00001336 a = *(buf ++ );
1337 b = *(buf ++ );
1338 printf("%02x%02x ", a, b );
1339 }
1340 printf("\n");
1341 }
1342 for ( i = 0; i < remainder/2 ; i++ ) {
1343 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001344
wdenk8bde7f72003-06-27 21:31:46 +00001345 a = *(buf ++ );
1346 b = *(buf ++ );
1347 printf("%02x%02x ", a, b );
1348 }
1349 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001350#endif
wdenkfe8c2802002-11-03 00:38:21 +00001351}
1352#endif
1353
Ben Warren7194ab82009-10-04 22:37:03 -07001354int smc91111_initialize(u8 dev_num, int base_addr)
wdenk0b97ab12003-06-19 23:58:30 +00001355{
Ben Warren7194ab82009-10-04 22:37:03 -07001356 struct smc91111_priv *priv;
1357 struct eth_device *dev;
wdenk3d3befa2004-03-14 15:06:13 +00001358 int i;
wdenkf39748a2004-06-09 13:37:52 +00001359
Ben Warren7194ab82009-10-04 22:37:03 -07001360 priv = malloc(sizeof(*priv));
1361 if (!priv)
1362 return 0;
1363 dev = malloc(sizeof(*dev));
1364 if (!dev) {
1365 free(priv);
1366 return 0;
wdenkb56ddc62003-09-15 21:14:37 +00001367 }
wdenkf39748a2004-06-09 13:37:52 +00001368
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001369 memset(dev, 0, sizeof(*dev));
Ben Warren7194ab82009-10-04 22:37:03 -07001370 priv->dev_num = dev_num;
1371 dev->priv = priv;
1372 dev->iobase = base_addr;
1373
1374 swap_to(ETHERNET);
1375 SMC_SELECT_BANK(dev, 1);
1376 for (i = 0; i < 6; ++i)
1377 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1378 swap_to(FLASH);
1379
1380 dev->init = smc_init;
1381 dev->halt = smc_halt;
1382 dev->send = smc_send;
1383 dev->recv = smc_rcv;
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001384 dev->write_hwaddr = smc_write_hwaddr;
Ben Warren7194ab82009-10-04 22:37:03 -07001385 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1386
1387 eth_register(dev);
1388 return 0;
wdenk0b97ab12003-06-19 23:58:30 +00001389}