blob: 3d180db7498b7d0f9bf186035c6f11d4ef6d0437 [file] [log] [blame]
wdenk945af8d2003-07-16 21:53:01 +00001/*
Detlev Zundel6f5f89f2010-04-01 14:16:41 +02002 * (C) Copyright 2003-2010
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
Ben Warren80b00af2008-08-28 23:58:29 -070011#include <mpc5xxx_sdma.h>
wdenk945af8d2003-07-16 21:53:01 +000012#include <malloc.h>
13#include <net.h>
Ben Warrene1d74802008-08-31 10:39:12 -070014#include <netdev.h>
wdenk945af8d2003-07-16 21:53:01 +000015#include <miiphy.h>
Ben Warren80b00af2008-08-28 23:58:29 -070016#include "mpc5xxx_fec.h"
wdenk945af8d2003-07-16 21:53:01 +000017
Wolfgang Denkd87080b2006-03-31 18:32:53 +020018DECLARE_GLOBAL_DATA_PTR;
19
wdenk77846742003-07-26 08:08:08 +000020/* #define DEBUG 0x28 */
wdenk945af8d2003-07-16 21:53:01 +000021
Jon Loeliger44312832007-07-09 19:06:00 -050022#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Marian Balakowicz63ff0042005-10-28 22:30:33 +020023#error "CONFIG_MII has to be defined!"
24#endif
25
wdenk945af8d2003-07-16 21:53:01 +000026#if (DEBUG & 0x60)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020027static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
wdenk945af8d2003-07-16 21:53:01 +000029#endif /* DEBUG */
30
wdenk77846742003-07-26 08:08:08 +000031typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36} NBUF;
37
Mike Frysinger5700bb62010-07-27 18:35:08 -040038int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
39int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
Marian Balakowicz63ff0042005-10-28 22:30:33 +020040
Sascha Hauerf5cf2ef2009-03-21 09:38:46 -040041static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
42
wdenk945af8d2003-07-16 21:53:01 +000043/********************************************************************/
wdenkd4ca31c2004-01-02 14:00:00 +000044#if (DEBUG & 0x2)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020045static void mpc5xxx_fec_phydump (char *devname)
wdenkd4ca31c2004-01-02 14:00:00 +000046{
47 uint16 phyStatus, i;
48 uint8 phyAddr = CONFIG_PHY_ADDR;
49 uint8 reg_mask[] = {
50#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
51 /* regs to print: 0...7, 16...19, 21, 23, 24 */
52 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
53 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
54#else
55 /* regs to print: 0...8, 16...20 */
56 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
58#endif
59 };
60
61 for (i = 0; i < 32; i++) {
62 if (reg_mask[i]) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +020063 miiphy_read(devname, phyAddr, i, &phyStatus);
wdenkd4ca31c2004-01-02 14:00:00 +000064 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
65 }
66 }
67}
68#endif
69
70/********************************************************************/
wdenk945af8d2003-07-16 21:53:01 +000071static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
72{
73 int ix;
74 char *data;
wdenk77846742003-07-26 08:08:08 +000075 static int once = 0;
wdenk945af8d2003-07-16 21:53:01 +000076
wdenk945af8d2003-07-16 21:53:01 +000077 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
wdenk77846742003-07-26 08:08:08 +000078 if (!once) {
79 data = (char *)malloc(FEC_MAX_PKT_SIZE);
80 if (data == NULL) {
81 printf ("RBD INIT FAILED\n");
82 return -1;
83 }
84 fec->rbdBase[ix].dataPointer = (uint32)data;
wdenk945af8d2003-07-16 21:53:01 +000085 }
86 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
87 fec->rbdBase[ix].dataLength = 0;
wdenk945af8d2003-07-16 21:53:01 +000088 }
wdenk77846742003-07-26 08:08:08 +000089 once ++;
wdenk945af8d2003-07-16 21:53:01 +000090
91 /*
92 * have the last RBD to close the ring
93 */
94 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
95 fec->rbdIndex = 0;
96
97 return 0;
98}
99
100/********************************************************************/
101static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
102{
103 int ix;
104
105 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
106 fec->tbdBase[ix].status = 0;
107 }
108
109 /*
110 * Have the last TBD to close the ring
111 */
112 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
113
114 /*
115 * Initialize some indices
116 */
117 fec->tbdIndex = 0;
118 fec->usedTbdIndex = 0;
119 fec->cleanTbdNum = FEC_TBD_NUM;
120}
121
122/********************************************************************/
wdenk151ab832005-02-24 22:44:16 +0000123static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
wdenk945af8d2003-07-16 21:53:01 +0000124{
125 /*
126 * Reset buffer descriptor as empty
127 */
128 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
129 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
130 else
131 pRbd->status = FEC_RBD_EMPTY;
132
133 pRbd->dataLength = 0;
134
135 /*
136 * Now, we have an empty RxBD, restart the SmartDMA receive task
137 */
138 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
139
140 /*
141 * Increment BD count
142 */
143 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
144}
145
146/********************************************************************/
147static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
148{
wdenk151ab832005-02-24 22:44:16 +0000149 volatile FEC_TBD *pUsedTbd;
wdenk945af8d2003-07-16 21:53:01 +0000150
151#if (DEBUG & 0x1)
152 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
153 fec->cleanTbdNum, fec->usedTbdIndex);
154#endif
155
156 /*
157 * process all the consumed TBDs
158 */
159 while (fec->cleanTbdNum < FEC_TBD_NUM) {
160 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
161 if (pUsedTbd->status & FEC_TBD_READY) {
162#if (DEBUG & 0x20)
163 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
164#endif
165 return;
166 }
167
168 /*
169 * clean this buffer descriptor
170 */
171 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
172 pUsedTbd->status = FEC_TBD_WRAP;
173 else
174 pUsedTbd->status = 0;
175
176 /*
177 * update some indeces for a correct handling of the TBD ring
178 */
179 fec->cleanTbdNum++;
180 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
181 }
182}
183
184/********************************************************************/
185static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
186{
187 uint8 currByte; /* byte for which to compute the CRC */
188 int byte; /* loop - counter */
189 int bit; /* loop - counter */
190 uint32 crc = 0xffffffff; /* initial value */
191
192 /*
193 * The algorithm used is the following:
194 * we loop on each of the six bytes of the provided address,
195 * and we compute the CRC by left-shifting the previous
196 * value by one position, so that each bit in the current
197 * byte of the address may contribute the calculation. If
198 * the latter and the MSB in the CRC are different, then
199 * the CRC value so computed is also ex-ored with the
200 * "polynomium generator". The current byte of the address
201 * is also shifted right by one bit at each iteration.
202 * This is because the CRC generatore in hardware is implemented
203 * as a shift-register with as many ex-ores as the radixes
204 * in the polynomium. This suggests that we represent the
205 * polynomiumm itself as a 32-bit constant.
206 */
207 for (byte = 0; byte < 6; byte++) {
208 currByte = mac[byte];
209 for (bit = 0; bit < 8; bit++) {
210 if ((currByte & 0x01) ^ (crc & 0x01)) {
211 crc >>= 1;
212 crc = crc ^ 0xedb88320;
213 } else {
214 crc >>= 1;
215 }
216 currByte >>= 1;
217 }
218 }
219
220 crc = crc >> 26;
221
222 /*
223 * Set individual hash table register
224 */
225 if (crc >= 32) {
226 fec->eth->iaddr1 = (1 << (crc - 32));
227 fec->eth->iaddr2 = 0;
228 } else {
229 fec->eth->iaddr1 = 0;
230 fec->eth->iaddr2 = (1 << crc);
231 }
232
233 /*
234 * Set physical address
235 */
236 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
237 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
238}
239
240/********************************************************************/
241static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
242{
243 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
244 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
wdenk945af8d2003-07-16 21:53:01 +0000245
246#if (DEBUG & 0x1)
247 printf ("mpc5xxx_fec_init... Begin\n");
248#endif
249
Sascha Hauerf5cf2ef2009-03-21 09:38:46 -0400250 mpc5xxx_fec_init_phy(dev, bis);
251
wdenk945af8d2003-07-16 21:53:01 +0000252 /*
Ilya Yanokf87a6f22010-08-19 11:09:06 +0200253 * Call board-specific PHY fixups (if any)
254 */
255#ifdef CONFIG_RESET_PHY_R
256 reset_phy();
257#endif
258
259 /*
wdenk945af8d2003-07-16 21:53:01 +0000260 * Initialize RxBD/TxBD rings
261 */
262 mpc5xxx_fec_rbd_init(fec);
263 mpc5xxx_fec_tbd_init(fec);
264
265 /*
wdenk945af8d2003-07-16 21:53:01 +0000266 * Clear FEC-Lite interrupt event register(IEVENT)
267 */
268 fec->eth->ievent = 0xffffffff;
269
270 /*
271 * Set interrupt mask register
272 */
273 fec->eth->imask = 0x00000000;
274
275 /*
276 * Set FEC-Lite receive control register(R_CNTRL):
277 */
278 if (fec->xcv_type == SEVENWIRE) {
279 /*
280 * Frame length=1518; 7-wire mode
281 */
282 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
283 } else {
284 /*
285 * Frame length=1518; MII mode;
286 */
287 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
288 }
289
wdenk7e780362004-04-08 22:31:29 +0000290 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
wdenk945af8d2003-07-16 21:53:01 +0000291
292 /*
293 * Set Opcode/Pause Duration Register
294 */
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100295 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
wdenk945af8d2003-07-16 21:53:01 +0000296
297 /*
298 * Set Rx FIFO alarm and granularity value
299 */
Wolfgang Denkc44ffb92005-09-04 23:19:41 +0200300 fec->eth->rfifo_cntrl = 0x0c000000
301 | (fec->eth->rfifo_cntrl & ~0x0f000000);
wdenk945af8d2003-07-16 21:53:01 +0000302 fec->eth->rfifo_alarm = 0x0000030c;
303#if (DEBUG & 0x22)
304 if (fec->eth->rfifo_status & 0x00700000 ) {
305 printf("mpc5xxx_fec_init() RFIFO error\n");
306 }
307#endif
308
309 /*
310 * Set Tx FIFO granularity value
311 */
Wolfgang Denkc44ffb92005-09-04 23:19:41 +0200312 fec->eth->tfifo_cntrl = 0x0c000000
313 | (fec->eth->tfifo_cntrl & ~0x0f000000);
wdenk945af8d2003-07-16 21:53:01 +0000314#if (DEBUG & 0x2)
315 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
316 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
317#endif
318
319 /*
320 * Set transmit fifo watermark register(X_WMRK), default = 64
321 */
322 fec->eth->tfifo_alarm = 0x00000080;
323 fec->eth->x_wmrk = 0x2;
324
325 /*
326 * Set individual address filter for unicast address
327 * and set physical address registers.
328 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200329 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
wdenk945af8d2003-07-16 21:53:01 +0000330
331 /*
332 * Set multicast address filter
333 */
334 fec->eth->gaddr1 = 0x00000000;
335 fec->eth->gaddr2 = 0x00000000;
336
337 /*
338 * Turn ON cheater FSM: ????
339 */
340 fec->eth->xmit_fsm = 0x03000000;
341
wdenk945af8d2003-07-16 21:53:01 +0000342 /*
Detlev Zundelfd428c02010-03-12 10:01:12 +0100343 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
wdenk945af8d2003-07-16 21:53:01 +0000344 * work w/ the current receive task.
345 */
346 sdma->PtdCntrl |= 0x00000001;
wdenk945af8d2003-07-16 21:53:01 +0000347
348 /*
349 * Set priority of different initiators
350 */
351 sdma->IPR0 = 7; /* always */
352 sdma->IPR3 = 6; /* Eth RX */
353 sdma->IPR4 = 5; /* Eth Tx */
354
355 /*
356 * Clear SmartDMA task interrupt pending bits
357 */
358 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
359
360 /*
wdenk945af8d2003-07-16 21:53:01 +0000361 * Initialize SmartDMA parameters stored in SRAM
362 */
wdenk151ab832005-02-24 22:44:16 +0000363 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
364 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
365 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
366 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
wdenk945af8d2003-07-16 21:53:01 +0000367
wdenk6c1362c2004-05-12 22:18:31 +0000368 /*
369 * Enable FEC-Lite controller
370 */
371 fec->eth->ecntrl |= 0x00000006;
372
373#if (DEBUG & 0x2)
374 if (fec->xcv_type != SEVENWIRE)
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100375 mpc5xxx_fec_phydump (dev->name);
wdenk6c1362c2004-05-12 22:18:31 +0000376#endif
377
378 /*
379 * Enable SmartDMA receive task
380 */
381 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
382
383#if (DEBUG & 0x1)
384 printf("mpc5xxx_fec_init... Done \n");
385#endif
386
387 return 1;
388}
389
390/********************************************************************/
391static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
392{
wdenk6c1362c2004-05-12 22:18:31 +0000393 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
394 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
Sascha Hauerf5cf2ef2009-03-21 09:38:46 -0400395 static int initialized = 0;
396
397 if(initialized)
398 return 0;
399 initialized = 1;
wdenk6c1362c2004-05-12 22:18:31 +0000400
401#if (DEBUG & 0x1)
402 printf ("mpc5xxx_fec_init_phy... Begin\n");
403#endif
404
405 /*
406 * Initialize GPIO pins
407 */
408 if (fec->xcv_type == SEVENWIRE) {
409 /* 10MBit with 7-wire operation */
wdenk6c7a1402004-07-11 19:17:20 +0000410#if defined(CONFIG_TOTAL5200)
411 /* 7-wire and USB2 on Ethernet */
412 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
413#else /* !CONFIG_TOTAL5200 */
414 /* 7-wire only */
wdenk6c1362c2004-05-12 22:18:31 +0000415 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
wdenk6c7a1402004-07-11 19:17:20 +0000416#endif /* CONFIG_TOTAL5200 */
wdenk6c1362c2004-05-12 22:18:31 +0000417 } else {
418 /* 100MBit with MD operation */
419 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
420 }
421
422 /*
423 * Clear FEC-Lite interrupt event register(IEVENT)
424 */
425 fec->eth->ievent = 0xffffffff;
426
427 /*
428 * Set interrupt mask register
429 */
430 fec->eth->imask = 0x00000000;
431
Bartlomiej Sieka008861a2007-05-07 22:36:15 +0200432/*
433 * In original Promess-provided code PHY initialization is disabled with the
434 * following comment: "Phy initialization is DISABLED for now. There was a
435 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
436 * PHY initialization for the Motion-PRO board, until a proper fix is found.
437 */
438
wdenk6c1362c2004-05-12 22:18:31 +0000439 if (fec->xcv_type != SEVENWIRE) {
440 /*
441 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
442 * and do not drop the Preamble.
443 */
444 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
445 }
446
wdenk945af8d2003-07-16 21:53:01 +0000447 if (fec->xcv_type != SEVENWIRE) {
448 /*
449 * Initialize PHY(LXT971A):
450 *
451 * Generally, on power up, the LXT971A reads its configuration
452 * pins to check for forced operation, If not cofigured for
453 * forced operation, it uses auto-negotiation/parallel detection
454 * to automatically determine line operating conditions.
455 * If the PHY device on the other side of the link supports
456 * auto-negotiation, the LXT971A auto-negotiates with it
457 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
458 * support auto-negotiation, the LXT971A automatically detects
459 * the presence of either link pulses(10Mbps PHY) or Idle
460 * symbols(100Mbps) and sets its operating conditions accordingly.
461 *
462 * When auto-negotiation is controlled by software, the following
463 * steps are recommended.
464 *
465 * Note:
466 * The physical address is dependent on hardware configuration.
467 *
468 */
469 int timeout = 1;
470 uint16 phyStatus;
471
472 /*
473 * Reset PHY, then delay 300ns
474 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200475 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
wdenk945af8d2003-07-16 21:53:01 +0000476 udelay(1000);
477
Heiko Schocher258c37b2008-08-21 20:44:49 +0200478#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
479 /* Set the LED configuration Register for the UC101
480 and MUCMC52 Board */
Heiko Schocher37403002007-04-14 05:26:48 +0200481 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
482#endif
wdenk945af8d2003-07-16 21:53:01 +0000483 if (fec->xcv_type == MII10) {
484 /*
485 * Force 10Base-T, FDX operation
486 */
wdenka57106f2003-09-16 17:29:31 +0000487#if (DEBUG & 0x2)
wdenk945af8d2003-07-16 21:53:01 +0000488 printf("Forcing 10 Mbps ethernet link... ");
wdenka57106f2003-09-16 17:29:31 +0000489#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200490 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000491 /*
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200492 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
wdenk945af8d2003-07-16 21:53:01 +0000493 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200494 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
wdenk945af8d2003-07-16 21:53:01 +0000495
496 timeout = 20;
497 do { /* wait for link status to go down */
498 udelay(10000);
499 if ((timeout--) == 0) {
500#if (DEBUG & 0x2)
501 printf("hmmm, should not have waited...");
502#endif
503 break;
504 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200505 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000506#if (DEBUG & 0x2)
507 printf("=");
508#endif
509 } while ((phyStatus & 0x0004)); /* !link up */
510
511 timeout = 1000;
512 do { /* wait for link status to come back up */
513 udelay(10000);
514 if ((timeout--) == 0) {
515 printf("failed. Link is down.\n");
516 break;
517 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200518 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000519#if (DEBUG & 0x2)
520 printf("+");
521#endif
522 } while (!(phyStatus & 0x0004)); /* !link up */
523
dzuab209d52003-09-30 14:08:43 +0000524#if (DEBUG & 0x2)
wdenk945af8d2003-07-16 21:53:01 +0000525 printf ("done.\n");
dzuab209d52003-09-30 14:08:43 +0000526#endif
wdenk945af8d2003-07-16 21:53:01 +0000527 } else { /* MII100 */
528 /*
529 * Set the auto-negotiation advertisement register bits
530 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200531 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
wdenk945af8d2003-07-16 21:53:01 +0000532
533 /*
534 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
535 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200536 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
wdenk945af8d2003-07-16 21:53:01 +0000537
538 /*
539 * Wait for AN completion
540 */
541 timeout = 5000;
542 do {
543 udelay(1000);
544
545 if ((timeout--) == 0) {
546#if (DEBUG & 0x2)
547 printf("PHY auto neg 0 failed...\n");
548#endif
549 return -1;
550 }
551
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200552 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
wdenk945af8d2003-07-16 21:53:01 +0000553#if (DEBUG & 0x2)
554 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
555#endif
556 return -1;
557 }
wdenk7e780362004-04-08 22:31:29 +0000558 } while (!(phyStatus & 0x0004));
wdenk945af8d2003-07-16 21:53:01 +0000559
560#if (DEBUG & 0x2)
561 printf("PHY auto neg complete! \n");
562#endif
563 }
564
565 }
566
wdenk945af8d2003-07-16 21:53:01 +0000567#if (DEBUG & 0x2)
wdenkd4ca31c2004-01-02 14:00:00 +0000568 if (fec->xcv_type != SEVENWIRE)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200569 mpc5xxx_fec_phydump (dev->name);
wdenk945af8d2003-07-16 21:53:01 +0000570#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000571
wdenk945af8d2003-07-16 21:53:01 +0000572
573#if (DEBUG & 0x1)
wdenk6c1362c2004-05-12 22:18:31 +0000574 printf("mpc5xxx_fec_init_phy... Done \n");
wdenk945af8d2003-07-16 21:53:01 +0000575#endif
576
wdenk013dc8d2003-08-07 14:52:18 +0000577 return 1;
wdenk945af8d2003-07-16 21:53:01 +0000578}
579
580/********************************************************************/
581static void mpc5xxx_fec_halt(struct eth_device *dev)
582{
wdenk945af8d2003-07-16 21:53:01 +0000583 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
wdenk77846742003-07-26 08:08:08 +0000584 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk945af8d2003-07-16 21:53:01 +0000585 int counter = 0xffff;
586
587#if (DEBUG & 0x2)
wdenkd4ca31c2004-01-02 14:00:00 +0000588 if (fec->xcv_type != SEVENWIRE)
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100589 mpc5xxx_fec_phydump (dev->name);
wdenk945af8d2003-07-16 21:53:01 +0000590#endif
591
wdenk945af8d2003-07-16 21:53:01 +0000592 /*
593 * mask FEC chip interrupts
594 */
595 fec->eth->imask = 0;
596
597 /*
598 * issue graceful stop command to the FEC transmitter if necessary
599 */
600 fec->eth->x_cntrl |= 0x00000001;
601
602 /*
603 * wait for graceful stop to register
604 */
605 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
606
wdenk945af8d2003-07-16 21:53:01 +0000607 /*
608 * Disable SmartDMA tasks
609 */
610 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
611 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
612
wdenk945af8d2003-07-16 21:53:01 +0000613 /*
Detlev Zundelfd428c02010-03-12 10:01:12 +0100614 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
wdenk945af8d2003-07-16 21:53:01 +0000615 * done. It doesn't work w/ the current receive task.
616 */
617 sdma->PtdCntrl &= ~0x00000001;
wdenk945af8d2003-07-16 21:53:01 +0000618
619 /*
620 * Disable the Ethernet Controller
621 */
622 fec->eth->ecntrl &= 0xfffffffd;
623
624 /*
625 * Clear FIFO status registers
626 */
627 fec->eth->rfifo_status &= 0x00700000;
628 fec->eth->tfifo_status &= 0x00700000;
629
630 fec->eth->reset_cntrl = 0x01000000;
631
632 /*
633 * Issue a reset command to the FEC chip
634 */
635 fec->eth->ecntrl |= 0x1;
636
637 /*
638 * wait at least 16 clock cycles
639 */
640 udelay(10);
641
Jon Smirlf949bd82009-03-11 15:08:56 -0400642 /* don't leave the MII speed set to zero */
643 if (fec->xcv_type != SEVENWIRE) {
644 /*
645 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
646 * and do not drop the Preamble.
647 */
648 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
649 }
650
wdenk945af8d2003-07-16 21:53:01 +0000651#if (DEBUG & 0x3)
652 printf("Ethernet task stopped\n");
653#endif
654}
655
656#if (DEBUG & 0x60)
657/********************************************************************/
658
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200659static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
wdenk945af8d2003-07-16 21:53:01 +0000660{
wdenkd4ca31c2004-01-02 14:00:00 +0000661 uint16 phyAddr = CONFIG_PHY_ADDR;
wdenk945af8d2003-07-16 21:53:01 +0000662 uint16 phyStatus;
663
664 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
665 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
666
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200667 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000668 printf("\nphyStatus: 0x%04x\n", phyStatus);
669 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
670 printf("ievent: 0x%08x\n", fec->eth->ievent);
671 printf("x_status: 0x%08x\n", fec->eth->x_status);
672 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
673
674 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
675 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
676 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
677 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
678 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
679 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
680 }
681}
682
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200683static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
wdenk945af8d2003-07-16 21:53:01 +0000684{
wdenkd4ca31c2004-01-02 14:00:00 +0000685 uint16 phyAddr = CONFIG_PHY_ADDR;
wdenk945af8d2003-07-16 21:53:01 +0000686 uint16 phyStatus;
687
688 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
689 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
690
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200691 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000692 printf("\nphyStatus: 0x%04x\n", phyStatus);
693 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
694 printf("ievent: 0x%08x\n", fec->eth->ievent);
695 printf("x_status: 0x%08x\n", fec->eth->x_status);
696 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
697
698 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
699 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
700 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
701 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
702 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
703 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
704 }
705}
706#endif /* DEBUG */
707
708/********************************************************************/
709
Anatolij Gustschin2f2c29a2012-05-20 12:22:57 +0000710static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
wdenk945af8d2003-07-16 21:53:01 +0000711 int data_length)
712{
713 /*
714 * This routine transmits one frame. This routine only accepts
715 * 6-byte Ethernet addresses.
716 */
717 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk151ab832005-02-24 22:44:16 +0000718 volatile FEC_TBD *pTbd;
wdenk945af8d2003-07-16 21:53:01 +0000719
720#if (DEBUG & 0x20)
721 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200722 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000723#endif
724
725 /*
726 * Clear Tx BD ring at first
727 */
728 mpc5xxx_fec_tbd_scrub(fec);
729
730 /*
731 * Check for valid length of data.
732 */
733 if ((data_length > 1500) || (data_length <= 0)) {
734 return -1;
735 }
736
737 /*
738 * Check the number of vacant TxBDs.
739 */
740 if (fec->cleanTbdNum < 1) {
741#if (DEBUG & 0x20)
742 printf("No available TxBDs ...\n");
743#endif
744 return -1;
745 }
746
747 /*
748 * Get the first TxBD to send the mac header
749 */
750 pTbd = &fec->tbdBase[fec->tbdIndex];
751 pTbd->dataLength = data_length;
752 pTbd->dataPointer = (uint32)eth_data;
wdenk77846742003-07-26 08:08:08 +0000753 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
wdenk945af8d2003-07-16 21:53:01 +0000754 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
755
756#if (DEBUG & 0x100)
757 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
758#endif
759
760 /*
761 * Kick the MII i/f
762 */
763 if (fec->xcv_type != SEVENWIRE) {
764 uint16 phyStatus;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200765 miiphy_read(dev->name, 0, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000766 }
767
768 /*
769 * Enable SmartDMA transmit task
770 */
771
772#if (DEBUG & 0x20)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200773 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000774#endif
775 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
776#if (DEBUG & 0x20)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200777 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000778#endif
779#if (DEBUG & 0x8)
780 printf( "+" );
781#endif
782
783 fec->cleanTbdNum -= 1;
784
785#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
786 printf ("smartDMA ethernet Tx task enabled\n");
787#endif
788 /*
789 * wait until frame is sent .
790 */
791 while (pTbd->status & FEC_TBD_READY) {
792 udelay(10);
793#if (DEBUG & 0x8)
794 printf ("TDB status = %04x\n", pTbd->status);
795#endif
796 }
797
798 return 0;
799}
800
801
802/********************************************************************/
803static int mpc5xxx_fec_recv(struct eth_device *dev)
804{
805 /*
806 * This command pulls one frame from the card
807 */
808 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk151ab832005-02-24 22:44:16 +0000809 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
wdenk945af8d2003-07-16 21:53:01 +0000810 unsigned long ievent;
wdenk77846742003-07-26 08:08:08 +0000811 int frame_length, len = 0;
812 NBUF *frame;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200813 uchar buff[FEC_MAX_PKT_SIZE];
wdenk945af8d2003-07-16 21:53:01 +0000814
815#if (DEBUG & 0x1)
816 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
817#endif
818#if (DEBUG & 0x8)
819 printf( "-" );
820#endif
821
822 /*
823 * Check if any critical events have happened
824 */
825 ievent = fec->eth->ievent;
826 fec->eth->ievent = ievent;
827 if (ievent & 0x20060000) {
828 /* BABT, Rx/Tx FIFO errors */
829 mpc5xxx_fec_halt(dev);
830 mpc5xxx_fec_init(dev, NULL);
831 return 0;
832 }
833 if (ievent & 0x80000000) {
834 /* Heartbeat error */
835 fec->eth->x_cntrl |= 0x00000001;
836 }
837 if (ievent & 0x10000000) {
838 /* Graceful stop complete */
839 if (fec->eth->x_cntrl & 0x00000001) {
840 mpc5xxx_fec_halt(dev);
841 fec->eth->x_cntrl &= ~0x00000001;
842 mpc5xxx_fec_init(dev, NULL);
843 }
844 }
845
wdenk77846742003-07-26 08:08:08 +0000846 if (!(pRbd->status & FEC_RBD_EMPTY)) {
847 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
848 ((pRbd->dataLength - 4) > 14)) {
wdenk945af8d2003-07-16 21:53:01 +0000849
wdenk77846742003-07-26 08:08:08 +0000850 /*
851 * Get buffer address and size
852 */
853 frame = (NBUF *)pRbd->dataPointer;
854 frame_length = pRbd->dataLength - 4;
855
856#if (DEBUG & 0x20)
857 {
858 int i;
859 printf("recv data hdr:");
860 for (i = 0; i < 14; i++)
861 printf("%x ", *(frame->head + i));
862 printf("\n");
863 }
wdenk945af8d2003-07-16 21:53:01 +0000864#endif
wdenk77846742003-07-26 08:08:08 +0000865 /*
866 * Fill the buffer and pass it to upper layers
867 */
868 memcpy(buff, frame->head, 14);
869 memcpy(buff + 14, frame->data, frame_length);
870 NetReceive(buff, frame_length);
871 len = frame_length;
872 }
873 /*
874 * Reset buffer descriptor as empty
875 */
876 mpc5xxx_fec_rbd_clean(fec, pRbd);
wdenk945af8d2003-07-16 21:53:01 +0000877 }
wdenk77846742003-07-26 08:08:08 +0000878 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
879 return len;
wdenk945af8d2003-07-16 21:53:01 +0000880}
881
882
883/********************************************************************/
884int mpc5xxx_fec_initialize(bd_t * bis)
885{
886 mpc5xxx_fec_priv *fec;
887 struct eth_device *dev;
wdenk12f34242003-09-02 22:48:03 +0000888 char *tmp, *end;
889 char env_enetaddr[6];
890 int i;
wdenk945af8d2003-07-16 21:53:01 +0000891
892 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
893 dev = (struct eth_device *)malloc(sizeof(*dev));
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200894 memset(dev, 0, sizeof *dev);
wdenk945af8d2003-07-16 21:53:01 +0000895
896 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
897 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
898 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
Ben Warren86321fc2009-02-05 23:58:25 -0800899#if defined(CONFIG_MPC5xxx_FEC_MII100)
wdenk945af8d2003-07-16 21:53:01 +0000900 fec->xcv_type = MII100;
Ben Warren86321fc2009-02-05 23:58:25 -0800901#elif defined(CONFIG_MPC5xxx_FEC_MII10)
wdenka57106f2003-09-16 17:29:31 +0000902 fec->xcv_type = MII10;
Ben Warren86321fc2009-02-05 23:58:25 -0800903#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
wdenk6c7a1402004-07-11 19:17:20 +0000904 fec->xcv_type = SEVENWIRE;
wdenka57106f2003-09-16 17:29:31 +0000905#else
906#error fec->xcv_type not initialized.
wdenk945af8d2003-07-16 21:53:01 +0000907#endif
Jon Smirlf949bd82009-03-11 15:08:56 -0400908 if (fec->xcv_type != SEVENWIRE) {
909 /*
910 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
911 * and do not drop the Preamble.
912 */
913 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
914 }
wdenk945af8d2003-07-16 21:53:01 +0000915
916 dev->priv = (void *)fec;
917 dev->iobase = MPC5XXX_FEC;
918 dev->init = mpc5xxx_fec_init;
919 dev->halt = mpc5xxx_fec_halt;
920 dev->send = mpc5xxx_fec_send;
921 dev->recv = mpc5xxx_fec_recv;
922
Wolfgang Denk82369c02010-08-05 21:31:54 +0200923 sprintf(dev->name, "FEC");
wdenk945af8d2003-07-16 21:53:01 +0000924 eth_register(dev);
925
Jon Loeliger44312832007-07-09 19:06:00 -0500926#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200927 miiphy_register (dev->name,
928 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
929#endif
930
wdenk12f34242003-09-02 22:48:03 +0000931 /*
932 * Try to set the mac address now. The fec mac address is
wdenk42d1f032003-10-15 23:53:47 +0000933 * a garbage after reset. When not using fec for booting
wdenk12f34242003-09-02 22:48:03 +0000934 * the Linux fec driver will try to work with this garbage.
935 */
936 tmp = getenv("ethaddr");
937 if (tmp) {
938 for (i=0; i<6; i++) {
939 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
940 if (tmp)
941 tmp = (*end) ? end+1 : end;
942 }
943 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
944 }
945
wdenk945af8d2003-07-16 21:53:01 +0000946 return 1;
947}
948
949/* MII-interface related functions */
950/********************************************************************/
Mike Frysinger5700bb62010-07-27 18:35:08 -0400951int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
wdenk945af8d2003-07-16 21:53:01 +0000952{
953 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
954 uint32 reg; /* convenient holder for the PHY register */
955 uint32 phy; /* convenient holder for the PHY */
956 int timeout = 0xffff;
957
958 /*
959 * reading from any PHY's register is done by properly
960 * programming the FEC's MII data register.
961 */
962 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
963 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
964
965 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
966
967 /*
968 * wait for the related interrupt
969 */
970 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
971
972 if (timeout == 0) {
973#if (DEBUG & 0x2)
974 printf ("Read MDIO failed...\n");
975#endif
976 return -1;
977 }
978
979 /*
980 * clear mii interrupt bit
981 */
982 eth->ievent = 0x00800000;
983
984 /*
985 * it's now safe to read the PHY's register
986 */
987 *retVal = (uint16) eth->mii_data;
988
989 return 0;
990}
991
992/********************************************************************/
Mike Frysinger5700bb62010-07-27 18:35:08 -0400993int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
wdenk945af8d2003-07-16 21:53:01 +0000994{
995 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
996 uint32 reg; /* convenient holder for the PHY register */
997 uint32 phy; /* convenient holder for the PHY */
998 int timeout = 0xffff;
999
1000 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
1001 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
1002
1003 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1004 FEC_MII_DATA_TA | phy | reg | data);
1005
1006 /*
1007 * wait for the MII interrupt
1008 */
1009 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1010
1011 if (timeout == 0) {
1012#if (DEBUG & 0x2)
1013 printf ("Write MDIO failed...\n");
1014#endif
1015 return -1;
1016 }
1017
1018 /*
1019 * clear MII interrupt bit
1020 */
1021 eth->ievent = 0x00800000;
1022
1023 return 0;
1024}