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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * MPC85xx Internal Memory Map
3 *
Ed Swarthout837f1ba2007-07-27 01:50:51 -05004 * Copyright 2007 Freescale Semiconductor.
5 *
wdenk42d1f032003-10-15 23:53:47 +00006 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
9 */
10
11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
Jon Loeliger3dfa9cf2006-10-20 17:16:35 -050014#include <asm/types.h>
15#include <asm/fsl_i2c.h>
16
Jon Loeligerde1d0a62005-08-01 13:20:47 -050017/*
18 * Local-Access Registers and ECM Registers(0x0000-0x2000)
19 */
wdenk42d1f032003-10-15 23:53:47 +000020typedef struct ccsr_local_ecm {
21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
22 char res1[4];
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
24 char res2[4];
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
26 char res3[12];
27 uint bptr; /* 0x20 - Boot Page Translation Register */
28 char res4[3044];
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
30 char res5[4];
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
32 char res6[20];
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
34 char res7[4];
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
36 char res8[20];
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
38 char res9[4];
39 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
40 char res10[20];
41 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
42 char res11[4];
43 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
44 char res12[20];
45 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
46 char res13[4];
47 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
48 char res14[20];
49 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
50 char res15[4];
51 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
52 char res16[20];
53 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
54 char res17[4];
55 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
56 char res18[20];
57 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
58 char res19[4];
59 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070060 char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
wdenk42d1f032003-10-15 23:53:47 +000061 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
62 char res21[12];
63 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
64 char res22[3564];
65 uint eedr; /* 0x1e00 - ECM Error Detect Register */
66 char res23[4];
67 uint eeer; /* 0x1e08 - ECM Error Enable Register */
68 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
69 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
70 char res24[492];
71} ccsr_local_ecm_t;
72
Jon Loeligerde1d0a62005-08-01 13:20:47 -050073/*
74 * DDR memory controller registers(0x2000-0x3000)
75 */
wdenk42d1f032003-10-15 23:53:47 +000076typedef struct ccsr_ddr {
77 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
78 char res1[4];
79 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
80 char res2[4];
81 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
82 char res3[4];
83 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
84 char res4[100];
85 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
86 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
87 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
88 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
James Yang5893b3d2008-02-12 16:35:07 -060089 char res4a[48];
90 uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
91 uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
92 uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
93 uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
94 char res5[48];
Kumar Gala45239cf2008-04-29 10:27:08 -050095 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050096 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
wdenk42d1f032003-10-15 23:53:47 +000097 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
98 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
99 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500100 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
wdenk42d1f032003-10-15 23:53:47 +0000101 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500102 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
103 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
wdenk42d1f032003-10-15 23:53:47 +0000104 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500105 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
106 char res6[4];
wdenk547b4cb2004-06-09 00:51:50 +0000107 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500108 char res7[20];
Kumar Galaef7d30b2008-04-29 10:28:34 -0500109 uint init_addr; /* 0x2148 - DDR training initialization address */
110 uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
James Yang5893b3d2008-02-12 16:35:07 -0600111 char res8_1[16];
112 uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
113 uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
114 char reg8_1a[8];
115 uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
116 uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
117 uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
118 uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
119 uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
120 uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
121 char res8_1b[2672];
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500122 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
123 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
124 char res8_2[512];
wdenk42d1f032003-10-15 23:53:47 +0000125 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
126 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
127 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
128 char res9[20];
129 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
130 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
131 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
132 char res10[20];
133 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
134 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
135 uint err_int_en; /* 0x2e48 - DDR */
136 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
137 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
138 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
139 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
140 char res11[164];
141 uint debug_1; /* 0x2f00 */
142 uint debug_2;
143 uint debug_3;
144 uint debug_4;
145 char res12[240];
146} ccsr_ddr_t;
147
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500148/*
149 * I2C Registers(0x3000-0x4000)
150 */
wdenk42d1f032003-10-15 23:53:47 +0000151typedef struct ccsr_i2c {
Jon Loeliger3dfa9cf2006-10-20 17:16:35 -0500152 struct fsl_i2c i2c[1];
153 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
wdenk42d1f032003-10-15 23:53:47 +0000154} ccsr_i2c_t;
155
wdenk03f5c552004-10-10 21:21:55 +0000156#if defined(CONFIG_MPC8540) \
157 || defined(CONFIG_MPC8541) \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500158 || defined(CONFIG_MPC8548) \
wdenk03f5c552004-10-10 21:21:55 +0000159 || defined(CONFIG_MPC8555)
wdenk42d1f032003-10-15 23:53:47 +0000160/* DUART Registers(0x4000-0x5000) */
161typedef struct ccsr_duart {
162 char res1[1280];
163 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
164 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
165 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
166 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
167 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
168 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
169 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
170 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
171 char res2[8];
172 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
173 char res3[239];
174 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
175 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
176 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
177 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
178 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
179 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
180 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
181 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
182 char res4[8];
183 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
184 char res5[2543];
185} ccsr_duart_t;
186#else /* MPC8560 uses UART on its CPM */
187typedef struct ccsr_duart {
188 char res[4096];
189} ccsr_duart_t;
190#endif
191
192/* Local Bus Controller Registers(0x5000-0x6000) */
193/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
194
195typedef struct ccsr_lbc {
196 uint br0; /* 0x5000 - LBC Base Register 0 */
197 uint or0; /* 0x5004 - LBC Options Register 0 */
198 uint br1; /* 0x5008 - LBC Base Register 1 */
199 uint or1; /* 0x500c - LBC Options Register 1 */
200 uint br2; /* 0x5010 - LBC Base Register 2 */
201 uint or2; /* 0x5014 - LBC Options Register 2 */
202 uint br3; /* 0x5018 - LBC Base Register 3 */
203 uint or3; /* 0x501c - LBC Options Register 3 */
204 uint br4; /* 0x5020 - LBC Base Register 4 */
205 uint or4; /* 0x5024 - LBC Options Register 4 */
206 uint br5; /* 0x5028 - LBC Base Register 5 */
207 uint or5; /* 0x502c - LBC Options Register 5 */
208 uint br6; /* 0x5030 - LBC Base Register 6 */
209 uint or6; /* 0x5034 - LBC Options Register 6 */
210 uint br7; /* 0x5038 - LBC Base Register 7 */
211 uint or7; /* 0x503c - LBC Options Register 7 */
212 char res1[40];
213 uint mar; /* 0x5068 - LBC UPM Address Register */
214 char res2[4];
215 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
216 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
217 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
218 char res3[8];
219 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
220 uint mdr; /* 0x5088 - LBC UPM Data Register */
221 char res4[8];
222 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
223 char res5[8];
224 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
225 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
226 char res6[8];
227 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
228 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
229 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
230 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
231 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
232 char res7[12];
233 uint lbcr; /* 0x50d0 - LBC Configuration Register */
234 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
James Yang5893b3d2008-02-12 16:35:07 -0600235 char res8[3880];
wdenk42d1f032003-10-15 23:53:47 +0000236} ccsr_lbc_t;
237
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500238/*
239 * PCI Registers(0x8000-0x9000)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500240 */
wdenk42d1f032003-10-15 23:53:47 +0000241typedef struct ccsr_pcix {
242 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
243 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
244 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
245 char res1[3060];
246 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
247 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
248 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
249 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
250 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
251 char res2[12];
252 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
253 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
254 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
255 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
256 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
257 char res3[12];
258 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
259 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
260 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
261 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
262 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
263 char res4[12];
264 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
265 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
266 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
267 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
268 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
269 char res5[12];
270 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
271 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
272 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
273 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
274 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
275 char res6[268];
276 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
277 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
278 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
279 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
280 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
281 char res7[12];
282 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
283 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
284 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
285 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
286 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
287 char res8[12];
288 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
289 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
290 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
291 char res9[4];
292 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
293 char res10[12];
294 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
295 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
296 uint peer; /* 0x8e08 - PCIX Error Enable Register */
297 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
298 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
299 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
300 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
301 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
Matthew McClintock97074ed2006-06-28 10:45:17 -0500302 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
303 char res11[476];
wdenk42d1f032003-10-15 23:53:47 +0000304} ccsr_pcix_t;
305
Matthew McClintock97074ed2006-06-28 10:45:17 -0500306#define PCIX_COMMAND 0x62
307#define POWAR_EN 0x80000000
308#define POWAR_IO_READ 0x00080000
309#define POWAR_MEM_READ 0x00040000
310#define POWAR_IO_WRITE 0x00008000
311#define POWAR_MEM_WRITE 0x00004000
312#define POWAR_MEM_512M 0x0000001c
313#define POWAR_IO_1M 0x00000013
314
315#define PIWAR_EN 0x80000000
316#define PIWAR_PF 0x20000000
317#define PIWAR_LOCAL 0x00f00000
318#define PIWAR_READ_SNOOP 0x00050000
319#define PIWAR_WRITE_SNOOP 0x00005000
320#define PIWAR_MEM_2G 0x0000001e
321
322
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500323/*
324 * L2 Cache Registers(0x2_0000-0x2_1000)
325 */
wdenk42d1f032003-10-15 23:53:47 +0000326typedef struct ccsr_l2cache {
327 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
328 char res1[12];
329 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
330 char res2[4];
331 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
332 char res3[4];
333 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
334 char res4[4];
335 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
336 char res5[4];
337 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
338 char res6[4];
339 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
340 char res7[4];
341 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
342 char res8[4];
343 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
344 char res9[180];
345 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
346 char res10[4];
347 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
348 char res11[3316];
349 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
350 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
351 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
352 char res12[20];
353 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
354 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
355 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
356 char res13[20];
357 uint l2errdet; /* 0x20e40 - L2 error detect register */
358 uint l2errdis; /* 0x20e44 - L2 error disable register */
359 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
360 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
361 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
362 char res14[4];
363 uint l2errctl; /* 0x20e58 - L2 error control register */
364 char res15[420];
365} ccsr_l2cache_t;
366
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500367/*
368 * DMA Registers(0x2_1000-0x2_2000)
369 */
wdenk42d1f032003-10-15 23:53:47 +0000370typedef struct ccsr_dma {
371 char res1[256];
372 uint mr0; /* 0x21100 - DMA 0 Mode Register */
373 uint sr0; /* 0x21104 - DMA 0 Status Register */
374 char res2[4];
375 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
376 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
377 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
378 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
379 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
380 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
381 char res3[4];
382 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
383 char res4[8];
384 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
385 char res5[4];
386 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
387 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
388 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
389 char res6[56];
390 uint mr1; /* 0x21180 - DMA 1 Mode Register */
391 uint sr1; /* 0x21184 - DMA 1 Status Register */
392 char res7[4];
393 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
394 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
395 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
396 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
397 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
398 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
399 char res8[4];
400 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
401 char res9[8];
402 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
403 char res10[4];
404 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
405 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
406 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
407 char res11[56];
408 uint mr2; /* 0x21200 - DMA 2 Mode Register */
409 uint sr2; /* 0x21204 - DMA 2 Status Register */
410 char res12[4];
411 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
412 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
413 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
414 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
415 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
416 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
417 char res13[4];
418 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
419 char res14[8];
420 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
421 char res15[4];
422 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
423 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
424 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
425 char res16[56];
426 uint mr3; /* 0x21280 - DMA 3 Mode Register */
427 uint sr3; /* 0x21284 - DMA 3 Status Register */
428 char res17[4];
429 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
430 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
431 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
432 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
433 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
434 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
435 char res18[4];
436 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
437 char res19[8];
438 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
439 char res20[4];
440 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
441 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
442 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
443 char res21[56];
444 uint dgsr; /* 0x21300 - DMA General Status Register */
445 char res22[11516];
446} ccsr_dma_t;
447
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500448/*
449 * tsec1 tsec2: 24000-26000
450 */
wdenk42d1f032003-10-15 23:53:47 +0000451typedef struct ccsr_tsec {
452 char res1[16];
453 uint ievent; /* 0x24010 - Interrupt Event Register */
454 uint imask; /* 0x24014 - Interrupt Mask Register */
455 uint edis; /* 0x24018 - Error Disabled Register */
456 char res2[4];
457 uint ecntrl; /* 0x24020 - Ethernet Control Register */
458 uint minflr; /* 0x24024 - Minimum Frame Length Register */
459 uint ptv; /* 0x24028 - Pause Time Value Register */
460 uint dmactrl; /* 0x2402c - DMA Control Register */
461 uint tbipa; /* 0x24030 - TBI PHY Address Register */
462 char res3[88];
463 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
464 char res4[8];
465 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
466 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
467 char res5[96];
468 uint tctrl; /* 0x24100 - Transmit Control Register */
469 uint tstat; /* 0x24104 - Transmit Status Register */
470 char res6[4];
471 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
472 char res7[16];
473 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
474 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
475 char res8[88];
476 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
477 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
478 char res9[120];
479 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
480 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
481 char res10[168];
482 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
483 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
484 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
485 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
486 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
487 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
488 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
489 char res11[52];
490 uint rctrl; /* 0x24300 - Receive Control Register */
491 uint rstat; /* 0x24304 - Receive Status Register */
492 char res12[4];
493 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
494 char res13[16];
495 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
496 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
497 char res14[24];
498 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
499 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
500 char res15[56];
501 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
502 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
503 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
504 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
505 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
506 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
507 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
508 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
509 char res16[96];
510 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
511 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
512 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
513 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
514 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
515 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
516 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
517 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
518 char res17[224];
519 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
520 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
521 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
522 uint hafdup; /* 0x2450c - Half Duplex Register */
523 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
524 char res18[12];
525 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
526 uint miimcom; /* 0x24524 - MII Management Command Register */
527 uint miimadd; /* 0x24528 - MII Management Address Register */
528 uint miimcon; /* 0x2452c - MII Management Control Register */
529 uint miimstat; /* 0x24530 - MII Management Status Register */
530 uint miimind; /* 0x24534 - MII Management Indicator Register */
531 char res19[4];
532 uint ifstat; /* 0x2453c - Interface Status Register */
533 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
534 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
535 char res20[312];
536 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
537 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
538 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
539 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
540 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
541 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
542 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
543 uint rbyt; /* 0x2469c - Receive Byte Counter */
544 uint rpkt; /* 0x246a0 - Receive Packet Counter */
545 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
546 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
547 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
548 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
549 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
550 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
551 uint raln; /* 0x246bc - Receive Alignment Error Counter */
552 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
553 uint rcde; /* 0x246c4 - Receive Code Error Counter */
554 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
555 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
556 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
557 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
558 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
559 uint rdrp; /* 0x246dc - Receive Drop Counter */
560 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
561 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
562 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
563 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
564 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
565 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
566 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
567 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
568 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
569 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
570 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
571 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
572 char res21[4];
573 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
574 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
575 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
576 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
577 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
578 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
579 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
580 uint car1; /* 0x24730 - Carry Register One */
581 uint car2; /* 0x24734 - Carry Register Two */
582 uint cam1; /* 0x24738 - Carry Mask Register One */
583 uint cam2; /* 0x2473c - Carry Mask Register Two */
584 char res22[192];
585 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
586 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
587 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
588 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
589 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
590 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
591 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
592 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
593 char res23[96];
594 uint gaddr0; /* 0x24880 - Global address register 0 */
595 uint gaddr1; /* 0x24884 - Global address register 1 */
596 uint gaddr2; /* 0x24888 - Global address register 2 */
597 uint gaddr3; /* 0x2488c - Global address register 3 */
598 uint gaddr4; /* 0x24890 - Global address register 4 */
599 uint gaddr5; /* 0x24894 - Global address register 5 */
600 uint gaddr6; /* 0x24898 - Global address register 6 */
601 uint gaddr7; /* 0x2489c - Global address register 7 */
602 char res24[96];
603 uint pmd0; /* 0x24900 - Pattern Match Data Register */
604 char res25[4];
605 uint pmask0; /* 0x24908 - Pattern Mask Register */
606 char res26[4];
607 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
608 char res27[4];
609 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
610 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
611 uint pmd1; /* 0x24920 - Pattern Match Data Register */
612 char res28[4];
613 uint pmask1; /* 0x24928 - Pattern Mask Register */
614 char res29[4];
615 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
616 char res30[4];
617 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
618 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
619 uint pmd2; /* 0x24940 - Pattern Match Data Register */
620 char res31[4];
621 uint pmask2; /* 0x24948 - Pattern Mask Register */
622 char res32[4];
623 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
624 char res33[4];
625 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
626 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
627 uint pmd3; /* 0x24960 - Pattern Match Data Register */
628 char res34[4];
629 uint pmask3; /* 0x24968 - Pattern Mask Register */
630 char res35[4];
631 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
632 char res36[4];
633 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
634 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
635 uint pmd4; /* 0x24980 - Pattern Match Data Register */
636 char res37[4];
637 uint pmask4; /* 0x24988 - Pattern Mask Register */
638 char res38[4];
639 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
640 char res39[4];
641 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
642 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
643 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
644 char res40[4];
645 uint pmask5; /* 0x249a8 - Pattern Mask Register */
646 char res41[4];
647 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
648 char res42[4];
649 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
650 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
651 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
652 char res43[4];
653 uint pmask6; /* 0x249c8 - Pattern Mask Register */
654 char res44[4];
655 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
656 char res45[4];
657 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
658 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
659 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
660 char res46[4];
661 uint pmask7; /* 0x249e8 - Pattern Mask Register */
662 char res47[4];
663 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
664 char res48[4];
665 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
666 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
667 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
668 char res49[4];
669 uint pmask8; /* 0x24a08 - Pattern Mask Register */
670 char res50[4];
671 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
672 char res51[4];
673 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
674 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
675 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
676 char res52[4];
677 uint pmask9; /* 0x24a28 - Pattern Mask Register */
678 char res53[4];
679 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
680 char res54[4];
681 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
682 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
683 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
684 char res55[4];
685 uint pmask10; /* 0x24a48 - Pattern Mask Register */
686 char res56[4];
687 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
688 char res57[4];
689 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
690 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
691 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
692 char res58[4];
693 uint pmask11; /* 0x24a68 - Pattern Mask Register */
694 char res59[4];
695 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
696 char res60[4];
697 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
698 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
699 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
700 char res61[4];
701 uint pmask12; /* 0x24a88 - Pattern Mask Register */
702 char res62[4];
703 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
704 char res63[4];
705 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
706 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
707 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
708 char res64[4];
709 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
710 char res65[4];
711 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
712 char res66[4];
713 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
714 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
715 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
716 char res67[4];
717 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
718 char res68[4];
719 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
720 char res69[4];
721 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
722 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
723 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
724 char res70[4];
725 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
726 char res71[4];
727 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
728 char res72[4];
729 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
730 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
731 char res73[248];
732 uint attr; /* 0x24bf8 - Attributes Register */
733 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
734 char res74[1024];
735} ccsr_tsec_t;
736
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500737/*
Kumar Gala04db4002007-11-29 02:10:09 -0600738 * PIC Registers(0x4_0000-0x8_0000)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500739 */
wdenk42d1f032003-10-15 23:53:47 +0000740typedef struct ccsr_pic {
Kumar Gala04db4002007-11-29 02:10:09 -0600741 char res1[64]; /* 0x40000 */
wdenk42d1f032003-10-15 23:53:47 +0000742 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
743 char res2[12];
744 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
745 char res3[12];
746 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
747 char res4[12];
748 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
749 char res5[12];
750 uint ctpr; /* 0x40080 - Current Task Priority Register */
751 char res6[12];
752 uint whoami; /* 0x40090 - Who Am I Register */
753 char res7[12];
754 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
755 char res8[12];
756 uint eoi; /* 0x400b0 - End Of Interrupt Register */
757 char res9[3916];
758 uint frr; /* 0x41000 - Feature Reporting Register */
759 char res10[28];
760 uint gcr; /* 0x41020 - Global Configuration Register */
wdenk343117b2005-05-13 22:49:36 +0000761#define MPC85xx_PICGCR_RST 0x80000000
762#define MPC85xx_PICGCR_M 0x20000000
wdenk42d1f032003-10-15 23:53:47 +0000763 char res11[92];
764 uint vir; /* 0x41080 - Vendor Identification Register */
765 char res12[12];
766 uint pir; /* 0x41090 - Processor Initialization Register */
767 char res13[12];
768 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
769 char res14[12];
770 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
771 char res15[12];
772 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
773 char res16[12];
774 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
775 char res17[12];
776 uint svr; /* 0x410e0 - Spurious Vector Register */
777 char res18[12];
778 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
779 char res19[12];
780 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
781 char res20[12];
782 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
783 char res21[12];
784 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
785 char res22[12];
786 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
787 char res23[12];
788 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
789 char res24[12];
790 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
791 char res25[12];
792 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
793 char res26[12];
794 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
795 char res27[12];
796 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
797 char res28[12];
798 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
799 char res29[12];
800 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
801 char res30[12];
802 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
803 char res31[12];
804 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
805 char res32[12];
806 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
807 char res33[12];
808 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
809 char res34[12];
810 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
811 char res35[268];
812 uint tcr; /* 0x41300 - Timer Control Register */
813 char res36[12];
814 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
815 char res37[12];
816 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
817 char res38[12];
818 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
819 char res39[12];
820 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
821 char res40[188];
822 uint msgr0; /* 0x41400 - Message Register 0 */
823 char res41[12];
824 uint msgr1; /* 0x41410 - Message Register 1 */
825 char res42[12];
826 uint msgr2; /* 0x41420 - Message Register 2 */
827 char res43[12];
828 uint msgr3; /* 0x41430 - Message Register 3 */
829 char res44[204];
830 uint mer; /* 0x41500 - Message Enable Register */
831 char res45[12];
832 uint msr; /* 0x41510 - Message Status Register */
833 char res46[60140];
834 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
835 char res47[12];
836 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
837 char res48[12];
838 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
839 char res49[12];
840 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
841 char res50[12];
842 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
843 char res51[12];
844 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
845 char res52[12];
846 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
847 char res53[12];
848 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
849 char res54[12];
850 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
851 char res55[12];
852 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
853 char res56[12];
854 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
855 char res57[12];
856 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
857 char res58[12];
858 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
859 char res59[12];
860 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
861 char res60[12];
862 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
863 char res61[12];
864 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
865 char res62[12];
866 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
867 char res63[12];
868 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
869 char res64[12];
870 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
871 char res65[12];
872 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
873 char res66[12];
874 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
875 char res67[12];
876 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
877 char res68[12];
878 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
879 char res69[12];
880 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
881 char res70[140];
882 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
883 char res71[12];
884 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
885 char res72[12];
886 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
887 char res73[12];
888 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
889 char res74[12];
890 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
891 char res75[12];
892 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
893 char res76[12];
894 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
895 char res77[12];
896 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
897 char res78[12];
898 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
899 char res79[12];
900 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
901 char res80[12];
902 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
903 char res81[12];
904 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
905 char res82[12];
906 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
907 char res83[12];
908 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
909 char res84[12];
910 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
911 char res85[12];
912 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
913 char res86[12];
914 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
915 char res87[12];
916 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
917 char res88[12];
918 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
919 char res89[12];
920 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
921 char res90[12];
922 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
923 char res91[12];
924 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
925 char res92[12];
926 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
927 char res93[12];
928 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
929 char res94[12];
930 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
931 char res95[12];
932 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
933 char res96[12];
934 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
935 char res97[12];
936 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
937 char res98[12];
938 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
939 char res99[12];
940 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
941 char res100[12];
942 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
943 char res101[12];
944 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
945 char res102[12];
946 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
947 char res103[12];
948 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
949 char res104[12];
950 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
951 char res105[12];
952 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
953 char res106[12];
954 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
955 char res107[12];
956 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
957 char res108[12];
958 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
959 char res109[12];
960 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
961 char res110[12];
962 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
963 char res111[12];
964 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
965 char res112[12];
966 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
967 char res113[12];
968 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
969 char res114[12];
970 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
971 char res115[12];
972 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
973 char res116[12];
974 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
975 char res117[12];
976 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
977 char res118[12];
978 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
979 char res119[12];
980 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
981 char res120[12];
982 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
983 char res121[12];
984 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
985 char res122[12];
986 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
987 char res123[12];
988 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
989 char res124[12];
990 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
991 char res125[12];
992 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
993 char res126[12];
994 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
995 char res127[12];
996 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
997 char res128[12];
998 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
999 char res129[12];
1000 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
1001 char res130[12];
1002 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
1003 char res131[12];
1004 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
1005 char res132[12];
1006 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1007 char res133[12];
1008 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1009 char res134[4108];
1010 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1011 char res135[12];
1012 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1013 char res136[12];
1014 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1015 char res137[12];
1016 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1017 char res138[12];
1018 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1019 char res139[12];
1020 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1021 char res140[12];
1022 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1023 char res141[12];
1024 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1025 char res142[59852];
1026 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1027 char res143[12];
1028 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1029 char res144[12];
1030 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1031 char res145[12];
1032 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1033 char res146[12];
1034 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1035 char res147[12];
1036 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1037 char res148[12];
1038 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1039 char res149[12];
1040 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1041 char res150[130892];
1042} ccsr_pic_t;
1043
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001044/*
1045 * CPM Block(0x8_0000-0xc_0000)
1046 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -05001047#ifndef CONFIG_CPM2
wdenk42d1f032003-10-15 23:53:47 +00001048typedef struct ccsr_cpm {
1049 char res[262144];
1050} ccsr_cpm_t;
1051#else
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001052/*
1053 * 0x8000-0x8ffff:DPARM
1054 * 0x9000-0x90bff: General SIU
1055 */
wdenk42d1f032003-10-15 23:53:47 +00001056typedef struct ccsr_cpm_siu {
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001057 char res1[80];
wdenk42d1f032003-10-15 23:53:47 +00001058 uint smaer;
1059 uint smser;
1060 uint smevr;
1061 char res2[4];
1062 uint lmaer;
1063 uint lmser;
1064 uint lmevr;
1065 char res3[2964];
1066} ccsr_cpm_siu_t;
1067
1068/* 0x90c00-0x90cff: Interrupt Controller */
1069typedef struct ccsr_cpm_intctl {
1070 ushort sicr;
1071 char res1[2];
1072 uint sivec;
1073 uint sipnrh;
1074 uint sipnrl;
1075 uint siprr;
1076 uint scprrh;
1077 uint scprrl;
1078 uint simrh;
1079 uint simrl;
1080 uint siexr;
1081 char res2[88];
1082 uint sccr;
1083 char res3[124];
1084} ccsr_cpm_intctl_t;
1085
1086/* 0x90d00-0x90d7f: input/output port */
1087typedef struct ccsr_cpm_iop {
1088 uint pdira;
1089 uint ppara;
1090 uint psora;
1091 uint podra;
1092 uint pdata;
1093 char res1[12];
1094 uint pdirb;
1095 uint pparb;
1096 uint psorb;
1097 uint podrb;
1098 uint pdatb;
1099 char res2[12];
1100 uint pdirc;
1101 uint pparc;
1102 uint psorc;
1103 uint podrc;
1104 uint pdatc;
1105 char res3[12];
1106 uint pdird;
1107 uint ppard;
1108 uint psord;
1109 uint podrd;
1110 uint pdatd;
1111 char res4[12];
1112} ccsr_cpm_iop_t;
1113
1114/* 0x90d80-0x91017: CPM timers */
1115typedef struct ccsr_cpm_timer {
1116 u_char tgcr1;
1117 char res1[3];
1118 u_char tgcr2;
1119 char res2[11];
1120 ushort tmr1;
1121 ushort tmr2;
1122 ushort trr1;
1123 ushort trr2;
1124 ushort tcr1;
1125 ushort tcr2;
1126 ushort tcn1;
1127 ushort tcn2;
1128 ushort tmr3;
1129 ushort tmr4;
1130 ushort trr3;
1131 ushort trr4;
1132 ushort tcr3;
1133 ushort tcr4;
1134 ushort tcn3;
1135 ushort tcn4;
1136 ushort ter1;
1137 ushort ter2;
1138 ushort ter3;
1139 ushort ter4;
1140 char res3[608];
1141} ccsr_cpm_timer_t;
1142
1143/* 0x91018-0x912ff: SDMA */
1144typedef struct ccsr_cpm_sdma {
1145 uchar sdsr;
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001146 char res1[3];
1147 uchar sdmr;
1148 char res2[739];
wdenk42d1f032003-10-15 23:53:47 +00001149} ccsr_cpm_sdma_t;
1150
1151/* 0x91300-0x9131f: FCC1 */
1152typedef struct ccsr_cpm_fcc1 {
1153 uint gfmr;
1154 uint fpsmr;
1155 ushort ftodr;
1156 char res1[2];
1157 ushort fdsr;
1158 char res2[2];
1159 ushort fcce;
1160 char res3[2];
1161 ushort fccm;
1162 char res4[2];
1163 u_char fccs;
1164 char res5[3];
1165 u_char ftirr_phy[4];
1166} ccsr_cpm_fcc1_t;
1167
1168/* 0x91320-0x9133f: FCC2 */
1169typedef struct ccsr_cpm_fcc2 {
1170 uint gfmr;
1171 uint fpsmr;
1172 ushort ftodr;
1173 char res1[2];
1174 ushort fdsr;
1175 char res2[2];
1176 ushort fcce;
1177 char res3[2];
1178 ushort fccm;
1179 char res4[2];
1180 u_char fccs;
1181 char res5[3];
1182 u_char ftirr_phy[4];
1183} ccsr_cpm_fcc2_t;
1184
1185/* 0x91340-0x9137f: FCC3 */
1186typedef struct ccsr_cpm_fcc3 {
1187 uint gfmr;
1188 uint fpsmr;
1189 ushort ftodr;
1190 char res1[2];
1191 ushort fdsr;
1192 char res2[2];
1193 ushort fcce;
1194 char res3[2];
1195 ushort fccm;
1196 char res4[2];
1197 u_char fccs;
1198 char res5[3];
1199 char res[36];
1200} ccsr_cpm_fcc3_t;
1201
1202/* 0x91380-0x9139f: FCC1 extended */
1203typedef struct ccsr_cpm_fcc1_ext {
1204 uint firper;
1205 uint firer;
1206 uint firsr_h;
1207 uint firsr_l;
1208 u_char gfemr;
1209 char res[15];
1210
1211} ccsr_cpm_fcc1_ext_t;
1212
1213/* 0x913a0-0x913cf: FCC2 extended */
1214typedef struct ccsr_cpm_fcc2_ext {
1215 uint firper;
1216 uint firer;
1217 uint firsr_h;
1218 uint firsr_l;
1219 u_char gfemr;
1220 char res[31];
1221} ccsr_cpm_fcc2_ext_t;
1222
1223/* 0x913d0-0x913ff: FCC3 extended */
1224typedef struct ccsr_cpm_fcc3_ext {
1225 u_char gfemr;
1226 char res[47];
1227} ccsr_cpm_fcc3_ext_t;
1228
1229/* 0x91400-0x915ef: TC layers */
1230typedef struct ccsr_cpm_tmp1 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001231 char res[496];
wdenk42d1f032003-10-15 23:53:47 +00001232} ccsr_cpm_tmp1_t;
1233
1234/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1235typedef struct ccsr_cpm_brg2 {
1236 uint brgc5;
1237 uint brgc6;
1238 uint brgc7;
1239 uint brgc8;
1240 char res[608];
1241} ccsr_cpm_brg2_t;
1242
1243/* 0x91860-0x919bf: I2C */
1244typedef struct ccsr_cpm_i2c {
1245 u_char i2mod;
1246 char res1[3];
1247 u_char i2add;
1248 char res2[3];
1249 u_char i2brg;
1250 char res3[3];
1251 u_char i2com;
1252 char res4[3];
1253 u_char i2cer;
1254 char res5[3];
1255 u_char i2cmr;
1256 char res6[331];
1257} ccsr_cpm_i2c_t;
1258
1259/* 0x919c0-0x919ef: CPM core */
1260typedef struct ccsr_cpm_cp {
1261 uint cpcr;
1262 uint rccr;
1263 char res1[14];
1264 ushort rter;
1265 char res2[2];
1266 ushort rtmr;
1267 ushort rtscr;
1268 char res3[2];
1269 uint rtsr;
1270 char res4[12];
1271} ccsr_cpm_cp_t;
1272
1273/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1274typedef struct ccsr_cpm_brg1 {
1275 uint brgc1;
1276 uint brgc2;
1277 uint brgc3;
1278 uint brgc4;
1279} ccsr_cpm_brg1_t;
1280
1281/* 0x91a00-0x91a9f: SCC1-SCC4 */
1282typedef struct ccsr_cpm_scc {
1283 uint gsmrl;
1284 uint gsmrh;
1285 ushort psmr;
1286 char res1[2];
1287 ushort todr;
1288 ushort dsr;
1289 ushort scce;
1290 char res2[2];
1291 ushort sccm;
1292 char res3;
1293 u_char sccs;
1294 char res4[8];
1295} ccsr_cpm_scc_t;
1296
1297/* 0x91a80-0x91a9f */
1298typedef struct ccsr_cpm_tmp2 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001299 char res[32];
wdenk42d1f032003-10-15 23:53:47 +00001300} ccsr_cpm_tmp2_t;
1301
1302/* 0x91aa0-0x91aff: SPI */
1303typedef struct ccsr_cpm_spi {
1304 ushort spmode;
1305 char res1[4];
1306 u_char spie;
1307 char res2[3];
1308 u_char spim;
1309 char res3[2];
1310 u_char spcom;
1311 char res4[82];
1312} ccsr_cpm_spi_t;
1313
1314/* 0x91b00-0x91b1f: CPM MUX */
1315typedef struct ccsr_cpm_mux {
1316 u_char cmxsi1cr;
1317 char res1;
1318 u_char cmxsi2cr;
1319 char res2;
1320 uint cmxfcr;
1321 uint cmxscr;
1322 char res3[2];
1323 ushort cmxuar;
1324 char res4[16];
1325} ccsr_cpm_mux_t;
1326
1327/* 0x91b20-0xbffff: SI,MCC,etc */
1328typedef struct ccsr_cpm_tmp3 {
1329 char res[58592];
1330} ccsr_cpm_tmp3_t;
1331
1332typedef struct ccsr_cpm_iram {
1333 unsigned long iram[8192];
1334 char res[98304];
1335} ccsr_cpm_iram_t;
1336
1337typedef struct ccsr_cpm {
1338 /* Some references are into the unique and known dpram spaces,
1339 * others are from the generic base.
1340 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001341#define im_dprambase im_dpram1
1342 u_char im_dpram1[16*1024];
1343 char res1[16*1024];
1344 u_char im_dpram2[16*1024];
1345 char res2[16*1024];
1346 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1347 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1348 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1349 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1350 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
wdenk42d1f032003-10-15 23:53:47 +00001351 ccsr_cpm_fcc1_t im_cpm_fcc1;
1352 ccsr_cpm_fcc2_t im_cpm_fcc2;
1353 ccsr_cpm_fcc3_t im_cpm_fcc3;
1354 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1355 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1356 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1357 ccsr_cpm_tmp1_t im_cpm_tmp1;
1358 ccsr_cpm_brg2_t im_cpm_brg2;
1359 ccsr_cpm_i2c_t im_cpm_i2c;
1360 ccsr_cpm_cp_t im_cpm_cp;
1361 ccsr_cpm_brg1_t im_cpm_brg1;
1362 ccsr_cpm_scc_t im_cpm_scc[4];
1363 ccsr_cpm_tmp2_t im_cpm_tmp2;
1364 ccsr_cpm_spi_t im_cpm_spi;
1365 ccsr_cpm_mux_t im_cpm_mux;
1366 ccsr_cpm_tmp3_t im_cpm_tmp3;
1367 ccsr_cpm_iram_t im_cpm_iram;
1368} ccsr_cpm_t;
1369#endif
wdenk42d1f032003-10-15 23:53:47 +00001370
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001371/*
1372 * RapidIO Registers(0xc_0000-0xe_0000)
1373 */
wdenk42d1f032003-10-15 23:53:47 +00001374typedef struct ccsr_rio {
1375 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1376 uint dicar; /* 0xc0004 - Device Information Capability Register */
1377 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1378 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1379 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1380 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1381 uint socar; /* 0xc0018 - Source Operations Capability Register */
1382 uint docar; /* 0xc001c - Destination Operations Capability Register */
1383 char res1[32];
1384 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1385 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1386 char res2[4];
1387 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1388 char res3[12];
1389 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1390 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1391 char res4[4];
1392 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1393 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1394 char res5[144];
1395 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1396 char res6[28];
1397 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1398 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1399 char res7[20];
1400 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1401 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1402 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1403 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1404 char res8[12];
1405 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1406 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1407 char res9[65184];
1408 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1409 char res10[12];
1410 uint pcr; /* 0xd0010 - Port Configuration Register */
1411 uint peir; /* 0xd0014 - Port Error Injection Register */
1412 char res11[3048];
1413 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1414 char res12[12];
1415 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1416 char res13[12];
1417 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1418 char res14[4];
1419 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1420 char res15[4];
1421 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1422 char res16[12];
1423 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1424 char res17[4];
1425 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1426 char res18[4];
1427 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1428 char res19[12];
1429 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1430 char res20[4];
1431 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1432 char res21[4];
1433 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1434 char res22[12];
1435 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1436 char res23[4];
1437 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1438 char res24[4];
1439 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1440 char res25[12];
1441 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1442 char res26[4];
1443 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1444 char res27[4];
1445 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1446 char res28[12];
1447 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1448 char res29[4];
1449 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1450 char res30[4];
1451 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1452 char res31[12];
1453 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1454 char res32[4];
1455 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1456 char res33[4];
1457 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1458 char res34[12];
1459 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1460 char res35[4];
1461 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1462 char res36[4];
1463 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1464 char res37[76];
1465 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1466 char res38[4];
1467 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1468 char res39[4];
1469 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1470 char res40[12];
1471 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1472 char res41[4];
1473 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1474 char res42[4];
1475 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1476 char res43[12];
1477 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1478 char res44[4];
1479 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1480 char res45[4];
1481 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1482 char res46[12];
1483 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1484 char res47[4];
1485 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1486 char res48[4];
1487 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1488 char res49[12];
1489 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1490 char res50[12];
1491 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1492 char res51[12];
1493 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1494 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1495 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1496 uint pecr; /* 0xd0e0c - Port Error Control Register */
1497 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1498 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1499 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1500 char res52[4];
1501 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1502 char res53[4];
1503 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1504 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1505 char res54[464];
1506 uint omr; /* 0xd1000 - Outbound Mode Register */
1507 uint osr; /* 0xd1004 - Outbound Status Register */
1508 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1509 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1510 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1511 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1512 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1513 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1514 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1515 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1516 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1517 char res55[52];
1518 uint imr; /* 0xd1060 - Outbound Mode Register */
1519 uint isr; /* 0xd1064 - Inbound Status Register */
1520 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1521 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1522 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1523 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1524 char res56[1000];
1525 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1526 uint dsr; /* 0xd1464 - Doorbell Status Register */
1527 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1528 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1529 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1530 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1531 char res57[104];
1532 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1533 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1534 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1535 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1536 char res58[60176];
1537} ccsr_rio_t;
1538
Haiying Wangc59e4092007-06-19 14:18:34 -04001539/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
1540typedef struct par_io {
1541 uint cpodr; /* 0x100 */
1542 uint cpdat; /* 0x104 */
1543 uint cpdir1; /* 0x108 */
1544 uint cpdir2; /* 0x10c */
1545 uint cppar1; /* 0x110 */
1546 uint cppar2; /* 0x114 */
1547 char res[8];
1548}par_io_t;
1549
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001550/*
1551 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1552 */
wdenk42d1f032003-10-15 23:53:47 +00001553typedef struct ccsr_gur {
1554 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1555 uint porbmsr; /* 0xe0004 - POR boot mode status register */
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001556#define MPC85xx_PORBMSR_HA 0x00070000
wdenk42d1f032003-10-15 23:53:47 +00001557 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1558 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001559#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1560#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1561#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1562#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
1563#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001564#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1565#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1566#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1567#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1568#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001569#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001570#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001571#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
wdenk42d1f032003-10-15 23:53:47 +00001572 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
Timur Tabi88353a92008-04-04 11:15:58 -05001573 uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
1574#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
1575 char res1[8];
wdenk42d1f032003-10-15 23:53:47 +00001576 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1577 char res2[12];
1578 uint gpiocr; /* 0xe0030 - GPIO control register */
1579 char res3[12];
1580 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1581 char res4[12];
1582 uint gpindr; /* 0xe0050 - General-purpose input data register */
1583 char res5[12];
1584 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1585 char res6[12];
1586 uint devdisr; /* 0xe0070 - Device disable control */
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001587#define MPC85xx_DEVDISR_PCI1 0x80000000
1588#define MPC85xx_DEVDISR_PCI2 0x40000000
1589#define MPC85xx_DEVDISR_PCIE 0x20000000
1590#define MPC85xx_DEVDISR_LBC 0x08000000
1591#define MPC85xx_DEVDISR_PCIE2 0x04000000
1592#define MPC85xx_DEVDISR_PCIE3 0x02000000
1593#define MPC85xx_DEVDISR_SEC 0x01000000
1594#define MPC85xx_DEVDISR_SRIO 0x00080000
1595#define MPC85xx_DEVDISR_RMSG 0x00040000
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001596#define MPC85xx_DEVDISR_DDR 0x00010000
1597#define MPC85xx_DEVDISR_CPU 0x00008000
1598#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1599#define MPC85xx_DEVDISR_TB 0x00004000
1600#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1601#define MPC85xx_DEVDISR_CPU1 0x00002000
1602#define MPC85xx_DEVDISR_TB1 0x00001000
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001603#define MPC85xx_DEVDISR_DMA 0x00000400
1604#define MPC85xx_DEVDISR_TSEC1 0x00000080
1605#define MPC85xx_DEVDISR_TSEC2 0x00000040
1606#define MPC85xx_DEVDISR_TSEC3 0x00000020
1607#define MPC85xx_DEVDISR_TSEC4 0x00000010
1608#define MPC85xx_DEVDISR_I2C 0x00000004
1609#define MPC85xx_DEVDISR_DUART 0x00000002
wdenk42d1f032003-10-15 23:53:47 +00001610 char res7[12];
1611 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1612 char res8[12];
1613 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1614 char res9[12];
1615 uint pvr; /* 0xe00a0 - Processor version register */
1616 uint svr; /* 0xe00a4 - System version register */
Andy Fleming982efcf2007-06-05 16:38:44 -05001617 char res10a[8];
1618 uint rstcr; /* 0xe00b0 - Reset control register */
Andy Flemingb96c83d2007-08-15 20:03:34 -05001619#ifdef CONFIG_MPC8568
Haiying Wangc59e4092007-06-19 14:18:34 -04001620 char res10b[76];
1621 par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
1622 char res10c[3136];
1623#else
Andy Fleming982efcf2007-06-05 16:38:44 -05001624 char res10b[3404];
Haiying Wangc59e4092007-06-19 14:18:34 -04001625#endif
wdenk42d1f032003-10-15 23:53:47 +00001626 uint clkocr; /* 0xe0e00 - Clock out select register */
1627 char res11[12];
1628 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1629 char res12[12];
1630 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001631 char res13[248];
1632 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1633 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1634 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1635 uint res14; /* 0xe0f28 */
1636 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
Ed Swarthout837f1ba2007-07-27 01:50:51 -05001637 char res15[61648]; /* 0xe0f30 to 0xefffff */
wdenk42d1f032003-10-15 23:53:47 +00001638} ccsr_gur_t;
1639
Matthew McClintock97074ed2006-06-28 10:45:17 -05001640#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
1641
Kumar Gala04db4002007-11-29 02:10:09 -06001642#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
1643#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
1644#define CFG_MPC85xx_ECM_OFFSET (0x0000)
1645#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
1646#define CFG_MPC85xx_DDR_OFFSET (0x2000)
1647#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
James Yang5893b3d2008-02-12 16:35:07 -06001648#define CFG_MPC85xx_DDR2_OFFSET (0x6000)
1649#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
Kumar Gala04db4002007-11-29 02:10:09 -06001650#define CFG_MPC85xx_LBC_OFFSET (0x5000)
1651#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
1652#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
1653#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
1654#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
1655#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
1656#define CFG_MPC85xx_L2_OFFSET (0x20000)
1657#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
1658#define CFG_MPC85xx_DMA_OFFSET (0x21000)
1659#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
1660#define CFG_MPC85xx_PIC_OFFSET (0x40000)
1661#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
Kumar Galaaafeefb2007-11-28 00:36:33 -06001662#define CFG_MPC85xx_CPM_OFFSET (0x80000)
1663#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
1664
wdenk42d1f032003-10-15 23:53:47 +00001665#endif /*__IMMAP_85xx__*/