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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hudd029362016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor
Yangbo Lu34f39ce2021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Hudd029362016-09-07 18:47:28 +08005 */
6
7#ifndef __LS1046A_COMMON_H
8#define __LS1046A_COMMON_H
9
Sumit Garga52ff332017-03-30 09:53:13 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_QBMAN
13#define SPL_NO_FMAN
14#define SPL_NO_ENV
15#define SPL_NO_MISC
16#define SPL_NO_QSPI
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#endif
York Sun038b9652018-06-26 14:48:29 -070020#if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
Sumit Garga52ff332017-03-30 09:53:13 +053022#define SPL_NO_MMC
23#endif
York Sun80bec962018-06-08 16:37:27 -070024#if defined(CONFIG_SPL_BUILD) && \
York Sun80bec962018-06-08 16:37:27 -070025 !defined(CONFIG_SPL_FSL_LS_PPA)
Sumit Garga52ff332017-03-30 09:53:13 +053026#define SPL_NO_IFC
27#endif
28
Mingkai Hudd029362016-09-07 18:47:28 +080029#define CONFIG_REMAKE_ELF
Mingkai Hudd029362016-09-07 18:47:28 +080030#define CONFIG_GICV2
31
32#include <asm/arch/config.h>
Bharat Bhushanb52a0502017-03-22 12:06:28 +053033#include <asm/arch/stream_id_lsch2.h>
Mingkai Hudd029362016-09-07 18:47:28 +080034
35/* Link Definitions */
Rajesh Bhagat8e156bb2018-11-05 18:02:36 +000036#ifdef CONFIG_TFABOOT
37#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
38#else
Mingkai Hudd029362016-09-07 18:47:28 +080039#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagat8e156bb2018-11-05 18:02:36 +000040#endif
Mingkai Hudd029362016-09-07 18:47:28 +080041
Mingkai Hudd029362016-09-07 18:47:28 +080042#define CONFIG_SKIP_LOWLEVEL_INIT
Mingkai Hudd029362016-09-07 18:47:28 +080043
44#define CONFIG_VERY_BIG_RAM
45#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
49
Michael Walle3d3fe8b2020-06-01 21:53:26 +020050#define CPU_RELEASE_ADDR secondary_boot_addr
Mingkai Hudd029362016-09-07 18:47:28 +080051
52/* Generic Timer Definitions */
53#define COUNTER_FREQUENCY 25000000 /* 25MHz */
54
55/* Size of malloc() pool */
56#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
57
58/* Serial Port */
Mingkai Hudd029362016-09-07 18:47:28 +080059#define CONFIG_SYS_NS16550_SERIAL
60#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080061#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hudd029362016-09-07 18:47:28 +080062
Mingkai Hudd029362016-09-07 18:47:28 +080063#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
64
65/* SD boot SPL */
66#ifdef CONFIG_SD_BOOT
Mingkai Hudd029362016-09-07 18:47:28 +080067#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
68#define CONFIG_SPL_STACK 0x10020000
69#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
70#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
72#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
73 CONFIG_SPL_BSS_MAX_SIZE)
74#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
Ruchika Gupta511fc862017-04-17 18:07:19 +053075
Udit Agarwal5536c3c2019-11-07 16:11:32 +000076#ifdef CONFIG_NXP_ESBC
Ruchika Gupta511fc862017-04-17 18:07:19 +053077#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
78/*
79 * HDR would be appended at end of image and copied to DDR along
80 * with U-Boot image. Here u-boot max. size is 512K. So if binary
81 * size increases then increase this size in case of secure boot as
82 * it uses raw u-boot image instead of fit image.
83 */
84#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85#else
86#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal5536c3c2019-11-07 16:11:32 +000087#endif /* ifdef CONFIG_NXP_ESBC */
Mingkai Hudd029362016-09-07 18:47:28 +080088#endif
89
York Sun038b9652018-06-26 14:48:29 -070090#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
91#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
York Sun038b9652018-06-26 14:48:29 -070092#define CONFIG_SPL_MAX_SIZE 0x1f000
93#define CONFIG_SPL_STACK 0x10020000
94#define CONFIG_SPL_PAD_TO 0x20000
95#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
96#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
97#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
98 CONFIG_SPL_BSS_MAX_SIZE)
99#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
100#define CONFIG_SYS_MONITOR_LEN 0x100000
York Sun038b9652018-06-26 14:48:29 -0700101#endif
102
Shaohui Xie126fe702016-09-07 17:56:14 +0800103/* NAND SPL */
104#ifdef CONFIG_NAND_BOOT
105#define CONFIG_SPL_PBL_PAD
Shaohui Xie126fe702016-09-07 17:56:14 +0800106#define CONFIG_SPL_LIBCOMMON_SUPPORT
107#define CONFIG_SPL_LIBGENERIC_SUPPORT
108#define CONFIG_SPL_ENV_SUPPORT
Simon Glass078111b2021-07-10 21:14:28 -0600109#define CONFIG_SPL_WATCHDOG
Shaohui Xie126fe702016-09-07 17:56:14 +0800110#define CONFIG_SPL_I2C_SUPPORT
Shaohui Xie126fe702016-09-07 17:56:14 +0800111#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
112
113#define CONFIG_SPL_NAND_SUPPORT
Simon Glass9ca00682021-07-10 21:14:31 -0600114#define CONFIG_SPL_DRIVERS_MISC
Ruchika Gupta511fc862017-04-17 18:07:19 +0530115#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
Shaohui Xie126fe702016-09-07 17:56:14 +0800116#define CONFIG_SPL_STACK 0x1001f000
117#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
118#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
119
120#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
121#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
122#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
123 CONFIG_SPL_BSS_MAX_SIZE)
124#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
125#define CONFIG_SYS_MONITOR_LEN 0xa0000
126#endif
127
Biwen Li0077d712021-02-05 19:02:01 +0800128/* GPIO */
129#ifdef CONFIG_DM_GPIO
130#ifndef CONFIG_MPC8XXX_GPIO
131#define CONFIG_MPC8XXX_GPIO
132#endif
133#endif
134
Mingkai Hudd029362016-09-07 18:47:28 +0800135/* I2C */
Igor Opaniuk2147a162021-02-09 13:52:45 +0200136#if !CONFIG_IS_ENABLED(DM_I2C)
Simon Glass69d9eda2021-07-10 21:14:32 -0600137#define CONFIG_SYS_I2C_LEGACY
Biwen Libb1165f2020-02-05 22:02:17 +0800138#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
139#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
140#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
141#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
142#else
143#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
144#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
145#endif
Mingkai Hudd029362016-09-07 18:47:28 +0800146
Hou Zhiqiang3098e532017-04-14 16:49:01 +0800147/* PCIe */
148#define CONFIG_PCIE1 /* PCIE controller 1 */
149#define CONFIG_PCIE2 /* PCIE controller 2 */
150#define CONFIG_PCIE3 /* PCIE controller 3 */
151
152#ifdef CONFIG_PCI
153#define CONFIG_PCI_SCAN_SHOW
Hou Zhiqiang3098e532017-04-14 16:49:01 +0800154#endif
155
Yuantian Tangf216ef22018-01-03 15:53:09 +0800156/* SATA */
157#ifndef SPL_NO_SATA
158#define CONFIG_SCSI_AHCI_PLAT
159
160#define CONFIG_SYS_SATA AHCI_BASE_ADDR
161
162#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
163#define CONFIG_SYS_SCSI_MAX_LUN 1
164#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
165 CONFIG_SYS_SCSI_MAX_LUN)
166#endif
167
Mingkai Hudd029362016-09-07 18:47:28 +0800168/* FMan ucode */
Sumit Garga52ff332017-03-30 09:53:13 +0530169#ifndef SPL_NO_FMAN
Mingkai Hudd029362016-09-07 18:47:28 +0800170#define CONFIG_SYS_DPAA_FMAN
171#ifdef CONFIG_SYS_DPAA_FMAN
172#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
Sumit Garga52ff332017-03-30 09:53:13 +0530173#endif
Mingkai Hudd029362016-09-07 18:47:28 +0800174
Rajesh Bhagat8e156bb2018-11-05 18:02:36 +0000175#ifdef CONFIG_TFABOOT
176#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
Rajesh Bhagat8e156bb2018-11-05 18:02:36 +0000177#else
Mingkai Hudd029362016-09-07 18:47:28 +0800178#ifdef CONFIG_SD_BOOT
179/*
180 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
181 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
Alison Wang8104deb2017-05-16 10:45:59 +0800182 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
Mingkai Hudd029362016-09-07 18:47:28 +0800183 */
Alison Wang8104deb2017-05-16 10:45:59 +0800184#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
Shaohui Xie126fe702016-09-07 17:56:14 +0800185#elif defined(CONFIG_QSPI_BOOT)
Alison Wang8104deb2017-05-16 10:45:59 +0800186#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
Shaohui Xie126fe702016-09-07 17:56:14 +0800187#elif defined(CONFIG_NAND_BOOT)
Gong Qianyu752513d2017-09-18 16:59:28 +0800188#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xie126fe702016-09-07 17:56:14 +0800189#else
Alison Wang8104deb2017-05-16 10:45:59 +0800190#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
Mingkai Hudd029362016-09-07 18:47:28 +0800191#endif
Rajesh Bhagat8e156bb2018-11-05 18:02:36 +0000192#endif
Mingkai Hudd029362016-09-07 18:47:28 +0800193#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
194#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
195#endif
196
197/* Miscellaneous configurable options */
198#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
Mingkai Hudd029362016-09-07 18:47:28 +0800199
200#define CONFIG_HWCONFIG
201#define HWCONFIG_BUFFER_SIZE 128
202
Qianyu Gong8de227e2017-06-15 11:10:09 +0800203#ifndef CONFIG_SPL_BUILD
204#define BOOT_TARGET_DEVICES(func) \
Yuantian Tangf216ef22018-01-03 15:53:09 +0800205 func(SCSI, scsi, 0) \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800206 func(MMC, mmc, 0) \
Mian Yousaf Kaukabf43cc402019-01-29 16:38:37 +0100207 func(USB, usb, 0) \
208 func(DHCP, dhcp, na)
Qianyu Gong8de227e2017-06-15 11:10:09 +0800209#include <config_distro_bootcmd.h>
210#endif
211
Vabhav Sharmad90c7ac2019-06-06 12:35:28 +0000212#if defined(CONFIG_TARGET_LS1046AFRWY)
213#define LS1046A_BOOT_SRC_AND_HDR\
214 "boot_scripts=ls1046afrwy_boot.scr\0" \
215 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
Biwen Lid71f65e2020-04-20 18:29:06 +0800216#elif defined(CONFIG_TARGET_LS1046AQDS)
217#define LS1046A_BOOT_SRC_AND_HDR\
218 "boot_scripts=ls1046aqds_boot.scr\0" \
219 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
Vabhav Sharmad90c7ac2019-06-06 12:35:28 +0000220#else
221#define LS1046A_BOOT_SRC_AND_HDR\
222 "boot_scripts=ls1046ardb_boot.scr\0" \
223 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
224#endif
Sumit Garga52ff332017-03-30 09:53:13 +0530225#ifndef SPL_NO_MISC
Mingkai Hudd029362016-09-07 18:47:28 +0800226/* Initial environment variables */
227#define CONFIG_EXTRA_ENV_SETTINGS \
228 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800229 "ramdisk_addr=0x800000\0" \
230 "ramdisk_size=0x2000000\0" \
Yuantian Tange9d9c2e2020-02-19 17:02:22 +0800231 "bootm_size=0x10000000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800232 "fdt_addr=0x64f00000\0" \
Biwen Lid71f65e2020-04-20 18:29:06 +0800233 "kernel_addr=0x61000000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800234 "scriptaddr=0x80000000\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530235 "scripthdraddr=0x80080000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800236 "fdtheader_addr_r=0x80100000\0" \
237 "kernelheader_addr_r=0x80200000\0" \
238 "load_addr=0xa0000000\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530239 "kernel_addr_r=0x81000000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800240 "fdt_addr_r=0x90000000\0" \
241 "ramdisk_addr_r=0xa0000000\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800242 "kernel_start=0x1000000\0" \
Priyanka Singhe735ad32020-01-22 10:29:46 +0000243 "kernelheader_start=0x600000\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800244 "kernel_load=0xa0000000\0" \
245 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530246 "kernelheader_size=0x40000\0" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800247 "kernel_addr_sd=0x8000\0" \
248 "kernel_size_sd=0x14000\0" \
Priyanka Singhe735ad32020-01-22 10:29:46 +0000249 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530250 "kernelhdr_size_sd=0x10\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800251 "console=ttyS0,115200\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400252 CONFIG_MTDPARTS_DEFAULT "\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800253 BOOTENV \
Vabhav Sharmad90c7ac2019-06-06 12:35:28 +0000254 LS1046A_BOOT_SRC_AND_HDR \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800255 "scan_dev_for_boot_part=" \
256 "part list ${devtype} ${devnum} devplist; " \
257 "env exists devplist || setenv devplist 1; " \
258 "for distro_bootpart in ${devplist}; do " \
259 "if fstype ${devtype} " \
260 "${devnum}:${distro_bootpart} " \
261 "bootfstype; then " \
262 "run scan_dev_for_boot; " \
263 "fi; " \
264 "done\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530265 "boot_a_script=" \
266 "load ${devtype} ${devnum}:${distro_bootpart} " \
267 "${scriptaddr} ${prefix}${script}; " \
268 "env exists secureboot && load ${devtype} " \
269 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000270 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
271 "env exists secureboot " \
272 "&& esbc_validate ${scripthdraddr};" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530273 "source ${scriptaddr}\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800274 "qspi_bootcmd=echo Trying load from qspi..;" \
275 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530276 "$kernel_start $kernel_size; env exists secureboot " \
277 "&& sf read $kernelheader_addr_r $kernelheader_start " \
278 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
279 "bootm $load_addr#$board\0" \
Biwen Lid71f65e2020-04-20 18:29:06 +0800280 "nand_bootcmd=echo Trying load from nand..;" \
281 "nand info; nand read $load_addr " \
282 "$kernel_start $kernel_size; env exists secureboot " \
283 "&& nand read $kernelheader_addr_r $kernelheader_start " \
284 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
285 "bootm $load_addr#$board\0" \
286 "nor_bootcmd=echo Trying load from nor..;" \
287 "cp.b $kernel_addr $load_addr " \
288 "$kernel_size; env exists secureboot " \
289 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
290 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
291 "bootm $load_addr#$board\0" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800292 "sd_bootcmd=echo Trying load from SD ..;" \
293 "mmcinfo; mmc read $load_addr " \
294 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530295 "env exists secureboot && mmc read $kernelheader_addr_r " \
296 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
297 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800298 "bootm $load_addr#$board\0"
Qianyu Gong8de227e2017-06-15 11:10:09 +0800299
Sumit Garga52ff332017-03-30 09:53:13 +0530300#endif
301
Mingkai Hudd029362016-09-07 18:47:28 +0800302/* Monitor Command Prompt */
303#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Garga52ff332017-03-30 09:53:13 +0530304
Mingkai Hudd029362016-09-07 18:47:28 +0800305#define CONFIG_SYS_MAXARGS 64 /* max command args */
306
307#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
308
Simon Glass457e51c2017-05-17 08:23:10 -0600309#include <asm/arch/soc.h>
310
Mingkai Hudd029362016-09-07 18:47:28 +0800311#endif /* __LS1046A_COMMON_H */