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Joe Hamman11c45eb2007-12-13 06:45:08 -06001/*
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -04002 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
3 *
Joe Hamman11c45eb2007-12-13 06:45:08 -06004 * Copyright 2007 Embedded Specialties, Inc.
5 *
6 * Copyright 2004, 2007 Freescale Semiconductor.
7 *
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Joe Hamman11c45eb2007-12-13 06:45:08 -060011 */
12
13#include <common.h>
14#include <pci.h>
15#include <asm/processor.h>
16#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050017#include <asm/fsl_pci.h>
Kumar Gala33b90792008-08-26 23:15:28 -050018#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060019#include <asm/fsl_serdes.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060020#include <spd_sdram.h>
Paul Gortmaker94ca0912009-09-18 19:08:44 -040021#include <netdev.h>
22#include <tsec.h>
Joe Hamman11c45eb2007-12-13 06:45:08 -060023#include <miiphy.h>
24#include <libfdt.h>
25#include <fdt_support.h>
26
Joe Hamman11c45eb2007-12-13 06:45:08 -060027DECLARE_GLOBAL_DATA_PTR;
28
Joe Hamman11c45eb2007-12-13 06:45:08 -060029void local_bus_init(void);
Joe Hamman11c45eb2007-12-13 06:45:08 -060030
31int board_early_init_f (void)
32{
33 return 0;
34}
35
36int checkboard (void)
37{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
39 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
Joe Hamman11c45eb2007-12-13 06:45:08 -060040
41 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040042 in_8(rev) >> 4);
Joe Hamman11c45eb2007-12-13 06:45:08 -060043
44 /*
45 * Initialize local bus.
46 */
47 local_bus_init ();
48
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040049 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
50 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
Joe Hamman11c45eb2007-12-13 06:45:08 -060051 return 0;
52}
53
Joe Hamman11c45eb2007-12-13 06:45:08 -060054/*
55 * Initialize Local Bus
56 */
57void
58local_bus_init(void)
59{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050061 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Joe Hamman11c45eb2007-12-13 06:45:08 -060062
Paul Gortmakere2b363f2011-12-30 23:53:13 -050063 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
Joe Hamman11c45eb2007-12-13 06:45:08 -060064 sys_info_t sysinfo;
65
66 get_sys_info(&sysinfo);
Paul Gortmakere2b363f2011-12-30 23:53:13 -050067
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053068 lbc_mhz = sysinfo.freq_localbus / 1000000;
69 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
Paul Gortmakere2b363f2011-12-30 23:53:13 -050070
71 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
Joe Hamman11c45eb2007-12-13 06:45:08 -060072
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040073 out_be32(&gur->lbiuiplldcr1, 0x00078080);
Joe Hamman11c45eb2007-12-13 06:45:08 -060074 if (clkdiv == 16) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040075 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060076 } else if (clkdiv == 8) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040077 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060078 } else if (clkdiv == 4) {
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -040079 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
Joe Hamman11c45eb2007-12-13 06:45:08 -060080 }
81
Paul Gortmakere2b363f2011-12-30 23:53:13 -050082 /*
83 * Local Bus Clock > 83.3 MHz. According to timing
84 * specifications set LCRR[EADC] to 2 delay cycles.
85 */
86 if (lbc_mhz > 83) {
87 lcrr &= ~LCRR_EADC;
88 lcrr |= LCRR_EADC_2;
89 }
Joe Hamman11c45eb2007-12-13 06:45:08 -060090
Paul Gortmakere2b363f2011-12-30 23:53:13 -050091 /*
92 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
93 * disable PLL bypass for Local Bus Clock > 83 MHz.
94 */
95 if (lbc_mhz >= 66)
96 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
97
98 else
99 lcrr |= LCRR_DBYP; /* DLL Bypass */
100
101 out_be32(&lbc->lcrr, lcrr);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600102 asm("sync;isync;msync");
103
Paul Gortmakere2b363f2011-12-30 23:53:13 -0500104 /*
105 * According to MPC8548ERMAD Rev.1.3 read back LCRR
106 * and terminate with isync
107 */
108 lcrr = in_be32(&lbc->lcrr);
109 asm ("isync;");
110
111 /* let DLL stabilize */
112 udelay(500);
113
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400114 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
115 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600116}
117
118/*
119 * Initialize SDRAM memory on the Local Bus.
120 */
Becky Bruce70961ba2010-12-17 17:17:57 -0600121void lbc_sdram_init(void)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600122{
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400123#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600124
125 uint idx;
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500126 const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500127 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500129 uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600130
131 puts(" SDRAM: ");
132
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500133 print_size(size, "\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600134
135 /*
136 * Setup SDRAM Base and Option Registers
137 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500138 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
139 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
140 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
141 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400142
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400143 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600144 asm("msync");
145
Paul Gortmaker0c7e4d42009-09-20 20:36:03 -0400146 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
147 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600148 asm("msync");
149
150 /*
Joe Hamman11c45eb2007-12-13 06:45:08 -0600151 * Issue PRECHARGE ALL command.
152 */
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500153 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600154 asm("sync;msync");
155 *sdram_addr = 0xff;
156 ppcDcbf((unsigned long) sdram_addr);
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500157 *sdram_addr2 = 0xff;
158 ppcDcbf((unsigned long) sdram_addr2);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600159 udelay(100);
160
161 /*
162 * Issue 8 AUTO REFRESH commands.
163 */
164 for (idx = 0; idx < 8; idx++) {
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500165 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600166 asm("sync;msync");
167 *sdram_addr = 0xff;
168 ppcDcbf((unsigned long) sdram_addr);
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500169 *sdram_addr2 = 0xff;
170 ppcDcbf((unsigned long) sdram_addr2);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600171 udelay(100);
172 }
173
174 /*
175 * Issue 8 MODE-set command.
176 */
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500177 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600178 asm("sync;msync");
179 *sdram_addr = 0xff;
180 ppcDcbf((unsigned long) sdram_addr);
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500181 *sdram_addr2 = 0xff;
182 ppcDcbf((unsigned long) sdram_addr2);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600183 udelay(100);
184
185 /*
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500186 * Issue RFEN command.
Joe Hamman11c45eb2007-12-13 06:45:08 -0600187 */
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500188 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600189 asm("sync;msync");
190 *sdram_addr = 0xff;
191 ppcDcbf((unsigned long) sdram_addr);
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500192 *sdram_addr2 = 0xff;
193 ppcDcbf((unsigned long) sdram_addr2);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600194 udelay(200); /* Overkill. Must wait > 200 bus cycles */
195
196#endif /* enable SDRAM init */
197}
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600200int
201testdram(void)
202{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
204 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600205 uint *p;
206
207 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 CONFIG_SYS_MEMTEST_START,
209 CONFIG_SYS_MEMTEST_END);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600210
211 printf("DRAM test phase 1:\n");
212 for (p = pstart; p < pend; p++)
213 *p = 0xaaaaaaaa;
214
215 for (p = pstart; p < pend; p++) {
216 if (*p != 0xaaaaaaaa) {
217 printf ("DRAM test fails at: %08x\n", (uint) p);
218 return 1;
219 }
220 }
221
222 printf("DRAM test phase 2:\n");
223 for (p = pstart; p < pend; p++)
224 *p = 0x55555555;
225
226 for (p = pstart; p < pend; p++) {
227 if (*p != 0x55555555) {
228 printf ("DRAM test fails at: %08x\n", (uint) p);
229 return 1;
230 }
231 }
232
233 printf("DRAM test passed.\n");
234 return 0;
235}
236#endif
237
Paul Gortmaker7b1f1392009-09-18 19:08:39 -0400238#ifdef CONFIG_PCI1
239static struct pci_controller pci1_hose;
240#endif /* CONFIG_PCI1 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600241
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400242#ifdef CONFIG_PCI
Joe Hamman11c45eb2007-12-13 06:45:08 -0600243void
244pci_init_board(void)
245{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400247 int first_free_busno = 0;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600248
249#ifdef CONFIG_PCI1
Kumar Gala2d0a0542010-12-17 10:30:44 -0600250 struct fsl_pci_info pci_info;
251 u32 devdisr = in_be32(&gur->devdisr);
252 u32 pordevsr = in_be32(&gur->pordevsr);
253 u32 porpllsr = in_be32(&gur->porpllsr);
254
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400255 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
256 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
257 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
258 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
259 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600260
Peter Tyser8ca78f22010-10-29 17:59:24 -0500261 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600262 (pci_32) ? 32 : 64,
Paul Gortmaker2c40acd2009-09-18 19:08:40 -0400263 (pci_speed == 33000000) ? "33" :
264 (pci_speed == 66000000) ? "66" : "unknown",
Joe Hamman11c45eb2007-12-13 06:45:08 -0600265 pci_clk_sel ? "sync" : "async",
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400266 pci_arb ? "arbiter" : "external-arbiter");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600267
Kumar Gala2d0a0542010-12-17 10:30:44 -0600268 SET_STD_PCI_INFO(pci_info, 1);
269 set_next_law(pci_info.mem_phys,
270 law_size_bits(pci_info.mem_size), pci_info.law);
271 set_next_law(pci_info.io_phys,
272 law_size_bits(pci_info.io_size), pci_info.law);
273
274 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala01471d52009-11-04 01:29:04 -0600275 &pci1_hose, first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600276 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500277 printf("PCI: disabled\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600278 }
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400279
280 puts("\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600281#else
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400282 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600283#endif
284
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400285 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
Joe Hamman11c45eb2007-12-13 06:45:08 -0600286
Kumar Gala2d0a0542010-12-17 10:30:44 -0600287 fsl_pcie_init_board(first_free_busno);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600288}
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400289#endif
Joe Hamman11c45eb2007-12-13 06:45:08 -0600290
Paul Gortmaker94ca0912009-09-18 19:08:44 -0400291int board_eth_init(bd_t *bis)
292{
293 tsec_standard_init(bis);
294 pci_eth_init(bis);
295 return 0; /* otherwise cpu_eth_init gets run */
296}
297
Joe Hamman11c45eb2007-12-13 06:45:08 -0600298int last_stage_init(void)
299{
300 return 0;
301}
302
303#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500304void ft_board_setup(void *blob, bd_t *bd)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600305{
306 ft_cpu_setup(blob, bd);
Kumar Gala6525d512010-07-08 22:37:44 -0500307
308#ifdef CONFIG_FSL_PCI_INIT
309 FT_FSL_PCI_SETUP;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600310#endif
311}
312#endif