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Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <malloc.h>
27#include <asm/arch/ixp425.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020031/* predefine these here for FPGA programming (before including fpga.c) */
32#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
34#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020035#define OLD_VAL old_val
36
37static unsigned long old_val = 0;
38
39/*
40 * include common fpga code (for prodrive boards)
41 */
42#include "../common/fpga.c"
43
44/*
45 * Miscelaneous platform dependent initialisations
46 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020047int board_init(void)
48{
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020049 /* adress of boot parameters */
50 gd->bd->bi_boot_params = 0x00000100;
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
53 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
56 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020057
58 /*
59 * Setup GPIO's for FPGA programming
60 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
62 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
63 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
64 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
65 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
66 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
67 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
68 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020069
70 /*
71 * Setup GPIO's for interrupts
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
74 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
75 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
76 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
77 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
78 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
79 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
80 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020081
82 /*
83 * Setup GPIO's for 33MHz clock output
84 */
85 *IXP425_GPIO_GPCLKR = 0x01FF0000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020087
88 /*
89 * Setup other chip select's
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020092
93 return 0;
94}
95
96/*
97 * Check Board Identity
98 */
99int checkboard(void)
100{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000101 char buf[64];
102 int i = getenv_f("serial#", buf, sizeof(buf));
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200103
104 puts("Board: PDNB3");
105
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000106 if (i > 0) {
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200107 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000108 puts(buf);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200109 }
110 putc('\n');
111
112 return (0);
113}
114
115int dram_init(void)
116{
117 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
118 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
119
120 return (0);
121}
122
123int do_fpga_boot(unsigned char *fpgadata)
124{
125 unsigned char *dst;
126 int status;
127 int index;
128 int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 ulong len = CONFIG_SYS_MALLOC_LEN;
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200130
131 /*
132 * Setup GPIO's for FPGA programming
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
135 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
136 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200137
138 /*
139 * Save value so no readback is required upon programming
140 */
141 old_val = *IXP425_GPIO_GPOUTR;
142
143 /*
144 * First try to decompress fpga image (gzip compressed?)
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
147 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200148 printf("Error: Image has to be gzipp'ed!\n");
149 return -1;
150 }
151
152 status = fpga_boot(dst, len);
153 if (status != 0) {
154 printf("\nFPGA: Booting failed ");
155 switch (status) {
156 case ERROR_FPGA_PRG_INIT_LOW:
157 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
158 break;
159 case ERROR_FPGA_PRG_INIT_HIGH:
160 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
161 break;
162 case ERROR_FPGA_PRG_DONE:
163 printf("(Timeout: DONE not high after programming FPGA)\n ");
164 break;
165 }
166
167 /* display infos on fpgaimage */
168 index = 15;
169 for (i=0; i<4; i++) {
170 len = dst[index];
171 printf("FPGA: %s\n", &(dst[index+1]));
172 index += len+3;
173 }
174 putc ('\n');
175 /* delayed reboot */
176 for (i=5; i>0; i--) {
177 printf("Rebooting in %2d seconds \r",i);
178 for (index=0;index<1000;index++)
179 udelay(1000);
180 }
181 putc('\n');
182 do_reset(NULL, 0, 0, NULL);
183 }
184
185 puts("FPGA: ");
186
187 /* display infos on fpgaimage */
188 index = 15;
189 for (i=0; i<4; i++) {
190 len = dst[index];
191 printf("%s ", &(dst[index+1]));
192 index += len+3;
193 }
194 putc('\n');
195
196 free(dst);
197
198 /*
199 * Reset FPGA
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200202 udelay(10);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200204
205 return (0);
206}
207
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200208int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200209{
210 ulong addr;
211
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200212 if (argc < 2)
213 return cmd_usage(cmdtp);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200214
215 addr = simple_strtoul(argv[1], NULL, 16);
216
217 return do_fpga_boot((unsigned char *)addr);
218}
219
220U_BOOT_CMD(
221 fpga, 2, 0, do_fpga,
Peter Tyser2fb26042009-01-27 18:03:12 -0600222 "boot FPGA",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200223 "address size\n - boot FPGA with gzipped image at <address>"
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200224);
225
Jon Loeliger3fe00102007-07-09 18:38:39 -0500226#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200227extern struct pci_controller hose;
228extern void pci_ixp_init(struct pci_controller * hose);
229
230void pci_init_board(void)
231{
232 extern void pci_ixp_init (struct pci_controller *hose);
233
234 pci_ixp_init(&hose);
235}
236#endif