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Aubrey Li65458982007-03-20 18:16:24 +08001/*
Mike Frysingerae091022008-10-11 20:42:17 -04002 * U-boot - main board file
Aubrey Li65458982007-03-20 18:16:24 +08003 *
Mike Frysingerae091022008-10-11 20:42:17 -04004 * Copyright (c) 2005-2008 Analog Devices Inc.
Aubrey Li65458982007-03-20 18:16:24 +08005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080024 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 * MA 02110-1301 USA
Aubrey Li65458982007-03-20 18:16:24 +080026 */
27
28#include <common.h>
29#include <asm/io.h>
30
Wolfgang Denk1218abf2007-09-15 20:48:41 +020031DECLARE_GLOBAL_DATA_PTR;
32
Aubrey Li65458982007-03-20 18:16:24 +080033int checkboard(void)
34{
Aubrey Li65458982007-03-20 18:16:24 +080035 printf("Board: ADI BF561 EZ-Kit Lite board\n");
36 printf(" Support: http://blackfin.uclinux.org/\n");
37 return 0;
38}
39
Becky Bruce9973e3c2008-06-09 16:03:40 -050040phys_size_t initdram(int board_type)
Aubrey Li65458982007-03-20 18:16:24 +080041{
Aubrey Li65458982007-03-20 18:16:24 +080042#ifdef DEBUG
43 int brate;
44 char *tmp = getenv("baudrate");
45 brate = simple_strtoul(tmp, NULL, 16);
46 printf("Serial Port initialized with Baud rate = %x\n", brate);
47 printf("SDRAM attributes:\n");
48 printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
49 "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
50 3, 3, 6, 2, 3);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051 printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
52 printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
Aubrey Li65458982007-03-20 18:16:24 +080053#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
55 gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
56 return CONFIG_SYS_MAX_RAM_SIZE;
Aubrey Li65458982007-03-20 18:16:24 +080057}