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Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - ezkit561.c
3 *
4 * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
Aubrey Li155fd762007-04-05 18:31:18 +08005 * Copyright (c) 2005-2007 Analog Devices Inc.
Aubrey Li65458982007-03-20 18:16:24 +08006 *
7 * (C) Copyright 2000-2004
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080025 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * MA 02110-1301 USA
Aubrey Li65458982007-03-20 18:16:24 +080027 */
28
29#include <common.h>
30#include <asm/io.h>
31
Wolfgang Denk1218abf2007-09-15 20:48:41 +020032DECLARE_GLOBAL_DATA_PTR;
33
Aubrey Li65458982007-03-20 18:16:24 +080034int checkboard(void)
35{
36 printf("CPU: ADSP BF561\n");
37 printf("Board: ADI BF561 EZ-Kit Lite board\n");
38 printf(" Support: http://blackfin.uclinux.org/\n");
39 return 0;
40}
41
Becky Bruce9973e3c2008-06-09 16:03:40 -050042phys_size_t initdram(int board_type)
Aubrey Li65458982007-03-20 18:16:24 +080043{
Aubrey Li65458982007-03-20 18:16:24 +080044#ifdef DEBUG
45 int brate;
46 char *tmp = getenv("baudrate");
47 brate = simple_strtoul(tmp, NULL, 16);
48 printf("Serial Port initialized with Baud rate = %x\n", brate);
49 printf("SDRAM attributes:\n");
50 printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
51 "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
52 3, 3, 6, 2, 3);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
54 printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
Aubrey Li65458982007-03-20 18:16:24 +080055#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
57 gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
58 return CONFIG_SYS_MAX_RAM_SIZE;
Aubrey Li65458982007-03-20 18:16:24 +080059}
60
61#if defined(CONFIG_MISC_INIT_R)
62/* miscellaneous platform dependent initialisations */
63int misc_init_r(void)
64{
65 /* Keep PF12 low to be able to drive the USB-LAN Extender */
66 *pFIO0_DIR = 0x0000;
67 *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
Mike Frysingerd4d77302008-02-04 19:26:55 -050068 SSYNC();
Aubrey Li65458982007-03-20 18:16:24 +080069 *pFIO0_POLAR = 0x0000;
Mike Frysingerd4d77302008-02-04 19:26:55 -050070 SSYNC();
Aubrey Li65458982007-03-20 18:16:24 +080071
72 return 0;
73}
74#endif