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wdenk7a8e9bed2003-05-31 18:35:21 +00001/*
wdenk8bde7f72003-06-27 21:31:46 +00002 *
wdenk7a8e9bed2003-05-31 18:35:21 +00003 * (C) Copyright 2002
4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <ssi.h>
28#include <asm/io.h>
29#include <asm/pci.h>
30#include <asm/ic/sc520.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
wdenk8bde7f72003-06-27 21:31:46 +000033
34/*
wdenk7a8e9bed2003-05-31 18:35:21 +000035 * Theory:
36 * We first set up all IRQs to be non-pci, edge triggered,
wdenk8bde7f72003-06-27 21:31:46 +000037 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
wdenk7a8e9bed2003-05-31 18:35:21 +000038 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
39 * as needed. Whe choose the irqs to gram from a configurable list
40 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
41 * such as 0 thngas will not work)
42 */
43
44static void irq_init(void)
45{
46 /* disable global interrupt mode */
wdenk8bde7f72003-06-27 21:31:46 +000047 write_mmcr_byte(SC520_PICICR, 0x40);
48
wdenk7a8e9bed2003-05-31 18:35:21 +000049 /* set all irqs to edge */
50 write_mmcr_byte(SC520_MPICMODE, 0x00);
51 write_mmcr_byte(SC520_SL1PICMODE, 0x00);
52 write_mmcr_byte(SC520_SL2PICMODE, 0x00);
wdenk8bde7f72003-06-27 21:31:46 +000053
54 /* active low polarity on PIC interrupt pins,
wdenk7a8e9bed2003-05-31 18:35:21 +000055 * active high polarity on all other irq pins */
56 write_mmcr_word(SC520_INTPINPOL, 0x0000);
57
58 /* set irq number mapping */
wdenk8bde7f72003-06-27 21:31:46 +000059 write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000060 write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
61 write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
wdenk8bde7f72003-06-27 21:31:46 +000062 write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
wdenk7a8e9bed2003-05-31 18:35:21 +000063 write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
64 write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
65 write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
66 write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
67 write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
68 write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
wdenk8bde7f72003-06-27 21:31:46 +000069 write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000070 write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/
71 write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
72 write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
73 write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
74 write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
75 write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
wdenk8bde7f72003-06-27 21:31:46 +000076
wdenk7a8e9bed2003-05-31 18:35:21 +000077 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
78 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
wdenk8bde7f72003-06-27 21:31:46 +000079
wdenk7a8e9bed2003-05-31 18:35:21 +000080 write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
81 write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */
wdenk8bde7f72003-06-27 21:31:46 +000082 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
wdenk7a8e9bed2003-05-31 18:35:21 +000083 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */
84 write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */
85 write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */
86 write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */
87 write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */
88 write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */
89 write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */
wdenk8bde7f72003-06-27 21:31:46 +000090 write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */
91
wdenk7a8e9bed2003-05-31 18:35:21 +000092 write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
93 write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
wdenk8bde7f72003-06-27 21:31:46 +000094
wdenk7a8e9bed2003-05-31 18:35:21 +000095}
96
wdenk8bde7f72003-06-27 21:31:46 +000097
wdenk7a8e9bed2003-05-31 18:35:21 +000098/* PCI stuff */
99static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
100{
101 int version = read_mmcr_byte(SC520_SYSINFO);
wdenk8bde7f72003-06-27 21:31:46 +0000102
wdenk7a8e9bed2003-05-31 18:35:21 +0000103 /* a configurable lists of irqs to steal
104 * when we need one (a board with more pci interrupt pins
105 * would use a larger table */
106 static int irq_list[] = {
107 CFG_FIRST_PCI_IRQ,
108 CFG_SECOND_PCI_IRQ,
109 CFG_THIRD_PCI_IRQ,
110 CFG_FORTH_PCI_IRQ
111 };
112 static int next_irq_index=0;
wdenk8bde7f72003-06-27 21:31:46 +0000113
114 char tmp_pin;
wdenk7a8e9bed2003-05-31 18:35:21 +0000115 int pin;
wdenk8bde7f72003-06-27 21:31:46 +0000116
wdenk7a8e9bed2003-05-31 18:35:21 +0000117 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
118 pin = tmp_pin;
wdenk8bde7f72003-06-27 21:31:46 +0000119
wdenk7a8e9bed2003-05-31 18:35:21 +0000120 pin-=1; /* pci config space use 1-based numbering */
121 if (-1 == pin) {
122 return; /* device use no irq */
123 }
wdenk8bde7f72003-06-27 21:31:46 +0000124
125
wdenk7a8e9bed2003-05-31 18:35:21 +0000126 /* map device number + pin to a pin on the sc520 */
127 switch (PCI_DEV(dev)) {
wdenk8bde7f72003-06-27 21:31:46 +0000128 case 6: /* ETH0 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000129 pin+=SC520_PCI_INTA;
130 break;
wdenk8bde7f72003-06-27 21:31:46 +0000131
wdenk7a8e9bed2003-05-31 18:35:21 +0000132 case 7: /* ETH1 */
133 pin+=SC520_PCI_INTB;
134 break;
wdenk8bde7f72003-06-27 21:31:46 +0000135
wdenk7a8e9bed2003-05-31 18:35:21 +0000136 case 8: /* Crypto */
137 pin+=SC520_PCI_INTC;
138 break;
wdenk8bde7f72003-06-27 21:31:46 +0000139
wdenk7a8e9bed2003-05-31 18:35:21 +0000140 case 9: /* PMC slot */
141 pin+=SC520_PCI_INTD;
142 break;
wdenk8bde7f72003-06-27 21:31:46 +0000143
wdenk7a8e9bed2003-05-31 18:35:21 +0000144 case 10: /* PC-Card */
wdenk8bde7f72003-06-27 21:31:46 +0000145
146 if (version < 10) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000147 pin+=SC520_PCI_INTD;
148 } else {
149 pin+=SC520_PCI_INTC;
150 }
151 break;
wdenk8bde7f72003-06-27 21:31:46 +0000152
153 default:
wdenk7a8e9bed2003-05-31 18:35:21 +0000154 return;
155 }
wdenk8bde7f72003-06-27 21:31:46 +0000156
wdenk7a8e9bed2003-05-31 18:35:21 +0000157 pin&=3; /* wrap around */
wdenk8bde7f72003-06-27 21:31:46 +0000158
wdenk7a8e9bed2003-05-31 18:35:21 +0000159 if (sc520_pci_ints[pin] == -1) {
wdenk8bde7f72003-06-27 21:31:46 +0000160 /* re-route one interrupt for us */
wdenk7a8e9bed2003-05-31 18:35:21 +0000161 if (next_irq_index > 3) {
162 return;
163 }
wdenk8bde7f72003-06-27 21:31:46 +0000164 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000165 return;
166 }
167 next_irq_index++;
168 }
169
wdenk8bde7f72003-06-27 21:31:46 +0000170
wdenk7a8e9bed2003-05-31 18:35:21 +0000171 if (-1 != sc520_pci_ints[pin]) {
wdenk8bde7f72003-06-27 21:31:46 +0000172 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
wdenk7a8e9bed2003-05-31 18:35:21 +0000173 sc520_pci_ints[pin]);
174 }
wdenk8bde7f72003-06-27 21:31:46 +0000175#if 0
176 printf("fixup_irq: device %d pin %c irq %d\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000177 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
178#endif
179}
180
181
wdenk8bde7f72003-06-27 21:31:46 +0000182static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
wdenk7a8e9bed2003-05-31 18:35:21 +0000183 pci_dev_t dev, struct pci_config_table *te)
184{
185 u32 io_base;
186 u32 temp;
wdenk8bde7f72003-06-27 21:31:46 +0000187
wdenk7a8e9bed2003-05-31 18:35:21 +0000188 pciauto_config_device(hose, dev);
wdenk8bde7f72003-06-27 21:31:46 +0000189
wdenk7a8e9bed2003-05-31 18:35:21 +0000190 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */
191 pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */
192 pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */
193 pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */
194 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */
195 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */
196 pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
wdenk8bde7f72003-06-27 21:31:46 +0000197
198 pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */
199 pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */
200 /* route MF0 to ~INT and MF3 to IRQ7
wdenk7a8e9bed2003-05-31 18:35:21 +0000201 * reserve all others */
wdenk8bde7f72003-06-27 21:31:46 +0000202 pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
wdenk7a8e9bed2003-05-31 18:35:21 +0000203 pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */
204 pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */
wdenk8bde7f72003-06-27 21:31:46 +0000205
wdenk7a8e9bed2003-05-31 18:35:21 +0000206 if (te->device != 0xac56) {
207 pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */
208 pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */
209 pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */
210 pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */
211 pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */
212 } else {
213 pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */
214 }
215 pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */
wdenk8bde7f72003-06-27 21:31:46 +0000216
217
wdenk7a8e9bed2003-05-31 18:35:21 +0000218 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
219 io_base &= ~0xfL;
wdenk8bde7f72003-06-27 21:31:46 +0000220
wdenk7a8e9bed2003-05-31 18:35:21 +0000221 writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
222 writel(0, io_base+0x10); /* CLKRUN default */
223 writel(0, io_base+0x20); /* CLKRUN default */
wdenk8bde7f72003-06-27 21:31:46 +0000224
wdenk7a8e9bed2003-05-31 18:35:21 +0000225}
226
227
wdenk7a8e9bed2003-05-31 18:35:21 +0000228static struct pci_config_table pci_sc520_spunk_config_table[] = {
wdenk8bde7f72003-06-27 21:31:46 +0000229 { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
230 { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
wdenk7a8e9bed2003-05-31 18:35:21 +0000231 { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
232};
233
234static struct pci_controller sc520_spunk_hose = {
235 fixup_irq: pci_sc520_spunk_fixup_irq,
236 config_table: pci_sc520_spunk_config_table,
237 first_busno: 0x00,
238 last_busno: 0xff,
239};
240
241void pci_init_board(void)
242{
243 pci_sc520_init(&sc520_spunk_hose);
244}
245
246
247/* set up the ISA bus timing and system address mappings */
248static void bus_init(void)
249{
wdenk8bde7f72003-06-27 21:31:46 +0000250 /* versions
wdenk7a8e9bed2003-05-31 18:35:21 +0000251 * 0 Hyglo versions 0.95 and 0.96 (large baords)
252 * ?? Hyglo version 0.97 (small board)
253 * 10 Spunk board
254 */
255 int version = read_mmcr_byte(SC520_SYSINFO);
wdenk8bde7f72003-06-27 21:31:46 +0000256
wdenk7a8e9bed2003-05-31 18:35:21 +0000257 if (version) {
258 /* set up the GP IO pins (for the Spunk board) */
259 write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */
260 write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */
261 write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */
262 write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */
wdenk8bde7f72003-06-27 21:31:46 +0000263 write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */
wdenk7a8e9bed2003-05-31 18:35:21 +0000264 write_mmcr_byte(SC520_CLKSEL, 0x70);
wdenk8bde7f72003-06-27 21:31:46 +0000265
wdenk7a8e9bed2003-05-31 18:35:21 +0000266 write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */
267 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
268
269 } else {
270 /* set up the GP IO pins (for the Hyglo board) */
271 write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */
272 write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */
273 write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */
274 write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */
wdenk8bde7f72003-06-27 21:31:46 +0000275 write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */
wdenk7a8e9bed2003-05-31 18:35:21 +0000276 write_mmcr_byte(SC520_CLKSEL, 0x70);
wdenk8bde7f72003-06-27 21:31:46 +0000277
wdenk7a8e9bed2003-05-31 18:35:21 +0000278 write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */
279 }
wdenk8bde7f72003-06-27 21:31:46 +0000280
281 write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
wdenk7a8e9bed2003-05-31 18:35:21 +0000282 write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
283 write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
284 write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
285 write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
wdenk8bde7f72003-06-27 21:31:46 +0000286 write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
wdenk7a8e9bed2003-05-31 18:35:21 +0000287 write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
288
wdenk8bde7f72003-06-27 21:31:46 +0000289 write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */
290
wdenk7a8e9bed2003-05-31 18:35:21 +0000291 /* adjust the memory map:
292 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
293 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
wdenk8bde7f72003-06-27 21:31:46 +0000294 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
295
296
wdenk7a8e9bed2003-05-31 18:35:21 +0000297 /* bootcs */
wdenk8bde7f72003-06-27 21:31:46 +0000298 write_mmcr_long(SC520_PAR12, 0x8bffe800);
299
wdenk7a8e9bed2003-05-31 18:35:21 +0000300 /* IDE0 = GPCS6 1f0-1f7 */
wdenk8bde7f72003-06-27 21:31:46 +0000301 write_mmcr_long(SC520_PAR3, 0x380801f0);
wdenk7a8e9bed2003-05-31 18:35:21 +0000302
303 /* IDE1 = GPCS7 3f6 */
wdenk8bde7f72003-06-27 21:31:46 +0000304 write_mmcr_long(SC520_PAR4, 0x3c0003f6);
wdenk7a8e9bed2003-05-31 18:35:21 +0000305
wdenk8bde7f72003-06-27 21:31:46 +0000306 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
wdenk7a8e9bed2003-05-31 18:35:21 +0000307
wdenk8bde7f72003-06-27 21:31:46 +0000308 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
wdenk7a8e9bed2003-05-31 18:35:21 +0000309
310}
311
312
wdenk7a8e9bed2003-05-31 18:35:21 +0000313/* par usage:
314 * PAR0 (legacy_video)
315 * PAR1 (PCI ROM mapping)
wdenk8bde7f72003-06-27 21:31:46 +0000316 * PAR2
317 * PAR3 IDE
wdenk7a8e9bed2003-05-31 18:35:21 +0000318 * PAR4 IDE
319 * PAR5 (legacy_video)
wdenk8bde7f72003-06-27 21:31:46 +0000320 * PAR6
wdenk7a8e9bed2003-05-31 18:35:21 +0000321 * PAR7 (legacy_video)
322 * PAR8 (legacy_video)
323 * PAR9 (legacy_video)
324 * PAR10
325 * PAR11 (ISAROM)
326 * PAR12 BOOTCS
327 * PAR13
328 * PAR14
329 * PAR15
330 */
331
wdenk8bde7f72003-06-27 21:31:46 +0000332/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000333 * This function should map a chunk of size bytes
334 * of the system address space to the ISA bus
wdenk8bde7f72003-06-27 21:31:46 +0000335 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000336 * The function will return the memory address
337 * as seen by the host (which may very will be the
338 * same as the bus address)
339 */
wdenk8bde7f72003-06-27 21:31:46 +0000340u32 isa_map_rom(u32 bus_addr, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000341{
342 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000343
344 printf("isa_map_rom asked to map %d bytes at %x\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000345 size, bus_addr);
wdenk8bde7f72003-06-27 21:31:46 +0000346
wdenk7a8e9bed2003-05-31 18:35:21 +0000347 par = size;
348 if (par < 0x80000) {
349 par = 0x80000;
350 }
351 par >>= 12;
352 par--;
353 par&=0x7f;
354 par <<= 18;
355 par |= (bus_addr>>12);
356 par |= 0x50000000;
wdenk8bde7f72003-06-27 21:31:46 +0000357
wdenk7a8e9bed2003-05-31 18:35:21 +0000358 printf ("setting PAR11 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000359
wdenk7a8e9bed2003-05-31 18:35:21 +0000360 /* Map rom 0x10000 with PAR1 */
361 write_mmcr_long(SC520_PAR11, par);
wdenk8bde7f72003-06-27 21:31:46 +0000362
wdenk7a8e9bed2003-05-31 18:35:21 +0000363 return bus_addr;
364}
365
366/*
367 * this function removed any mapping created
368 * with pci_get_rom_window()
369 */
370void isa_unmap_rom(u32 addr)
371{
372 printf("isa_unmap_rom asked to unmap %x", addr);
373 if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
374 write_mmcr_long(SC520_PAR11, 0);
375 printf(" done\n");
376 return;
377 }
378 printf(" not ours\n");
379}
380
381#ifdef CONFIG_PCI
382#define PCI_ROM_TEMP_SPACE 0x10000
wdenk8bde7f72003-06-27 21:31:46 +0000383/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000384 * This function should map a chunk of size bytes
385 * of the system address space to the PCI bus,
386 * suitable to map PCI ROMS (bus address < 16M)
387 * the function will return the host memory address
388 * which should be converted into a bus address
wdenk8bde7f72003-06-27 21:31:46 +0000389 * before used to configure the PCI rom address
wdenk7a8e9bed2003-05-31 18:35:21 +0000390 * decoder
391 */
wdenk8bde7f72003-06-27 21:31:46 +0000392u32 pci_get_rom_window(struct pci_controller *hose, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000393{
394 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000395
wdenk7a8e9bed2003-05-31 18:35:21 +0000396 par = size;
397 if (par < 0x80000) {
398 par = 0x80000;
399 }
400 par >>= 16;
401 par--;
402 par&=0x7ff;
403 par <<= 14;
404 par |= (PCI_ROM_TEMP_SPACE>>16);
405 par |= 0x72000000;
wdenk8bde7f72003-06-27 21:31:46 +0000406
wdenk7a8e9bed2003-05-31 18:35:21 +0000407 printf ("setting PAR1 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000408
wdenk7a8e9bed2003-05-31 18:35:21 +0000409 /* Map rom 0x10000 with PAR1 */
410 write_mmcr_long(SC520_PAR1, par);
wdenk8bde7f72003-06-27 21:31:46 +0000411
wdenk7a8e9bed2003-05-31 18:35:21 +0000412 return PCI_ROM_TEMP_SPACE;
413}
414
415/*
416 * this function removed any mapping created
417 * with pci_get_rom_window()
418 */
419void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
420{
421 printf("pci_remove_rom_window: %x", addr);
422 if (addr == PCI_ROM_TEMP_SPACE) {
423 write_mmcr_long(SC520_PAR1, 0);
424 printf(" done\n");
425 return;
426 }
427 printf(" not ours\n");
wdenk8bde7f72003-06-27 21:31:46 +0000428
wdenk7a8e9bed2003-05-31 18:35:21 +0000429}
430
431/*
432 * This function is called in order to provide acces to the
wdenk8bde7f72003-06-27 21:31:46 +0000433 * legacy video I/O ports on the PCI bus.
434 * After this function accesses to I/O ports 0x3b0-0x3bb and
wdenk7a8e9bed2003-05-31 18:35:21 +0000435 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
wdenk8bde7f72003-06-27 21:31:46 +0000436 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000437 */
438int pci_enable_legacy_video_ports(struct pci_controller *hose)
439{
440 /* Map video memory to 0xa0000*/
441 write_mmcr_long(SC520_PAR0, 0x7200400a);
wdenk8bde7f72003-06-27 21:31:46 +0000442
wdenk7a8e9bed2003-05-31 18:35:21 +0000443 /* forward all I/O accesses to PCI */
wdenk8bde7f72003-06-27 21:31:46 +0000444 write_mmcr_byte(SC520_ADDDECCTL,
445 read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
446
447
wdenk7a8e9bed2003-05-31 18:35:21 +0000448 /* so we map away all io ports to pci (only way to access pci io
449 * below 0x400. But then we have to map back the portions that we dont
450 * use so that the generate cycles on the GPIO bus where the sio and
wdenk8bde7f72003-06-27 21:31:46 +0000451 * ISA slots are connected, this requre the use of several PAR registers
wdenk7a8e9bed2003-05-31 18:35:21 +0000452 */
wdenk8bde7f72003-06-27 21:31:46 +0000453
wdenk7a8e9bed2003-05-31 18:35:21 +0000454 /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
wdenk8bde7f72003-06-27 21:31:46 +0000455 write_mmcr_long(SC520_PAR5, 0x31f70100);
456
wdenk7a8e9bed2003-05-31 18:35:21 +0000457 /* com2 use 2f8-2ff */
wdenk8bde7f72003-06-27 21:31:46 +0000458
wdenk7a8e9bed2003-05-31 18:35:21 +0000459 /* bring 0x300 - 0x3af back to ISA using PAR7 */
wdenk8bde7f72003-06-27 21:31:46 +0000460 write_mmcr_long(SC520_PAR7, 0x30af0300);
461
wdenk7a8e9bed2003-05-31 18:35:21 +0000462 /* vga use 3b0-3bb */
wdenk8bde7f72003-06-27 21:31:46 +0000463
wdenk7a8e9bed2003-05-31 18:35:21 +0000464 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
wdenk8bde7f72003-06-27 21:31:46 +0000465 write_mmcr_long(SC520_PAR8, 0x300303bc);
466
wdenk7a8e9bed2003-05-31 18:35:21 +0000467 /* vga use 3c0-3df */
wdenk8bde7f72003-06-27 21:31:46 +0000468
wdenk7a8e9bed2003-05-31 18:35:21 +0000469 /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
wdenk8bde7f72003-06-27 21:31:46 +0000470 write_mmcr_long(SC520_PAR9, 0x301703e0);
471
472 /* com1 use 3f8-3ff */
wdenk7a8e9bed2003-05-31 18:35:21 +0000473
474 return 0;
475}
476#endif
477
478/*
479 * Miscelaneous platform dependent initialisations
480 */
481
482int board_init(void)
483{
wdenk8bde7f72003-06-27 21:31:46 +0000484 init_sc520();
wdenk7a8e9bed2003-05-31 18:35:21 +0000485 bus_init();
486 irq_init();
wdenk8bde7f72003-06-27 21:31:46 +0000487
wdenk7a8e9bed2003-05-31 18:35:21 +0000488 /* max drive current on SDRAM */
489 write_mmcr_word(SC520_DSCTL, 0x0100);
wdenk8bde7f72003-06-27 21:31:46 +0000490
wdenk7a8e9bed2003-05-31 18:35:21 +0000491 /* enter debug mode after next reset (only if jumper is also set) */
492 write_mmcr_byte(SC520_RESCFG, 0x08);
493 /* configure the software timer to 33.000MHz */
494 write_mmcr_byte(SC520_SWTMRCFG, 1);
495 gd->bus_clk = 33000000;
wdenk8bde7f72003-06-27 21:31:46 +0000496
wdenk7a8e9bed2003-05-31 18:35:21 +0000497 return 0;
498}
499
500int dram_init(void)
501{
502 init_sc520_dram();
503 return 0;
504}
505
506void show_boot_progress(int val)
507{
wdenk8bde7f72003-06-27 21:31:46 +0000508 int version = read_mmcr_byte(SC520_SYSINFO);
509
Heiko Schocher566a4942007-06-22 19:11:54 +0200510 if (val < -32) val = -1; /* let things compatible */
wdenk7a8e9bed2003-05-31 18:35:21 +0000511 if (version == 0) {
512 /* PIO31-PIO16 Data */
wdenk8bde7f72003-06-27 21:31:46 +0000513 write_mmcr_word(SC520_PIODATA31_16,
wdenk7a8e9bed2003-05-31 18:35:21 +0000514 (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
wdenk8bde7f72003-06-27 21:31:46 +0000515
wdenk7a8e9bed2003-05-31 18:35:21 +0000516 /* PIO0-PIO15 Data */
wdenk8bde7f72003-06-27 21:31:46 +0000517 write_mmcr_word(SC520_PIODATA15_0,
wdenk7a8e9bed2003-05-31 18:35:21 +0000518 (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
519 } else {
520 /* newer boards use PIO4-PIO12 */
521 /* PIO0-PIO15 Data */
wdenk8bde7f72003-06-27 21:31:46 +0000522#if 0
523 val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
wdenk7a8e9bed2003-05-31 18:35:21 +0000524#else
wdenk8bde7f72003-06-27 21:31:46 +0000525 val = (val & 0x007) | ((val & 0x07e) << 2);
wdenk7a8e9bed2003-05-31 18:35:21 +0000526#endif
wdenk8bde7f72003-06-27 21:31:46 +0000527 write_mmcr_word(SC520_PIODATA15_0,
wdenk7a8e9bed2003-05-31 18:35:21 +0000528 (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
529 }
530}
531
532
533int last_stage_init(void)
534{
wdenk8bde7f72003-06-27 21:31:46 +0000535
wdenk7a8e9bed2003-05-31 18:35:21 +0000536 int version = read_mmcr_byte(SC520_SYSINFO);
wdenk8bde7f72003-06-27 21:31:46 +0000537
wdenk7a8e9bed2003-05-31 18:35:21 +0000538 printf("Omicron Ceti SC520 Spunk revision %x\n", version);
wdenk8bde7f72003-06-27 21:31:46 +0000539
wdenk7a8e9bed2003-05-31 18:35:21 +0000540#if 0
541 if (version) {
542 int x, y;
wdenk8bde7f72003-06-27 21:31:46 +0000543
wdenk7a8e9bed2003-05-31 18:35:21 +0000544 printf("eeprom probe %d\n", spi_eeprom_probe(1));
wdenk8bde7f72003-06-27 21:31:46 +0000545
wdenk7a8e9bed2003-05-31 18:35:21 +0000546 spi_eeprom_read(1, 0, (u8*)&x, 2);
547 spi_eeprom_read(1, 1, (u8*)&y, 2);
548 printf("eeprom bytes %04x%04x\n", x, y);
549 x ^= 0xffff;
550 y ^= 0xffff;
551 spi_eeprom_write(1, 0, (u8*)&x, 2);
552 spi_eeprom_write(1, 1, (u8*)&y, 2);
wdenk8bde7f72003-06-27 21:31:46 +0000553
wdenk7a8e9bed2003-05-31 18:35:21 +0000554 spi_eeprom_read(1, 0, (u8*)&x, 2);
555 spi_eeprom_read(1, 1, (u8*)&y, 2);
556 printf("eeprom bytes %04x%04x\n", x, y);
wdenk8bde7f72003-06-27 21:31:46 +0000557
wdenk7a8e9bed2003-05-31 18:35:21 +0000558 } else {
559 int x, y;
wdenk8bde7f72003-06-27 21:31:46 +0000560
wdenk7a8e9bed2003-05-31 18:35:21 +0000561 printf("eeprom probe %d\n", mw_eeprom_probe(1));
wdenk8bde7f72003-06-27 21:31:46 +0000562
wdenk7a8e9bed2003-05-31 18:35:21 +0000563 mw_eeprom_read(1, 0, (u8*)&x, 2);
564 mw_eeprom_read(1, 1, (u8*)&y, 2);
565 printf("eeprom bytes %04x%04x\n", x, y);
wdenk8bde7f72003-06-27 21:31:46 +0000566
wdenk7a8e9bed2003-05-31 18:35:21 +0000567 x ^= 0xffff;
568 y ^= 0xffff;
569 mw_eeprom_write(1, 0, (u8*)&x, 2);
570 mw_eeprom_write(1, 1, (u8*)&y, 2);
wdenk8bde7f72003-06-27 21:31:46 +0000571
wdenk7a8e9bed2003-05-31 18:35:21 +0000572 mw_eeprom_read(1, 0, (u8*)&x, 2);
573 mw_eeprom_read(1, 1, (u8*)&y, 2);
574 printf("eeprom bytes %04x%04x\n", x, y);
wdenk8bde7f72003-06-27 21:31:46 +0000575
576
wdenk7a8e9bed2003-05-31 18:35:21 +0000577 }
578#endif
579
580 ds1722_probe(2);
wdenk8bde7f72003-06-27 21:31:46 +0000581
wdenk7a8e9bed2003-05-31 18:35:21 +0000582 return 0;
583}
584
wdenk8bde7f72003-06-27 21:31:46 +0000585void ssi_chip_select(int dev)
wdenk7a8e9bed2003-05-31 18:35:21 +0000586{
587 int version = read_mmcr_byte(SC520_SYSINFO);
wdenk8bde7f72003-06-27 21:31:46 +0000588
wdenk7a8e9bed2003-05-31 18:35:21 +0000589 if (version) {
590 /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
591 switch (dev) {
592 case 1: /* EEPROM */
593 write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
594 break;
wdenk8bde7f72003-06-27 21:31:46 +0000595
wdenk7a8e9bed2003-05-31 18:35:21 +0000596 case 2: /* Temp Probe */
597 write_mmcr_word(SC520_PIOSET31_16, 0x0002);
598 break;
wdenk8bde7f72003-06-27 21:31:46 +0000599
wdenk7a8e9bed2003-05-31 18:35:21 +0000600 case 3: /* CAN */
601 write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
602 break;
wdenk8bde7f72003-06-27 21:31:46 +0000603
604 case 4: /* AUX */
wdenk7a8e9bed2003-05-31 18:35:21 +0000605 write_mmcr_word(SC520_PIOSET31_16, 0x0001);
606 break;
wdenk8bde7f72003-06-27 21:31:46 +0000607
wdenk7a8e9bed2003-05-31 18:35:21 +0000608 case 0:
609 write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
610 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
611 break;
wdenk8bde7f72003-06-27 21:31:46 +0000612
wdenk7a8e9bed2003-05-31 18:35:21 +0000613 default:
614 printf("Illegal SSI device requested: %d\n", dev);
615 }
616 } else {
wdenk8bde7f72003-06-27 21:31:46 +0000617
wdenk7a8e9bed2003-05-31 18:35:21 +0000618 /* Globox board: Both EEPROM and TEMP are active-high */
619
620 switch (dev) {
621 case 1: /* EEPROM */
622 write_mmcr_word(SC520_PIOSET15_0, 0x0100);
623 break;
wdenk8bde7f72003-06-27 21:31:46 +0000624
wdenk7a8e9bed2003-05-31 18:35:21 +0000625 case 2: /* Temp Probe */
626 write_mmcr_word(SC520_PIOSET15_0, 0x0080);
627 break;
wdenk8bde7f72003-06-27 21:31:46 +0000628
wdenk7a8e9bed2003-05-31 18:35:21 +0000629 case 0:
630 write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
631 break;
wdenk8bde7f72003-06-27 21:31:46 +0000632
wdenk7a8e9bed2003-05-31 18:35:21 +0000633 default:
634 printf("Illegal SSI device requested: %d\n", dev);
635 }
wdenk8bde7f72003-06-27 21:31:46 +0000636 }
wdenk7a8e9bed2003-05-31 18:35:21 +0000637}
638
639
wdenk8bde7f72003-06-27 21:31:46 +0000640void spi_init_f(void)
wdenk7a8e9bed2003-05-31 18:35:21 +0000641{
642 read_mmcr_byte(SC520_SYSINFO) ?
wdenk8bde7f72003-06-27 21:31:46 +0000643 spi_eeprom_probe(1) :
wdenk7a8e9bed2003-05-31 18:35:21 +0000644 mw_eeprom_probe(1);
wdenk8bde7f72003-06-27 21:31:46 +0000645
wdenk7a8e9bed2003-05-31 18:35:21 +0000646}
647
wdenk8bde7f72003-06-27 21:31:46 +0000648ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000649{
650 int offset;
651 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000652
wdenk7a8e9bed2003-05-31 18:35:21 +0000653 offset = 0;
654 for (i=0;i<alen;i++) {
655 offset <<= 8;
656 offset |= addr[i];
657 }
wdenk8bde7f72003-06-27 21:31:46 +0000658
wdenk7a8e9bed2003-05-31 18:35:21 +0000659 return read_mmcr_byte(SC520_SYSINFO) ?
wdenk8bde7f72003-06-27 21:31:46 +0000660 spi_eeprom_read(1, offset, buffer, len) :
wdenk7a8e9bed2003-05-31 18:35:21 +0000661 mw_eeprom_read(1, offset, buffer, len);
662}
663
wdenk8bde7f72003-06-27 21:31:46 +0000664ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000665{
666 int offset;
667 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000668
wdenk7a8e9bed2003-05-31 18:35:21 +0000669 offset = 0;
670 for (i=0;i<alen;i++) {
671 offset <<= 8;
672 offset |= addr[i];
673 }
wdenk8bde7f72003-06-27 21:31:46 +0000674
wdenk7a8e9bed2003-05-31 18:35:21 +0000675 return read_mmcr_byte(SC520_SYSINFO) ?
wdenk8bde7f72003-06-27 21:31:46 +0000676 spi_eeprom_write(1, offset, buffer, len) :
wdenk7a8e9bed2003-05-31 18:35:21 +0000677 mw_eeprom_write(1, offset, buffer, len);
678}