blob: 209d3e23ce32fb9920501e1afe04441ad9040ddb [file] [log] [blame]
Marek Vasutd5914012011-01-19 04:40:37 +00001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51EVK Board
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#include <config_cmd_default.h>
28
29/*
30 * High Level Board Configuration Options
31 */
32/* An i.MX51 CPU */
33#define CONFIG_MX51
34#include <asm/arch/imx-regs.h>
35
36#define CONFIG_SYS_MX5_HCLK 24000000
37#define CONFIG_SYS_MX5_CLK32 32768
38#define CONFIG_DISPLAY_CPUINFO
39#define CONFIG_DISPLAY_BOARDINFO
40
Jana Rapava745525f2011-07-11 14:16:44 +000041#define CONFIG_SYS_TEXT_BASE 0x97800000
42
Aneesh Ve47f2db2011-06-16 23:30:48 +000043#define CONFIG_SYS_L2CACHE_OFF
Marek Vasutd5914012011-01-19 04:40:37 +000044
45/*
46 * Bootloader Components Configuration
47 */
48#define CONFIG_CMD_SPI
49#define CONFIG_CMD_SF
50#define CONFIG_CMD_MMC
51#define CONFIG_CMD_FAT
52#define CONFIG_CMD_IDE
53#undef CONFIG_CMD_IMLS
54
55/*
56 * Environmental settings
57 */
58
59#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
60#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
61#define CONFIG_ENV_SIZE (4 * 1024)
62
63/*
64 * ATAG setup
65 */
66#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
67#define CONFIG_REVISION_TAG
68#define CONFIG_SETUP_MEMORY_TAGS
69#define CONFIG_INITRD_TAG
70
Grant Likely2fa8ca92011-03-28 09:59:07 +000071#define CONFIG_OF_LIBFDT 1
72
Marek Vasutd5914012011-01-19 04:40:37 +000073/*
74 * Size of malloc() pool
75 */
76#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
77
78#define CONFIG_BOARD_EARLY_INIT_F
79#define BOARD_LATE_INIT
80
81/*
82 * Hardware drivers
83 */
84#define CONFIG_MXC_UART
85#define CONFIG_SYS_MX51_UART1
86#define CONFIG_CONS_INDEX 1
87#define CONFIG_BAUDRATE 115200
88#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
89
90#define CONFIG_MXC_GPIO
91
92/*
93 * SPI Interface
94 */
95#ifdef CONFIG_CMD_SPI
96
97#define CONFIG_HARD_SPI
98#define CONFIG_MXC_SPI
99#define CONFIG_DEFAULT_SPI_BUS 1
100#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
101
102/* SPI FLASH */
103#ifdef CONFIG_CMD_SF
104
105#define CONFIG_SPI_FLASH
106#define CONFIG_SPI_FLASH_SST
107#define CONFIG_SPI_FLASH_CS (1 | 121 << 8)
108#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
109#define CONFIG_SF_DEFAULT_SPEED 25000000
110
111#define CONFIG_ENV_SPI_CS (1 | 121 << 8)
112#define CONFIG_ENV_SPI_BUS 0
113#define CONFIG_ENV_SPI_MAX_HZ 25000000
114#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
115#define CONFIG_FSL_ENV_IN_SF
116#define CONFIG_ENV_IS_IN_SPI_FLASH
117#define CONFIG_SYS_NO_FLASH
118
119#else
120#define CONFIG_ENV_IS_NOWHERE
121#endif
122
123/* SPI PMIC */
124#define CONFIG_FSL_PMIC
125#define CONFIG_FSL_PMIC_BUS 0
126#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
127#define CONFIG_FSL_PMIC_CLK 25000000
128#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
129#define CONFIG_RTC_MC13783
130#endif
131
132/*
133 * MMC Configs
134 */
135#ifdef CONFIG_CMD_MMC
136#define CONFIG_MMC
137#define CONFIG_GENERIC_MMC
138#define CONFIG_FSL_ESDHC
139#define CONFIG_SYS_FSL_ESDHC_ADDR 0
140#define CONFIG_SYS_FSL_ESDHC_NUM 2
141#endif
142
143/*
144 * ATA/IDE
145 */
146#ifdef CONFIG_CMD_IDE
147#define CONFIG_LBA48
148#undef CONFIG_IDE_LED
149#undef CONFIG_IDE_RESET
150
151#define CONFIG_MX51_PATA
152
153#define __io
154
155#define CONFIG_SYS_IDE_MAXBUS 1
156#define CONFIG_SYS_IDE_MAXDEVICE 1
157
158#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000
159#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
160
161#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0
162#define CONFIG_SYS_ATA_REG_OFFSET 0xa0
163#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8
164
165#define CONFIG_SYS_ATA_STRIDE 4
166
167#define CONFIG_IDE_PREINIT
168#define CONFIG_MXC_ATA_PIO_MODE 4
169#endif
170
171/*
172 * Filesystems
173 */
174#ifdef CONFIG_CMD_FAT
175#define CONFIG_DOS_PARTITION
176#endif
177
178#undef CONFIG_CMD_PING
179#undef CONFIG_CMD_DHCP
180#undef CONFIG_CMD_NET
181#undef CONFIG_CMD_NFS
182#define CONFIG_CMD_DATE
183
184/*
185 * Miscellaneous configurable options
186 */
187#define CONFIG_ENV_OVERWRITE
188#define CONFIG_BOOTDELAY 3
189#define CONFIG_LOADADDR 0x90800000
190
191#define CONFIG_SYS_LONGHELP /* undef to save memory */
192#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
193#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
194#define CONFIG_SYS_PROMPT "Efika> "
195#define CONFIG_AUTO_COMPLETE
196#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
197/* Print Buffer Size */
198#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
199#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
200#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
201
202#define CONFIG_SYS_MEMTEST_START 0x90000000
203#define CONFIG_SYS_MEMTEST_END 0x10000
204
205#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
206
207#define CONFIG_SYS_HZ 1000
208#define CONFIG_CMDLINE_EDITING
209
210/*-----------------------------------------------------------------------
211 * Stack sizes
212 *
213 * The stack sizes are set up in start.S using the settings below
214 */
215#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
216
217/*-----------------------------------------------------------------------
218 * Physical Memory Map
219 */
220#define CONFIG_NR_DRAM_BANKS 1
221#define PHYS_SDRAM_1 CSD0_BASE_ADDR
222#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
223
224#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
225#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
226#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
227
228#define CONFIG_SYS_INIT_SP_OFFSET \
229 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
230#define CONFIG_SYS_INIT_SP_ADDR \
231 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
232
233#define CONFIG_SYS_DDR_CLKSEL 0
234#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
235
236#endif