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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek679b9942015-09-30 17:26:55 +02002/*
3 * (C) Copyright 2015 - 2016 Xilinx, Inc.
Michal Simek174d72842023-07-10 14:35:49 +02004 * Michal Simek <michal.simek@amd.com>
Michal Simek679b9942015-09-30 17:26:55 +02005 */
6#include <common.h>
Michal Simek49c4c782016-09-08 15:06:22 +02007#include <dm.h>
Michal Simek679b9942015-09-30 17:26:55 +02008#include <ahci.h>
Michal Simekf6f54512022-02-07 10:36:33 +01009#include <generic-phy.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Michal Simekf6f54512022-02-07 10:36:33 +010011#include <reset.h>
Michal Simek679b9942015-09-30 17:26:55 +020012#include <scsi.h>
Michal Simek679b9942015-09-30 17:26:55 +020013#include <asm/io.h>
Michal Simekf6f54512022-02-07 10:36:33 +010014#include <dm/device_compat.h>
Peng Mad2ebc382019-04-17 10:10:50 +000015#include <linux/ioport.h>
Michal Simek679b9942015-09-30 17:26:55 +020016
17/* Vendor Specific Register Offsets */
18#define AHCI_VEND_PCFG 0xA4
19#define AHCI_VEND_PPCFG 0xA8
20#define AHCI_VEND_PP2C 0xAC
21#define AHCI_VEND_PP3C 0xB0
22#define AHCI_VEND_PP4C 0xB4
23#define AHCI_VEND_PP5C 0xB8
Yuantian Tang79ed61e2018-07-13 17:25:30 +080024#define AHCI_VEND_AXICC 0xBc
Michal Simek679b9942015-09-30 17:26:55 +020025#define AHCI_VEND_PAXIC 0xC0
26#define AHCI_VEND_PTC 0xC8
27
28/* Vendor Specific Register bit definitions */
29#define PAXIC_ADBW_BW64 0x1
30#define PAXIC_MAWIDD (1 << 8)
31#define PAXIC_MARIDD (1 << 16)
32#define PAXIC_OTL (0x4 << 20)
33
34#define PCFG_TPSS_VAL (0x32 << 16)
35#define PCFG_TPRS_VAL (0x2 << 12)
36#define PCFG_PAD_VAL 0x2
37
38#define PPCFG_TTA 0x1FFFE
39#define PPCFG_PSSO_EN (1 << 28)
40#define PPCFG_PSS_EN (1 << 29)
41#define PPCFG_ESDF_EN (1 << 31)
42
43#define PP2C_CIBGMN 0x0F
44#define PP2C_CIBGMX (0x25 << 8)
45#define PP2C_CIBGN (0x18 << 16)
46#define PP2C_CINMP (0x29 << 24)
47
48#define PP3C_CWBGMN 0x04
49#define PP3C_CWBGMX (0x0B << 8)
50#define PP3C_CWBGN (0x08 << 16)
51#define PP3C_CWNMP (0x0F << 24)
52
53#define PP4C_BMX 0x0a
54#define PP4C_BNM (0x08 << 8)
55#define PP4C_SFD (0x4a << 16)
56#define PP4C_PTST (0x06 << 24)
57
58#define PP5C_RIT 0x60216
59#define PP5C_RCT (0x7f0 << 20)
60
61#define PTC_RX_WM_VAL 0x40
62#define PTC_RSVD (1 << 27)
63
64#define PORT0_BASE 0x100
65#define PORT1_BASE 0x180
66
67/* Port Control Register Bit Definitions */
68#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
69#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
70#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
71#define PORT_SCTL_IPM (0x3 << 8)
72
73#define PORT_BASE 0x100
74#define PORT_OFFSET 0x80
75#define NR_PORTS 2
76#define DRV_NAME "ahci-ceva"
77#define CEVA_FLAG_BROKEN_GEN2 1
78
Yuantian Tang79ed61e2018-07-13 17:25:30 +080079/* flag bit definition */
80#define FLAG_COHERENT 1
81
82/* register config value */
83#define CEVA_PHY1_CFG 0xa003fffe
84#define CEVA_PHY2_CFG 0x28184d1f
85#define CEVA_PHY3_CFG 0x0e081509
86#define CEVA_TRANS_CFG 0x08000029
87#define CEVA_AXICC_CFG 0x3fffffff
88
Peng Madf983a72018-08-01 14:15:43 +080089/* for ls1021a */
Peng Maaaaffe92018-10-22 10:39:49 +080090#define LS1021_AHCI_VEND_AXICC 0xC0
Peng Madf983a72018-08-01 14:15:43 +080091#define LS1021_CEVA_PHY2_CFG 0x28183414
92#define LS1021_CEVA_PHY3_CFG 0x0e080e06
93#define LS1021_CEVA_PHY4_CFG 0x064a080b
94#define LS1021_CEVA_PHY5_CFG 0x2aa86470
95
Peng Mad2ebc382019-04-17 10:10:50 +000096/* ecc val pair */
97#define ECC_DIS_VAL_CH1 0x00020000
Peng Maaaaffe92018-10-22 10:39:49 +080098#define ECC_DIS_VAL_CH2 0x80000000
Peng Mad2ebc382019-04-17 10:10:50 +000099#define ECC_DIS_VAL_CH3 0x40000000
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800100
101enum ceva_soc {
102 CEVA_1V84,
103 CEVA_LS1012A,
Peng Madf983a72018-08-01 14:15:43 +0800104 CEVA_LS1021A,
Peng Mad2ebc382019-04-17 10:10:50 +0000105 CEVA_LS1028A,
Peng Ma822d0602018-08-01 11:35:15 +0800106 CEVA_LS1043A,
Peng Ma5fcae592018-10-11 10:34:19 +0000107 CEVA_LS1046A,
Peng Maaaaffe92018-10-22 10:39:49 +0800108 CEVA_LS1088A,
Peng Ma1039d1a2018-10-22 10:43:20 +0800109 CEVA_LS2080A,
Michal Simekc3898a82018-04-06 13:32:52 +0200110};
111
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800112struct ceva_sata_priv {
113 ulong base;
Peng Mad2ebc382019-04-17 10:10:50 +0000114 ulong ecc_base;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800115 enum ceva_soc soc;
116 ulong flag;
117};
118
119static int ceva_init_sata(struct ceva_sata_priv *priv)
Michal Simek679b9942015-09-30 17:26:55 +0200120{
Peng Mad2ebc382019-04-17 10:10:50 +0000121 ulong ecc_addr = priv->ecc_base;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800122 ulong base = priv->base;
Michal Simek679b9942015-09-30 17:26:55 +0200123 ulong tmp;
Michal Simek679b9942015-09-30 17:26:55 +0200124
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800125 switch (priv->soc) {
126 case CEVA_1V84:
127 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
128 writel(tmp, base + AHCI_VEND_PAXIC);
129 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
130 writel(tmp, base + AHCI_VEND_PCFG);
Michal Simek679b9942015-09-30 17:26:55 +0200131 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800132 writel(tmp, base + AHCI_VEND_PPCFG);
Michal Simek679b9942015-09-30 17:26:55 +0200133 tmp = PTC_RX_WM_VAL | PTC_RSVD;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800134 writel(tmp, base + AHCI_VEND_PTC);
135 break;
Michal Simek679b9942015-09-30 17:26:55 +0200136
Peng Madf983a72018-08-01 14:15:43 +0800137 case CEVA_LS1021A:
Peng Mad2ebc382019-04-17 10:10:50 +0000138 if (!ecc_addr)
139 return -EINVAL;
140 writel(ECC_DIS_VAL_CH1, ecc_addr);
Peng Madf983a72018-08-01 14:15:43 +0800141 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
142 writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
143 writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
144 writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
145 writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
146 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Peng Madf983a72018-08-01 14:15:43 +0800147 break;
148
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800149 case CEVA_LS1012A:
Peng Ma822d0602018-08-01 11:35:15 +0800150 case CEVA_LS1043A:
Peng Ma5fcae592018-10-11 10:34:19 +0000151 case CEVA_LS1046A:
Peng Mad2ebc382019-04-17 10:10:50 +0000152 if (!ecc_addr)
153 return -EINVAL;
154 writel(ECC_DIS_VAL_CH2, ecc_addr);
Peng Ma1039d1a2018-10-22 10:43:20 +0800155 /* fallthrough */
156 case CEVA_LS2080A:
Peng Maaaaffe92018-10-22 10:39:49 +0800157 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
158 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Peng Maaaaffe92018-10-22 10:39:49 +0800159 break;
160
Peng Mad2ebc382019-04-17 10:10:50 +0000161 case CEVA_LS1028A:
Peng Maaaaffe92018-10-22 10:39:49 +0800162 case CEVA_LS1088A:
Peng Mad2ebc382019-04-17 10:10:50 +0000163 if (!ecc_addr)
164 return -EINVAL;
165 writel(ECC_DIS_VAL_CH3, ecc_addr);
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800166 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
167 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800168 break;
Michal Simek679b9942015-09-30 17:26:55 +0200169 }
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800170
Peng Mad2ebc382019-04-17 10:10:50 +0000171 if (priv->flag & FLAG_COHERENT)
172 writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
173
Michal Simek679b9942015-09-30 17:26:55 +0200174 return 0;
175}
Michal Simek49c4c782016-09-08 15:06:22 +0200176
Michal Simekc3898a82018-04-06 13:32:52 +0200177static int sata_ceva_bind(struct udevice *dev)
178{
179 struct udevice *scsi_dev;
180
181 return ahci_bind_scsi(dev, &scsi_dev);
182}
183
Michal Simek49c4c782016-09-08 15:06:22 +0200184static int sata_ceva_probe(struct udevice *dev)
185{
Michal Simekc3898a82018-04-06 13:32:52 +0200186 struct ceva_sata_priv *priv = dev_get_priv(dev);
Michal Simekf6f54512022-02-07 10:36:33 +0100187 struct phy phy;
188 int ret;
189 struct reset_ctl_bulk resets;
190
191 ret = generic_phy_get_by_index(dev, 0, &phy);
192 if (!ret) {
193 dev_dbg(dev, "Perform PHY initialization\n");
194 ret = generic_phy_init(&phy);
195 if (ret)
196 return ret;
197 } else if (ret != -ENOENT) {
198 dev_dbg(dev, "could not get phy (err %d)\n", ret);
199 return ret;
200 }
201
202 /* reset is optional */
203 ret = reset_get_bulk(dev, &resets);
204 if (ret && ret != -ENOTSUPP && ret != -ENOENT) {
205 dev_dbg(dev, "Getting reset fails (err %d)\n", ret);
206 return ret;
207 }
208
209 /* Just trigger reset when reset is specified */
210 if (!ret) {
211 dev_dbg(dev, "Perform IP reset\n");
212 ret = reset_deassert_bulk(&resets);
213 if (ret) {
214 dev_dbg(dev, "Reset fails (err %d)\n", ret);
215 reset_release_bulk(&resets);
216 return ret;
217 }
218 }
219
Jonas Karlman017ae492023-08-31 22:16:37 +0000220 if (generic_phy_valid(&phy)) {
Michal Simekf6f54512022-02-07 10:36:33 +0100221 dev_dbg(dev, "Perform PHY power on\n");
222 ret = generic_phy_power_on(&phy);
223 if (ret) {
224 dev_dbg(dev, "PHY power on failed (err %d)\n", ret);
225 return ret;
226 }
227 }
Michal Simek49c4c782016-09-08 15:06:22 +0200228
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800229 ceva_init_sata(priv);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600230
Michal Simekc3898a82018-04-06 13:32:52 +0200231 return ahci_probe_scsi(dev, priv->base);
Michal Simek49c4c782016-09-08 15:06:22 +0200232}
233
234static const struct udevice_id sata_ceva_ids[] = {
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800235 { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
236 { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
Peng Madf983a72018-08-01 14:15:43 +0800237 { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
Peng Mad2ebc382019-04-17 10:10:50 +0000238 { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
Peng Ma822d0602018-08-01 11:35:15 +0800239 { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
Peng Ma5fcae592018-10-11 10:34:19 +0000240 { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
Peng Maaaaffe92018-10-22 10:39:49 +0800241 { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
Peng Ma1039d1a2018-10-22 10:43:20 +0800242 { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
Michal Simek49c4c782016-09-08 15:06:22 +0200243 { }
244};
245
Simon Glassd1998a92020-12-03 16:55:21 -0700246static int sata_ceva_of_to_plat(struct udevice *dev)
Michal Simek49c4c782016-09-08 15:06:22 +0200247{
Michal Simekc3898a82018-04-06 13:32:52 +0200248 struct ceva_sata_priv *priv = dev_get_priv(dev);
Peng Mad2ebc382019-04-17 10:10:50 +0000249 struct resource res_regs;
250 int ret;
Michal Simek49c4c782016-09-08 15:06:22 +0200251
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800252 if (dev_read_bool(dev, "dma-coherent"))
253 priv->flag |= FLAG_COHERENT;
254
255 priv->base = dev_read_addr(dev);
Michal Simekc3898a82018-04-06 13:32:52 +0200256 if (priv->base == FDT_ADDR_T_NONE)
Michal Simek49c4c782016-09-08 15:06:22 +0200257 return -EINVAL;
258
Michael Wallecde9b142021-10-13 18:14:20 +0200259 ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
Peng Mad2ebc382019-04-17 10:10:50 +0000260 if (ret)
261 priv->ecc_base = 0;
262 else
263 priv->ecc_base = res_regs.start;
264
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800265 priv->soc = dev_get_driver_data(dev);
266
Peng Mad2ebc382019-04-17 10:10:50 +0000267 debug("ccsr-sata-base %lx\t ecc-base %lx\n",
268 priv->base,
269 priv->ecc_base);
270
Michal Simek49c4c782016-09-08 15:06:22 +0200271 return 0;
272}
273
274U_BOOT_DRIVER(ceva_host_blk) = {
275 .name = "ceva_sata",
Michal Simekc3898a82018-04-06 13:32:52 +0200276 .id = UCLASS_AHCI,
Michal Simek49c4c782016-09-08 15:06:22 +0200277 .of_match = sata_ceva_ids,
Michal Simekc3898a82018-04-06 13:32:52 +0200278 .bind = sata_ceva_bind,
Simon Glassf6ab5a92017-06-14 21:28:43 -0600279 .ops = &scsi_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700280 .priv_auto = sizeof(struct ceva_sata_priv),
Michal Simek49c4c782016-09-08 15:06:22 +0200281 .probe = sata_ceva_probe,
Simon Glassd1998a92020-12-03 16:55:21 -0700282 .of_to_plat = sata_ceva_of_to_plat,
Michal Simek49c4c782016-09-08 15:06:22 +0200283};