Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 - 2016 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 5 | */ |
| 6 | #include <common.h> |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 7 | #include <dm.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 8 | #include <ahci.h> |
| 9 | #include <scsi.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | |
| 12 | /* Vendor Specific Register Offsets */ |
| 13 | #define AHCI_VEND_PCFG 0xA4 |
| 14 | #define AHCI_VEND_PPCFG 0xA8 |
| 15 | #define AHCI_VEND_PP2C 0xAC |
| 16 | #define AHCI_VEND_PP3C 0xB0 |
| 17 | #define AHCI_VEND_PP4C 0xB4 |
| 18 | #define AHCI_VEND_PP5C 0xB8 |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 19 | #define AHCI_VEND_AXICC 0xBc |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 20 | #define AHCI_VEND_PAXIC 0xC0 |
| 21 | #define AHCI_VEND_PTC 0xC8 |
| 22 | |
| 23 | /* Vendor Specific Register bit definitions */ |
| 24 | #define PAXIC_ADBW_BW64 0x1 |
| 25 | #define PAXIC_MAWIDD (1 << 8) |
| 26 | #define PAXIC_MARIDD (1 << 16) |
| 27 | #define PAXIC_OTL (0x4 << 20) |
| 28 | |
| 29 | #define PCFG_TPSS_VAL (0x32 << 16) |
| 30 | #define PCFG_TPRS_VAL (0x2 << 12) |
| 31 | #define PCFG_PAD_VAL 0x2 |
| 32 | |
| 33 | #define PPCFG_TTA 0x1FFFE |
| 34 | #define PPCFG_PSSO_EN (1 << 28) |
| 35 | #define PPCFG_PSS_EN (1 << 29) |
| 36 | #define PPCFG_ESDF_EN (1 << 31) |
| 37 | |
| 38 | #define PP2C_CIBGMN 0x0F |
| 39 | #define PP2C_CIBGMX (0x25 << 8) |
| 40 | #define PP2C_CIBGN (0x18 << 16) |
| 41 | #define PP2C_CINMP (0x29 << 24) |
| 42 | |
| 43 | #define PP3C_CWBGMN 0x04 |
| 44 | #define PP3C_CWBGMX (0x0B << 8) |
| 45 | #define PP3C_CWBGN (0x08 << 16) |
| 46 | #define PP3C_CWNMP (0x0F << 24) |
| 47 | |
| 48 | #define PP4C_BMX 0x0a |
| 49 | #define PP4C_BNM (0x08 << 8) |
| 50 | #define PP4C_SFD (0x4a << 16) |
| 51 | #define PP4C_PTST (0x06 << 24) |
| 52 | |
| 53 | #define PP5C_RIT 0x60216 |
| 54 | #define PP5C_RCT (0x7f0 << 20) |
| 55 | |
| 56 | #define PTC_RX_WM_VAL 0x40 |
| 57 | #define PTC_RSVD (1 << 27) |
| 58 | |
| 59 | #define PORT0_BASE 0x100 |
| 60 | #define PORT1_BASE 0x180 |
| 61 | |
| 62 | /* Port Control Register Bit Definitions */ |
| 63 | #define PORT_SCTL_SPD_GEN3 (0x3 << 4) |
| 64 | #define PORT_SCTL_SPD_GEN2 (0x2 << 4) |
| 65 | #define PORT_SCTL_SPD_GEN1 (0x1 << 4) |
| 66 | #define PORT_SCTL_IPM (0x3 << 8) |
| 67 | |
| 68 | #define PORT_BASE 0x100 |
| 69 | #define PORT_OFFSET 0x80 |
| 70 | #define NR_PORTS 2 |
| 71 | #define DRV_NAME "ahci-ceva" |
| 72 | #define CEVA_FLAG_BROKEN_GEN2 1 |
| 73 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 74 | /* flag bit definition */ |
| 75 | #define FLAG_COHERENT 1 |
| 76 | |
| 77 | /* register config value */ |
| 78 | #define CEVA_PHY1_CFG 0xa003fffe |
| 79 | #define CEVA_PHY2_CFG 0x28184d1f |
| 80 | #define CEVA_PHY3_CFG 0x0e081509 |
| 81 | #define CEVA_TRANS_CFG 0x08000029 |
| 82 | #define CEVA_AXICC_CFG 0x3fffffff |
| 83 | |
| 84 | /* ecc addr-val pair */ |
| 85 | #define ECC_DIS_ADDR_CH2 0x80000000 |
| 86 | #define ECC_DIS_VAL_CH2 0x20140520 |
| 87 | |
| 88 | enum ceva_soc { |
| 89 | CEVA_1V84, |
| 90 | CEVA_LS1012A, |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame^] | 91 | CEVA_LS1043A, |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 92 | }; |
| 93 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 94 | struct ceva_sata_priv { |
| 95 | ulong base; |
| 96 | enum ceva_soc soc; |
| 97 | ulong flag; |
| 98 | }; |
| 99 | |
| 100 | static int ceva_init_sata(struct ceva_sata_priv *priv) |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 101 | { |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 102 | ulong base = priv->base; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 103 | ulong tmp; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 104 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 105 | switch (priv->soc) { |
| 106 | case CEVA_1V84: |
| 107 | tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; |
| 108 | writel(tmp, base + AHCI_VEND_PAXIC); |
| 109 | tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL; |
| 110 | writel(tmp, base + AHCI_VEND_PCFG); |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 111 | tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 112 | writel(tmp, base + AHCI_VEND_PPCFG); |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 113 | tmp = PTC_RX_WM_VAL | PTC_RSVD; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 114 | writel(tmp, base + AHCI_VEND_PTC); |
| 115 | break; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 116 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 117 | case CEVA_LS1012A: |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame^] | 118 | case CEVA_LS1043A: |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 119 | writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); |
| 120 | writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); |
| 121 | writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); |
| 122 | if (priv->flag & FLAG_COHERENT) |
| 123 | writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); |
| 124 | break; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 125 | } |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 126 | |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 127 | return 0; |
| 128 | } |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 129 | |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 130 | static int sata_ceva_bind(struct udevice *dev) |
| 131 | { |
| 132 | struct udevice *scsi_dev; |
| 133 | |
| 134 | return ahci_bind_scsi(dev, &scsi_dev); |
| 135 | } |
| 136 | |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 137 | static int sata_ceva_probe(struct udevice *dev) |
| 138 | { |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 139 | struct ceva_sata_priv *priv = dev_get_priv(dev); |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 140 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 141 | ceva_init_sata(priv); |
Simon Glass | 7cf1afc | 2017-06-14 21:28:37 -0600 | [diff] [blame] | 142 | |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 143 | return ahci_probe_scsi(dev, priv->base); |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static const struct udevice_id sata_ceva_ids[] = { |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 147 | { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, |
| 148 | { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame^] | 149 | { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 150 | { } |
| 151 | }; |
| 152 | |
| 153 | static int sata_ceva_ofdata_to_platdata(struct udevice *dev) |
| 154 | { |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 155 | struct ceva_sata_priv *priv = dev_get_priv(dev); |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 156 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 157 | if (dev_read_bool(dev, "dma-coherent")) |
| 158 | priv->flag |= FLAG_COHERENT; |
| 159 | |
| 160 | priv->base = dev_read_addr(dev); |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 161 | if (priv->base == FDT_ADDR_T_NONE) |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 162 | return -EINVAL; |
| 163 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 164 | priv->soc = dev_get_driver_data(dev); |
| 165 | |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | U_BOOT_DRIVER(ceva_host_blk) = { |
| 170 | .name = "ceva_sata", |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 171 | .id = UCLASS_AHCI, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 172 | .of_match = sata_ceva_ids, |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 173 | .bind = sata_ceva_bind, |
Simon Glass | f6ab5a9 | 2017-06-14 21:28:43 -0600 | [diff] [blame] | 174 | .ops = &scsi_ops, |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 175 | .priv_auto_alloc_size = sizeof(struct ceva_sata_priv), |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 176 | .probe = sata_ceva_probe, |
| 177 | .ofdata_to_platdata = sata_ceva_ofdata_to_platdata, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 178 | }; |