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Sergei Poselenovb4489622007-07-05 08:17:37 +02001/*
2 * (C) Copyright 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Author: Igor Lisitsin <igor@emcraft.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27
28/* Cache test
29 *
30 * This test verifies the CPU data and instruction cache using
31 * several test scenarios.
32 */
33
Sergei Poselenovb4489622007-07-05 08:17:37 +020034#include <post.h>
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#if CONFIG_POST & CONFIG_SYS_POST_CACHE
Sergei Poselenovb4489622007-07-05 08:17:37 +020037
38#include <asm/mmu.h>
39#include <watchdog.h>
40
41#define CACHE_POST_SIZE 1024
42
Sergei Poselenovb4489622007-07-05 08:17:37 +020043int cache_post_test1 (int tlb, void *p, int size);
44int cache_post_test2 (int tlb, void *p, int size);
45int cache_post_test3 (int tlb, void *p, int size);
46int cache_post_test4 (int tlb, void *p, int size);
47int cache_post_test5 (int tlb, void *p, int size);
48int cache_post_test6 (int tlb, void *p, int size);
49
Stefan Roeseeb2b4012007-08-14 14:39:44 +020050#ifdef CONFIG_440
Sergei Poselenovb4489622007-07-05 08:17:37 +020051static unsigned char testarea[CACHE_POST_SIZE]
52__attribute__((__aligned__(CACHE_POST_SIZE)));
Stefan Roeseeb2b4012007-08-14 14:39:44 +020053#endif
Sergei Poselenovb4489622007-07-05 08:17:37 +020054
55int cache_post_test (int flags)
56{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
Stefan Roeseeb2b4012007-08-14 14:39:44 +020058 int ints;
59 int res = 0;
Stefan Roese2e583d62007-12-26 20:20:19 +010060 int tlb = -1; /* index to the victim TLB entry */
Stefan Roeseeb2b4012007-08-14 14:39:44 +020061
62 /*
63 * All 44x variants deal with cache management differently
64 * because they have the address translation always enabled.
65 * The 40x ppc's don't use address translation in U-Boot at all,
66 * so we have to distinguish here between 40x and 44x.
67 */
68#ifdef CONFIG_440
69 int word0, i;
Sergei Poselenovb4489622007-07-05 08:17:37 +020070
Stefan Roesed9172212007-12-22 12:18:26 +010071 /*
72 * Allocate a new TLB entry, since we are going to modify
73 * the write-through and caching inhibited storage attributes.
74 */
75 program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
76 TLB_WORD2_I_ENABLE);
Sergei Poselenovb4489622007-07-05 08:17:37 +020077
Stefan Roesed9172212007-12-22 12:18:26 +010078 /* Find the TLB entry */
79 for (i = 0;; i++) {
80 if (i >= PPC4XX_TLB_SIZE) {
81 printf ("Failed to program tlb entry\n");
82 return -1;
83 }
84 word0 = mftlb1(i);
85 if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
86 tlb = i;
87 break;
Sergei Poselenovb4489622007-07-05 08:17:37 +020088 }
89 }
Stefan Roeseeb2b4012007-08-14 14:39:44 +020090#endif
Sergei Poselenovb4489622007-07-05 08:17:37 +020091 ints = disable_interrupts ();
92
93 WATCHDOG_RESET ();
94 if (res == 0)
95 res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
96 WATCHDOG_RESET ();
97 if (res == 0)
98 res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
99 WATCHDOG_RESET ();
100 if (res == 0)
101 res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
102 WATCHDOG_RESET ();
103 if (res == 0)
104 res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
105 WATCHDOG_RESET ();
106 if (res == 0)
107 res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
108 WATCHDOG_RESET ();
109 if (res == 0)
110 res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
111
112 if (ints)
113 enable_interrupts ();
114
Stefan Roesea2685902007-10-31 20:45:53 +0100115#ifdef CONFIG_440
Stefan Roese06713772007-10-23 18:03:12 +0200116 remove_tlb((u32)virt, CACHE_POST_SIZE);
Stefan Roesea2685902007-10-31 20:45:53 +0100117#endif
Stefan Roese6fa397d2007-10-23 14:40:30 +0200118
Sergei Poselenovb4489622007-07-05 08:17:37 +0200119 return res;
120}
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */