blob: 109ca1fbd1076af119758351562f6e0eca8b8e64 [file] [log] [blame]
Sergei Poselenovb4489622007-07-05 08:17:37 +02001/*
2 * (C) Copyright 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Author: Igor Lisitsin <igor@emcraft.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27
28/* Cache test
29 *
30 * This test verifies the CPU data and instruction cache using
31 * several test scenarios.
32 */
33
34#ifdef CONFIG_POST
35
36#include <post.h>
37
38#if CONFIG_POST & CFG_POST_CACHE
39
40#include <asm/mmu.h>
41#include <watchdog.h>
42
43#define CACHE_POST_SIZE 1024
44
45void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
46
47int cache_post_test1 (int tlb, void *p, int size);
48int cache_post_test2 (int tlb, void *p, int size);
49int cache_post_test3 (int tlb, void *p, int size);
50int cache_post_test4 (int tlb, void *p, int size);
51int cache_post_test5 (int tlb, void *p, int size);
52int cache_post_test6 (int tlb, void *p, int size);
53
54static int tlb = -1; /* index to the victim TLB entry */
55
Stefan Roeseeb2b4012007-08-14 14:39:44 +020056#ifdef CONFIG_440
Sergei Poselenovb4489622007-07-05 08:17:37 +020057static unsigned char testarea[CACHE_POST_SIZE]
58__attribute__((__aligned__(CACHE_POST_SIZE)));
Stefan Roeseeb2b4012007-08-14 14:39:44 +020059#endif
Sergei Poselenovb4489622007-07-05 08:17:37 +020060
61int cache_post_test (int flags)
62{
63 void* virt = (void*)CFG_POST_CACHE_ADDR;
Stefan Roeseeb2b4012007-08-14 14:39:44 +020064 int ints;
65 int res = 0;
66
67 /*
68 * All 44x variants deal with cache management differently
69 * because they have the address translation always enabled.
70 * The 40x ppc's don't use address translation in U-Boot at all,
71 * so we have to distinguish here between 40x and 44x.
72 */
73#ifdef CONFIG_440
74 int word0, i;
Sergei Poselenovb4489622007-07-05 08:17:37 +020075
76 if (tlb < 0) {
77 /*
78 * Allocate a new TLB entry, since we are going to modify
79 * the write-through and caching inhibited storage attributes.
80 */
81 program_tlb((u32)testarea, (u32)virt,
82 CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
83
84 /* Find the TLB entry */
85 for (i = 0;; i++) {
86 if (i >= PPC4XX_TLB_SIZE) {
87 printf ("Failed to program tlb entry\n");
88 return -1;
89 }
90 word0 = mftlb1(i);
91 if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
92 tlb = i;
93 break;
94 }
95 }
96 }
Stefan Roeseeb2b4012007-08-14 14:39:44 +020097#endif
Sergei Poselenovb4489622007-07-05 08:17:37 +020098 ints = disable_interrupts ();
99
100 WATCHDOG_RESET ();
101 if (res == 0)
102 res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
103 WATCHDOG_RESET ();
104 if (res == 0)
105 res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
106 WATCHDOG_RESET ();
107 if (res == 0)
108 res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
109 WATCHDOG_RESET ();
110 if (res == 0)
111 res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
112 WATCHDOG_RESET ();
113 if (res == 0)
114 res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
115 WATCHDOG_RESET ();
116 if (res == 0)
117 res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
118
119 if (ints)
120 enable_interrupts ();
121
122 return res;
123}
124
125#endif /* CONFIG_POST & CFG_POST_CACHE */
126#endif /* CONFIG_POST */