Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Samsung Electronics |
| 3 | * |
| 4 | * Configuration settings for the SAMSUNG EXYNOS5420 SoC |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_EXYNOS5420_H |
| 10 | #define __CONFIG_EXYNOS5420_H |
| 11 | |
Simon Glass | 87033d4 | 2014-10-07 22:01:46 -0600 | [diff] [blame] | 12 | #define CONFIG_EXYNOS5420 |
Akshay Saraswat | 79043d8 | 2014-11-13 22:38:17 +0530 | [diff] [blame^] | 13 | /* A variant of Exynos5420 (Exynos5 Family) */ |
| 14 | #define CONFIG_EXYNOS5800 |
Simon Glass | 87033d4 | 2014-10-07 22:01:46 -0600 | [diff] [blame] | 15 | |
Simon Glass | f94de73 | 2014-10-07 22:01:48 -0600 | [diff] [blame] | 16 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 17 | #define CONFIG_SPI_FLASH |
| 18 | #define CONFIG_ENV_SPI_BASE 0x12D30000 |
| 19 | #define FLASH_SIZE (0x4 << 20) |
| 20 | #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) |
| 21 | #define CONFIG_SPI_BOOTING |
| 22 | |
Simon Glass | 87033d4 | 2014-10-07 22:01:46 -0600 | [diff] [blame] | 23 | #include <configs/exynos5-common.h> |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 24 | |
Simon Glass | f94de73 | 2014-10-07 22:01:48 -0600 | [diff] [blame] | 25 | #define CONFIG_ARCH_EARLY_INIT_R |
| 26 | |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 27 | #define MACH_TYPE_SMDK5420 8002 |
| 28 | #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 |
| 29 | |
| 30 | #define CONFIG_VAR_SIZE_SPL |
| 31 | |
| 32 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 33 | #define CONFIG_SYS_TEXT_BASE 0x23E00000 |
| 34 | #ifdef CONFIG_VAR_SIZE_SPL |
| 35 | #define CONFIG_SPL_TEXT_BASE 0x02024410 |
| 36 | #else |
| 37 | #define CONFIG_SPL_TEXT_BASE 0x02024400 |
| 38 | #endif |
| 39 | #define CONFIG_IRAM_TOP 0x02074000 |
| 40 | |
Akshay Saraswat | d2fe10f | 2014-06-18 17:54:00 +0530 | [diff] [blame] | 41 | #define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) |
| 42 | |
Akshay Saraswat | 79043d8 | 2014-11-13 22:38:17 +0530 | [diff] [blame^] | 43 | #define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ |
| 44 | "exynos5420-peach-pit exynos5420-smdk5420" |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 45 | |
| 46 | #define CONFIG_MAX_I2C_NUM 11 |
| 47 | |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 48 | #define CONFIG_BOARD_REV_GPIO_COUNT 2 |
| 49 | |
| 50 | #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" |
| 51 | |
Simon Glass | f94de73 | 2014-10-07 22:01:48 -0600 | [diff] [blame] | 52 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| 53 | |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 54 | /* |
| 55 | * Put the initial stack pointer 1KB below this to allow room for the |
| 56 | * SPL marker. This value is arbitrary, but gd_t is placed starting here. |
| 57 | */ |
| 58 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) |
| 59 | |
Michael Pratt | 0cf7e18 | 2014-06-18 17:54:02 +0530 | [diff] [blame] | 60 | /* DRAM Memory Banks */ |
| 61 | #define CONFIG_NR_DRAM_BANKS 7 |
| 62 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ |
| 63 | |
Simon Glass | f94de73 | 2014-10-07 22:01:48 -0600 | [diff] [blame] | 64 | /* Miscellaneous configurable options */ |
| 65 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" |
| 66 | |
Akshay Saraswat | 8e4ab1d | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 67 | #endif /* __CONFIG_EXYNOS5420_H */ |