blob: 33e5ea9ebdd0d836d4412af5971f558b790dc8bd [file] [log] [blame]
Simon Glass87f938c2012-02-27 10:52:49 +00001/*
Lucas Stach7ae18f32013-02-07 07:16:29 +00002 * Copyright (c) 2011 The Chromium OS Authors.
Jim Lin7e44d932013-06-21 19:05:47 +08003 * Copyright (c) 2009-2013 NVIDIA Corporation
Lucas Stach7ae18f32013-02-07 07:16:29 +00004 * Copyright (c) 2013 Lucas Stach
Simon Glass87f938c2012-02-27 10:52:49 +00005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Simon Glass87f938c2012-02-27 10:52:49 +00007 */
8
9#include <common.h>
Lucas Stach7ae18f32013-02-07 07:16:29 +000010#include <asm/errno.h>
11#include <asm/io.h>
12#include <asm-generic/gpio.h>
13#include <asm/arch/clock.h>
14#include <asm/arch-tegra/usb.h>
Jim Lin7e44d932013-06-21 19:05:47 +080015#include <asm/arch-tegra/clk_rst.h>
Simon Glass87f938c2012-02-27 10:52:49 +000016#include <usb.h>
Lucas Stach7ae18f32013-02-07 07:16:29 +000017#include <usb/ulpi.h>
18#include <libfdt.h>
19#include <fdtdec.h>
Simon Glass87f938c2012-02-27 10:52:49 +000020
21#include "ehci.h"
Simon Glass87f938c2012-02-27 10:52:49 +000022
Jim Lin7e44d932013-06-21 19:05:47 +080023#define USB1_ADDR_MASK 0xFFFF0000
24
25#define HOSTPC1_DEVLC 0x84
26#define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3)
27
Lucas Stach7ae18f32013-02-07 07:16:29 +000028#ifdef CONFIG_USB_ULPI
29 #ifndef CONFIG_USB_ULPI_VIEWPORT
30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
31 define CONFIG_USB_ULPI_VIEWPORT"
32 #endif
33#endif
34
35enum {
36 USB_PORTS_MAX = 3, /* Maximum ports we allow */
37};
38
39/* Parameters we need for USB */
40enum {
41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
42 PARAM_DIVM, /* PLL INPUT DIVIDER */
43 PARAM_DIVP, /* POST DIVIDER (2^N) */
44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
52
53 PARAM_COUNT
54};
55
56/* Possible port types (dual role mode) */
57enum dr_mode {
58 DR_MODE_NONE = 0,
59 DR_MODE_HOST, /* supports host operation */
60 DR_MODE_DEVICE, /* supports device operation */
61 DR_MODE_OTG, /* supports both */
62};
63
64/* Information about a USB port */
65struct fdt_usb {
66 struct usb_ctlr *reg; /* address of registers in physical memory */
67 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
68 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
69 unsigned enabled:1; /* 1 to enable, 0 to disable */
70 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
71 unsigned initialized:1; /* has this port already been initialized? */
Stephen Warrena4539a22014-04-30 15:09:57 -060072 enum usb_init_type init_type;
Lucas Stach7ae18f32013-02-07 07:16:29 +000073 enum dr_mode dr_mode; /* dual role mode */
74 enum periph_id periph_id;/* peripheral id */
75 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
76 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
77};
78
79static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
80static unsigned port_count; /* Number of available ports */
Jim Lin7e44d932013-06-21 19:05:47 +080081/* Port that needs to clear CSC after Port Reset */
82static u32 port_addr_clear_csc;
Lucas Stach7ae18f32013-02-07 07:16:29 +000083
84/*
85 * This table has USB timing parameters for each Oscillator frequency we
86 * support. There are four sets of values:
87 *
88 * 1. PLLU configuration information (reference clock is osc/clk_m and
89 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
90 *
91 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
92 * ----------------------------------------------------------------------
93 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
94 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
95 * Filter frequency (MHz) 1 4.8 6 2
96 * CPCON 1100b 0011b 1100b 1100b
97 * LFCON0 0 0 0 0
98 *
99 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
100 *
101 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
102 * ---------------------------------------------------------------------------
103 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
104 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
105 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
106 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
107 *
108 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
109 * SessEnd. Each of these signals have their own debouncer and for each of
110 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
111 * BIAS_DEBOUNCE_B).
112 *
113 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
114 * 0xffff -> No debouncing at all
115 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
116 *
117 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
118 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
119 *
120 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
121 * values, so we can keep those to default.
122 *
123 * 4. The 20 microsecond delay after bias cell operation.
124 */
Jim Lin7e44d932013-06-21 19:05:47 +0800125static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
Lucas Stach7ae18f32013-02-07 07:16:29 +0000126 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
127 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
128 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
129 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
130 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
131};
132
Jim Lin7e44d932013-06-21 19:05:47 +0800133static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
134 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
135 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
136 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
137 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
138 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
139};
140
141static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
142 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
143 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
144 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
145 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
146 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
147};
148
Lucas Stach7ae18f32013-02-07 07:16:29 +0000149/* UTMIP Idle Wait Delay */
150static const u8 utmip_idle_wait_delay = 17;
151
152/* UTMIP Elastic limit */
153static const u8 utmip_elastic_limit = 16;
154
155/* UTMIP High Speed Sync Start Delay */
156static const u8 utmip_hs_sync_start_delay = 9;
Simon Glass87f938c2012-02-27 10:52:49 +0000157
Jim Lin7e44d932013-06-21 19:05:47 +0800158struct fdt_usb_controller {
159 int compat;
160 /* flag to determine whether controller supports hostpc register */
161 u32 has_hostpc:1;
162 const unsigned *pll_parameter;
163};
164
165static struct fdt_usb_controller fdt_usb_controllers[] = {
166 {
167 .compat = COMPAT_NVIDIA_TEGRA20_USB,
168 .has_hostpc = 0,
169 .pll_parameter = (const unsigned *)T20_usb_pll,
170 },
171 {
172 .compat = COMPAT_NVIDIA_TEGRA30_USB,
173 .has_hostpc = 1,
174 .pll_parameter = (const unsigned *)T30_usb_pll,
175 },
176 {
177 .compat = COMPAT_NVIDIA_TEGRA114_USB,
178 .has_hostpc = 1,
179 .pll_parameter = (const unsigned *)T114_usb_pll,
180 },
181};
182
183static struct fdt_usb_controller *controller;
184
Jim Lin8b3f7bf2012-06-24 20:40:57 +0000185/*
186 * A known hardware issue where Connect Status Change bit of PORTSC register
187 * of USB1 controller will be set after Port Reset.
188 * We have to clear it in order for later device enumeration to proceed.
189 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
190 * in "ehci-hcd.c".
191 */
192void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
193{
194 mdelay(50);
Jim Lin7e44d932013-06-21 19:05:47 +0800195 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
196 if (controller->has_hostpc)
197 *reg |= EHCI_PS_PE;
198
199 if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc)
Jim Lin8b3f7bf2012-06-24 20:40:57 +0000200 return;
201 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
202 if (ehci_readl(status_reg) & EHCI_PS_CSC)
203 *reg |= EHCI_PS_CSC;
204}
Simon Glass87f938c2012-02-27 10:52:49 +0000205
Jim Lin7e44d932013-06-21 19:05:47 +0800206/*
207 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode
208 * in "ehci-hcd.c".
209 */
210void ehci_set_usbmode(int index)
211{
212 struct fdt_usb *config;
213 struct usb_ctlr *usbctlr;
214 uint32_t tmp;
215
216 config = &port[index];
217 usbctlr = config->reg;
218
219 tmp = ehci_readl(&usbctlr->usb_mode);
220 tmp |= USBMODE_CM_HC;
221 ehci_writel(&usbctlr->usb_mode, tmp);
222}
223
224/*
225 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed
226 * in "ehci-hcd.c".
227 */
228int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
229{
230 uint32_t tmp;
231 uint32_t *reg_ptr;
232
233 if (controller->has_hostpc) {
234 reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC);
235 tmp = ehci_readl(reg_ptr);
236 return HOSTPC1_PSPD(tmp);
237 } else
238 return PORTSC_PSPD(reg);
239}
240
Stephen Warrena4539a22014-04-30 15:09:57 -0600241/* Set up VBUS for host/device mode */
242static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000243{
244 /*
Stephen Warrena4539a22014-04-30 15:09:57 -0600245 * If we are an OTG port initializing in host mode,
246 * check if remote host is driving VBus and bail out in this case.
Lucas Stach7ae18f32013-02-07 07:16:29 +0000247 */
Stephen Warrena4539a22014-04-30 15:09:57 -0600248 if (init == USB_INIT_HOST &&
249 config->dr_mode == DR_MODE_OTG &&
250 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
251 printf("tegrausb: VBUS input active; not enabling as host\n");
Lucas Stach7ae18f32013-02-07 07:16:29 +0000252 return;
Stephen Warrena4539a22014-04-30 15:09:57 -0600253 }
Lucas Stach7ae18f32013-02-07 07:16:29 +0000254
Lucas Stach7ae18f32013-02-07 07:16:29 +0000255 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
Stephen Warrena4539a22014-04-30 15:09:57 -0600256 int vbus_value;
257
Lucas Stach7ae18f32013-02-07 07:16:29 +0000258 fdtdec_setup_gpio(&config->vbus_gpio);
Stephen Warrena4539a22014-04-30 15:09:57 -0600259
260 vbus_value = (init == USB_INIT_HOST) ^
261 !!(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW);
262 gpio_direction_output(config->vbus_gpio.gpio, vbus_value);
263
264 debug("set_up_vbus: GPIO %d %d\n", config->vbus_gpio.gpio,
265 vbus_value);
Lucas Stach7ae18f32013-02-07 07:16:29 +0000266 }
267}
268
269void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
270{
271 /* Reset the USB controller with 2us delay */
272 reset_periph(config->periph_id, 2);
273
274 /*
275 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
276 * base address
277 */
278 if (config->has_legacy_mode)
279 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
280
281 /* Put UTMIP1/3 in reset */
282 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
283
284 /* Enable the UTMIP PHY */
285 if (config->utmi)
286 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
287}
288
Jim Lin7e44d932013-06-21 19:05:47 +0800289static const unsigned *get_pll_timing(void)
290{
291 const unsigned *timing;
292
293 timing = controller->pll_parameter +
294 clock_get_osc_freq() * PARAM_COUNT;
295
296 return timing;
297}
298
Stephen Warren2d341512014-04-30 15:09:56 -0600299/* select the PHY to use with a USB controller */
Stephen Warrena4539a22014-04-30 15:09:57 -0600300static void init_phy_mux(struct fdt_usb *config, uint pts,
301 enum usb_init_type init)
Stephen Warren2d341512014-04-30 15:09:56 -0600302{
303 struct usb_ctlr *usbctlr = config->reg;
304
305#if defined(CONFIG_TEGRA20)
306 if (config->periph_id == PERIPH_ID_USBD) {
307 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
308 PTS_UTMI << PTS1_SHIFT);
309 clrbits_le32(&usbctlr->port_sc1, STS1);
310 } else {
311 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
312 PTS_UTMI << PTS_SHIFT);
313 clrbits_le32(&usbctlr->port_sc1, STS);
314 }
315#else
Stephen Warrena4539a22014-04-30 15:09:57 -0600316 /* Set to Host mode (if applicable) after Controller Reset was done */
Stephen Warren2d341512014-04-30 15:09:56 -0600317 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
Stephen Warrena4539a22014-04-30 15:09:57 -0600318 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
319 /*
320 * Select PHY interface after setting host mode.
321 * For device mode, the ordering requirement is not an issue, since
322 * only the first USB controller supports device mode, and that USB
323 * controller can only talk to a UTMI PHY, so the PHY selection is
324 * already made at reset time, so this write is a no-op.
325 */
Stephen Warren2d341512014-04-30 15:09:56 -0600326 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
327 pts << PTS_SHIFT);
328 clrbits_le32(&usbctlr->hostpc1_devlc, STS);
329#endif
330}
331
Lucas Stach7ae18f32013-02-07 07:16:29 +0000332/* set up the UTMI USB controller with the parameters provided */
Stephen Warrena4539a22014-04-30 15:09:57 -0600333static int init_utmi_usb_controller(struct fdt_usb *config,
334 enum usb_init_type init)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000335{
Stephen Warrena4539a22014-04-30 15:09:57 -0600336 u32 b_sess_valid_mask, val;
Lucas Stach7ae18f32013-02-07 07:16:29 +0000337 int loop_count;
338 const unsigned *timing;
339 struct usb_ctlr *usbctlr = config->reg;
Jim Lin7e44d932013-06-21 19:05:47 +0800340 struct clk_rst_ctlr *clkrst;
341 struct usb_ctlr *usb1ctlr;
Lucas Stach7ae18f32013-02-07 07:16:29 +0000342
343 clock_enable(config->periph_id);
344
345 /* Reset the usb controller */
346 usbf_reset_controller(config, usbctlr);
347
348 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
349 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
350
351 /* Follow the crystal clock disable by >100ns delay */
352 udelay(1);
353
Stephen Warrena4539a22014-04-30 15:09:57 -0600354 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
355 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
356 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
357
Lucas Stach7ae18f32013-02-07 07:16:29 +0000358 /*
359 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
360 * mux must be switched to actually use a_sess_vld threshold.
361 */
Jim Lin7e44d932013-06-21 19:05:47 +0800362 if (config->dr_mode == DR_MODE_OTG &&
363 fdt_gpio_isvalid(&config->vbus_gpio))
Lucas Stach7ae18f32013-02-07 07:16:29 +0000364 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
365 VBUS_SENSE_CTL_MASK,
366 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
Lucas Stach7ae18f32013-02-07 07:16:29 +0000367
368 /*
369 * PLL Delay CONFIGURATION settings. The following parameters control
370 * the bring up of the plls.
371 */
Jim Lin7e44d932013-06-21 19:05:47 +0800372 timing = get_pll_timing();
Lucas Stach7ae18f32013-02-07 07:16:29 +0000373
Jim Lin7e44d932013-06-21 19:05:47 +0800374 if (!controller->has_hostpc) {
375 val = readl(&usbctlr->utmip_misc_cfg1);
376 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
377 timing[PARAM_STABLE_COUNT] <<
378 UTMIP_PLLU_STABLE_COUNT_SHIFT);
379 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
380 timing[PARAM_ACTIVE_DELAY_COUNT] <<
381 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
382 writel(val, &usbctlr->utmip_misc_cfg1);
Lucas Stach7ae18f32013-02-07 07:16:29 +0000383
Jim Lin7e44d932013-06-21 19:05:47 +0800384 /* Set PLL enable delay count and crystal frequency count */
385 val = readl(&usbctlr->utmip_pll_cfg1);
386 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
387 timing[PARAM_ENABLE_DELAY_COUNT] <<
388 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
389 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
390 timing[PARAM_XTAL_FREQ_COUNT] <<
391 UTMIP_XTAL_FREQ_COUNT_SHIFT);
392 writel(val, &usbctlr->utmip_pll_cfg1);
393 } else {
394 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
395
396 val = readl(&clkrst->crc_utmip_pll_cfg2);
397 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
398 timing[PARAM_STABLE_COUNT] <<
399 UTMIP_PLLU_STABLE_COUNT_SHIFT);
400 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
401 timing[PARAM_ACTIVE_DELAY_COUNT] <<
402 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
403 writel(val, &clkrst->crc_utmip_pll_cfg2);
404
405 /* Set PLL enable delay count and crystal frequency count */
406 val = readl(&clkrst->crc_utmip_pll_cfg1);
407 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
408 timing[PARAM_ENABLE_DELAY_COUNT] <<
409 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
410 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
411 timing[PARAM_XTAL_FREQ_COUNT] <<
412 UTMIP_XTAL_FREQ_COUNT_SHIFT);
413 writel(val, &clkrst->crc_utmip_pll_cfg1);
414
415 /* Disable Power Down state for PLL */
416 clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
417 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
418 PLL_ACTIVE_POWERDOWN);
419
420 /* Recommended PHY settings for EYE diagram */
421 val = readl(&usbctlr->utmip_xcvr_cfg0);
422 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
423 0x4 << UTMIP_XCVR_SETUP_SHIFT);
424 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
425 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
426 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
427 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
428 writel(val, &usbctlr->utmip_xcvr_cfg0);
429 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
430 UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
431 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
432
433 /* Some registers can be controlled from USB1 only. */
434 if (config->periph_id != PERIPH_ID_USBD) {
435 clock_enable(PERIPH_ID_USBD);
436 /* Disable Reset if in Reset state */
437 reset_set_enable(PERIPH_ID_USBD, 0);
438 }
439 usb1ctlr = (struct usb_ctlr *)
440 ((u32)config->reg & USB1_ADDR_MASK);
441 val = readl(&usb1ctlr->utmip_bias_cfg0);
442 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
443 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
444 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
445 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
446 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
447 writel(val, &usb1ctlr->utmip_bias_cfg0);
448
449 /* Miscellaneous setting mentioned in Programming Guide */
450 clrbits_le32(&usbctlr->utmip_misc_cfg0,
451 UTMIP_SUSPEND_EXIT_ON_EDGE);
452 }
Lucas Stach7ae18f32013-02-07 07:16:29 +0000453
454 /* Setting the tracking length time */
455 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
456 UTMIP_BIAS_PDTRK_COUNT_MASK,
457 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
458
459 /* Program debounce time for VBUS to become valid */
460 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
461 UTMIP_DEBOUNCE_CFG0_MASK,
462 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
463
464 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
465
466 /* Disable battery charge enabling bit */
467 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
468
469 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
470 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
471
472 /*
473 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
474 * Setting these fields, together with default values of the
475 * other fields, results in programming the registers below as
476 * follows:
477 * UTMIP_HSRX_CFG0 = 0x9168c000
478 * UTMIP_HSRX_CFG1 = 0x13
479 */
480
481 /* Set PLL enable delay count and Crystal frequency count */
482 val = readl(&usbctlr->utmip_hsrx_cfg0);
483 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
484 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
485 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
486 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
487 writel(val, &usbctlr->utmip_hsrx_cfg0);
488
489 /* Configure the UTMIP_HS_SYNC_START_DLY */
490 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
491 UTMIP_HS_SYNC_START_DLY_MASK,
492 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
493
494 /* Preceed the crystal clock disable by >100ns delay. */
495 udelay(1);
496
497 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
498 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
499
Jim Lin7e44d932013-06-21 19:05:47 +0800500 if (controller->has_hostpc) {
501 if (config->periph_id == PERIPH_ID_USBD)
502 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
503 UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
Stefan Agnerb03f4b32014-03-02 19:46:48 +0100504 if (config->periph_id == PERIPH_ID_USB2)
505 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
506 UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
Jim Lin7e44d932013-06-21 19:05:47 +0800507 if (config->periph_id == PERIPH_ID_USB3)
508 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
509 UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
510 }
Lucas Stach7ae18f32013-02-07 07:16:29 +0000511 /* Finished the per-controller init. */
512
513 /* De-assert UTMIP_RESET to bring out of reset. */
514 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
515
516 /* Wait for the phy clock to become valid in 100 ms */
517 for (loop_count = 100000; loop_count != 0; loop_count--) {
518 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
519 break;
520 udelay(1);
521 }
522 if (!loop_count)
523 return -1;
524
525 /* Disable ICUSB FS/LS transceiver */
526 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
527
528 /* Select UTMI parallel interface */
Stephen Warrena4539a22014-04-30 15:09:57 -0600529 init_phy_mux(config, PTS_UTMI, init);
Lucas Stach7ae18f32013-02-07 07:16:29 +0000530
531 /* Deassert power down state */
532 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
533 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
534 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
535 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
536
Jim Lin7e44d932013-06-21 19:05:47 +0800537 if (controller->has_hostpc) {
538 /*
539 * BIAS Pad Power Down is common among all 3 USB
540 * controllers and can be controlled from USB1 only.
541 */
542 usb1ctlr = (struct usb_ctlr *)
543 ((u32)config->reg & USB1_ADDR_MASK);
544 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
545 udelay(25);
546 clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
547 UTMIP_FORCE_PDTRK_POWERDOWN);
548 }
Lucas Stach7ae18f32013-02-07 07:16:29 +0000549 return 0;
550}
551
552#ifdef CONFIG_USB_ULPI
553/* if board file does not set a ULPI reference frequency we default to 24MHz */
554#ifndef CONFIG_ULPI_REF_CLK
555#define CONFIG_ULPI_REF_CLK 24000000
556#endif
557
558/* set up the ULPI USB controller with the parameters provided */
Stephen Warrena4539a22014-04-30 15:09:57 -0600559static int init_ulpi_usb_controller(struct fdt_usb *config,
560 enum usb_init_type init)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000561{
562 u32 val;
563 int loop_count;
564 struct ulpi_viewport ulpi_vp;
565 struct usb_ctlr *usbctlr = config->reg;
566
567 /* set up ULPI reference clock on pllp_out4 */
568 clock_enable(PERIPH_ID_DEV2_OUT);
569 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
570
571 /* reset ULPI phy */
572 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
573 fdtdec_setup_gpio(&config->phy_reset_gpio);
574 gpio_direction_output(config->phy_reset_gpio.gpio, 0);
575 mdelay(5);
576 gpio_set_value(config->phy_reset_gpio.gpio, 1);
577 }
578
579 /* Reset the usb controller */
580 clock_enable(config->periph_id);
581 usbf_reset_controller(config, usbctlr);
582
583 /* enable pinmux bypass */
584 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
585 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
586
587 /* Select ULPI parallel interface */
Stephen Warrena4539a22014-04-30 15:09:57 -0600588 init_phy_mux(config, PTS_ULPI, init);
Lucas Stach7ae18f32013-02-07 07:16:29 +0000589
590 /* enable ULPI transceiver */
591 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
592
593 /* configure ULPI transceiver timings */
594 val = 0;
595 writel(val, &usbctlr->ulpi_timing_ctrl_1);
596
597 val |= ULPI_DATA_TRIMMER_SEL(4);
598 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
599 val |= ULPI_DIR_TRIMMER_SEL(4);
600 writel(val, &usbctlr->ulpi_timing_ctrl_1);
601 udelay(10);
602
603 val |= ULPI_DATA_TRIMMER_LOAD;
604 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
605 val |= ULPI_DIR_TRIMMER_LOAD;
606 writel(val, &usbctlr->ulpi_timing_ctrl_1);
607
608 /* set up phy for host operation with external vbus supply */
609 ulpi_vp.port_num = 0;
610 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
611
612 if (ulpi_init(&ulpi_vp)) {
613 printf("Tegra ULPI viewport init failed\n");
614 return -1;
615 }
616
617 ulpi_set_vbus(&ulpi_vp, 1, 1);
618 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
619
620 /* enable wakeup events */
621 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
622
623 /* Enable and wait for the phy clock to become valid in 100 ms */
624 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
625 for (loop_count = 100000; loop_count != 0; loop_count--) {
626 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
627 break;
628 udelay(1);
629 }
630 if (!loop_count)
631 return -1;
632 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
633
634 return 0;
635}
636#else
Stephen Warrena4539a22014-04-30 15:09:57 -0600637static int init_ulpi_usb_controller(struct fdt_usb *config,
638 enum usb_init_type init)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000639{
640 printf("No code to set up ULPI controller, please enable"
641 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
642 return -1;
643}
644#endif
645
646static void config_clock(const u32 timing[])
647{
648 clock_start_pll(CLOCK_ID_USB,
649 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
650 timing[PARAM_CPCON], timing[PARAM_LFCON]);
651}
652
Jim Lin7e44d932013-06-21 19:05:47 +0800653static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000654{
655 const char *phy, *mode;
656
657 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
658 mode = fdt_getprop(blob, node, "dr_mode", NULL);
659 if (mode) {
660 if (0 == strcmp(mode, "host"))
661 config->dr_mode = DR_MODE_HOST;
662 else if (0 == strcmp(mode, "peripheral"))
663 config->dr_mode = DR_MODE_DEVICE;
664 else if (0 == strcmp(mode, "otg"))
665 config->dr_mode = DR_MODE_OTG;
666 else {
667 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
668 mode);
669 return -FDT_ERR_NOTFOUND;
670 }
671 } else {
672 config->dr_mode = DR_MODE_HOST;
673 }
674
675 phy = fdt_getprop(blob, node, "phy_type", NULL);
676 config->utmi = phy && 0 == strcmp("utmi", phy);
677 config->ulpi = phy && 0 == strcmp("ulpi", phy);
678 config->enabled = fdtdec_get_is_enabled(blob, node);
679 config->has_legacy_mode = fdtdec_get_bool(blob, node,
680 "nvidia,has-legacy-mode");
Jim Lin7e44d932013-06-21 19:05:47 +0800681 if (config->has_legacy_mode)
682 port_addr_clear_csc = (u32) config->reg;
Lucas Stach7ae18f32013-02-07 07:16:29 +0000683 config->periph_id = clock_decode_periph_id(blob, node);
684 if (config->periph_id == PERIPH_ID_NONE) {
685 debug("%s: Missing/invalid peripheral ID\n", __func__);
686 return -FDT_ERR_NOTFOUND;
687 }
688 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
689 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
690 &config->phy_reset_gpio);
691 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
692 "vbus=%d, phy_reset=%d, dr_mode=%d\n",
693 config->enabled, config->has_legacy_mode, config->utmi,
694 config->ulpi, config->periph_id, config->vbus_gpio.gpio,
695 config->phy_reset_gpio.gpio, config->dr_mode);
696
697 return 0;
698}
699
Jim Lin7e44d932013-06-21 19:05:47 +0800700/*
701 * process_usb_nodes() - Process a list of USB nodes, adding them to our list
702 * of USB ports.
703 * @blob: fdt blob
704 * @node_list: list of nodes to process (any <=0 are ignored)
705 * @count: number of nodes to process
706 *
707 * Return: 0 - ok, -1 - error
708 */
709static int process_usb_nodes(const void *blob, int node_list[], int count)
Lucas Stach7ae18f32013-02-07 07:16:29 +0000710{
711 struct fdt_usb config;
Jim Lin7e44d932013-06-21 19:05:47 +0800712 int node, i;
713 int clk_done = 0;
Lucas Stach7ae18f32013-02-07 07:16:29 +0000714
Jim Lin7e44d932013-06-21 19:05:47 +0800715 port_count = 0;
Lucas Stach7ae18f32013-02-07 07:16:29 +0000716 for (i = 0; i < count; i++) {
717 if (port_count == USB_PORTS_MAX) {
718 printf("tegrausb: Cannot register more than %d ports\n",
719 USB_PORTS_MAX);
720 return -1;
721 }
722
723 debug("USB %d: ", i);
724 node = node_list[i];
725 if (!node)
726 continue;
727 if (fdt_decode_usb(blob, node, &config)) {
728 debug("Cannot decode USB node %s\n",
729 fdt_get_name(blob, node, NULL));
730 return -1;
731 }
Jim Lin7e44d932013-06-21 19:05:47 +0800732 if (!clk_done) {
733 config_clock(get_pll_timing());
734 clk_done = 1;
735 }
Lucas Stach7ae18f32013-02-07 07:16:29 +0000736 config.initialized = 0;
737
738 /* add new USB port to the list of available ports */
739 port[port_count++] = config;
740 }
741
742 return 0;
743}
744
Mateusz Zalega16297cf2013-10-04 19:22:26 +0200745int usb_process_devicetree(const void *blob)
Jim Lin7e44d932013-06-21 19:05:47 +0800746{
747 int node_list[USB_PORTS_MAX];
748 int count, err = 0;
749 int i;
750
751 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
752 controller = &fdt_usb_controllers[i];
753
754 count = fdtdec_find_aliases_for_id(blob, "usb",
755 controller->compat, node_list, USB_PORTS_MAX);
756 if (count) {
757 err = process_usb_nodes(blob, node_list, count);
758 if (err)
759 printf("%s: Error processing USB node!\n",
760 __func__);
761 return err;
762 }
763 }
764 if (i == ARRAY_SIZE(fdt_usb_controllers))
765 controller = NULL;
766
767 return err;
768}
769
Lucas Stachd7a55e12013-02-07 07:16:30 +0000770/**
771 * Start up the given port number (ports are numbered from 0 on each board).
772 * This returns values for the appropriate hccr and hcor addresses to use for
773 * USB EHCI operations.
774 *
775 * @param index port number to start
776 * @param hccr returns start address of EHCI HCCR registers
777 * @param hcor returns start address of EHCI HCOR registers
778 * @return 0 if ok, -1 on error (generally invalid port number)
Simon Glass87f938c2012-02-27 10:52:49 +0000779 */
Troy Kisky127efc42013-10-10 15:27:57 -0700780int ehci_hcd_init(int index, enum usb_init_type init,
781 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Simon Glass87f938c2012-02-27 10:52:49 +0000782{
Lucas Stachd7a55e12013-02-07 07:16:30 +0000783 struct fdt_usb *config;
784 struct usb_ctlr *usbctlr;
Simon Glass87f938c2012-02-27 10:52:49 +0000785
Lucas Stachd7a55e12013-02-07 07:16:30 +0000786 if (index >= port_count)
Simon Glass87f938c2012-02-27 10:52:49 +0000787 return -1;
788
Lucas Stachd7a55e12013-02-07 07:16:30 +0000789 config = &port[index];
Simon Glass87f938c2012-02-27 10:52:49 +0000790
Stephen Warrena4539a22014-04-30 15:09:57 -0600791 switch (init) {
792 case USB_INIT_HOST:
793 switch (config->dr_mode) {
794 case DR_MODE_HOST:
795 case DR_MODE_OTG:
796 break;
797 default:
798 printf("tegrausb: Invalid dr_mode %d for host mode\n",
799 config->dr_mode);
800 return -1;
801 }
802 break;
803 case USB_INIT_DEVICE:
804 if (config->periph_id != PERIPH_ID_USBD) {
805 printf("tegrausb: Device mode only supported on first USB controller\n");
806 return -1;
807 }
808 if (!config->utmi) {
809 printf("tegrausb: Device mode only supported with UTMI PHY\n");
810 return -1;
811 }
812 switch (config->dr_mode) {
813 case DR_MODE_DEVICE:
814 case DR_MODE_OTG:
815 break;
816 default:
817 printf("tegrausb: Invalid dr_mode %d for device mode\n",
818 config->dr_mode);
819 return -1;
820 }
821 break;
822 default:
823 printf("tegrausb: Unknown USB_INIT_* %d\n", init);
824 return -1;
825 }
826
Lucas Stachd7a55e12013-02-07 07:16:30 +0000827 /* skip init, if the port is already initialized */
Stephen Warrena4539a22014-04-30 15:09:57 -0600828 if (config->initialized && config->init_type == init)
Lucas Stachd7a55e12013-02-07 07:16:30 +0000829 goto success;
830
Stephen Warrena4539a22014-04-30 15:09:57 -0600831 if (config->utmi && init_utmi_usb_controller(config, init)) {
Lucas Stachd7a55e12013-02-07 07:16:30 +0000832 printf("tegrausb: Cannot init port %d\n", index);
833 return -1;
834 }
835
Stephen Warrena4539a22014-04-30 15:09:57 -0600836 if (config->ulpi && init_ulpi_usb_controller(config, init)) {
Lucas Stachd7a55e12013-02-07 07:16:30 +0000837 printf("tegrausb: Cannot init port %d\n", index);
838 return -1;
839 }
840
Stephen Warrena4539a22014-04-30 15:09:57 -0600841 set_up_vbus(config, init);
Lucas Stachd7a55e12013-02-07 07:16:30 +0000842
843 config->initialized = 1;
Stephen Warrena4539a22014-04-30 15:09:57 -0600844 config->init_type = init;
Lucas Stachd7a55e12013-02-07 07:16:30 +0000845
846success:
847 usbctlr = config->reg;
848 *hccr = (struct ehci_hccr *)&usbctlr->cap_length;
849 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
Jim Lin7e44d932013-06-21 19:05:47 +0800850
Simon Glass87f938c2012-02-27 10:52:49 +0000851 return 0;
852}
853
854/*
Lucas Stachd7a55e12013-02-07 07:16:30 +0000855 * Bring down the specified USB controller
Simon Glass87f938c2012-02-27 10:52:49 +0000856 */
Lucas Stach676ae062012-09-26 00:14:35 +0200857int ehci_hcd_stop(int index)
Simon Glass87f938c2012-02-27 10:52:49 +0000858{
Lucas Stachd7a55e12013-02-07 07:16:30 +0000859 struct usb_ctlr *usbctlr;
860
861 usbctlr = port[index].reg;
862
863 /* Stop controller */
864 writel(0, &usbctlr->usb_cmd);
865 udelay(1000);
866
867 /* Initiate controller reset */
868 writel(2, &usbctlr->usb_cmd);
869 udelay(1000);
870
871 port[index].initialized = 0;
872
873 return 0;
Simon Glass87f938c2012-02-27 10:52:49 +0000874}