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wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the LUBBOCK board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk71f95112003-06-15 22:40:42 +000021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkda27dcf2002-09-10 19:19:06 +000022 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkda27dcf2002-09-10 19:19:06 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
wdenk71f95112003-06-15 22:40:42 +000037#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
39#define CONFIG_LCD 1
wdenk63cfcbb2004-10-09 22:32:26 +000040#ifdef CONFIG_LCD
41#define CONFIG_SHARP_LM8V31
42#endif
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +010043#define CONFIG_MMC
Helmut Raiger9660e442011-10-20 04:19:47 +000044#define CONFIG_BOARD_LATE_INIT
Jean-Christophe PLAGNIOL-VILLARD10cdb8d2007-10-19 00:24:59 +020045#define CONFIG_DOS_PARTITION
Marek Vasut3c43ca22010-10-20 20:55:44 +020046#define CONFIG_SYS_TEXT_BASE 0x0
wdenk71f95112003-06-15 22:40:42 +000047#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenkda27dcf2002-09-10 19:19:06 +000048
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020049/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000050#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020051
wdenkda27dcf2002-09-10 19:19:06 +000052/*
53 * Size of malloc() pool
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkda27dcf2002-09-10 19:19:06 +000056
57/*
58 * Hardware drivers
59 */
Nishanth Menonac6b3622009-10-16 00:06:37 -050060#define CONFIG_LAN91C96
wdenk45219c42003-05-12 21:50:16 +000061#define CONFIG_LAN91C96_BASE 0x0C000000
wdenkda27dcf2002-09-10 19:19:06 +000062
63/*
64 * select serial console configuration
65 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020066#define CONFIG_PXA_SERIAL
wdenk71f95112003-06-15 22:40:42 +000067#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
wdenkda27dcf2002-09-10 19:19:06 +000068
69/* allow to overwrite serial and ethaddr */
70#define CONFIG_ENV_OVERWRITE
71
wdenk71f95112003-06-15 22:40:42 +000072#define CONFIG_BAUDRATE 115200
wdenkda27dcf2002-09-10 19:19:06 +000073
wdenkda27dcf2002-09-10 19:19:06 +000074
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050075/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050076 * BOOTP options
77 */
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82
83
84/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050085 * Command line configuration.
86 */
87#include <config_cmd_default.h>
88
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050089#define CONFIG_CMD_FAT
90
wdenkda27dcf2002-09-10 19:19:06 +000091
wdenk71f95112003-06-15 22:40:42 +000092#define CONFIG_BOOTDELAY 3
93#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
94#define CONFIG_NETMASK 255.255.0.0
95#define CONFIG_IPADDR 192.168.0.21
96#define CONFIG_SERVERIP 192.168.0.250
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +020097#define CONFIG_BOOTCOMMAND "bootm 80000"
wdenk71f95112003-06-15 22:40:42 +000098#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
99#define CONFIG_CMDLINE_TAG
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200100#define CONFIG_TIMESTAMP
wdenkda27dcf2002-09-10 19:19:06 +0000101
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500102#if defined(CONFIG_CMD_KGDB)
wdenk71f95112003-06-15 22:40:42 +0000103#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
104#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
wdenkda27dcf2002-09-10 19:19:06 +0000105#endif
106
107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_HUSH_PARSER 1
111#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk71f95112003-06-15 22:40:42 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
114#ifdef CONFIG_SYS_HUSH_PARSER
115#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000116#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000118#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
123#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkda27dcf2002-09-10 19:19:06 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
126#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkda27dcf2002-09-10 19:19:06 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
wdenkda27dcf2002-09-10 19:19:06 +0000129
Micha Kalfon94a33122009-02-11 19:50:11 +0200130#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
wdenkda27dcf2002-09-10 19:19:06 +0000132
wdenk71f95112003-06-15 22:40:42 +0000133 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk71f95112003-06-15 22:40:42 +0000135
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100136#ifdef CONFIG_MMC
137#define CONFIG_PXA_MMC
138#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100140#endif
wdenkda27dcf2002-09-10 19:19:06 +0000141
142/*
143 * Stack sizes
144 *
145 * The stack sizes are set up in start.S using the settings below
146 */
wdenk71f95112003-06-15 22:40:42 +0000147#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenkda27dcf2002-09-10 19:19:06 +0000148#ifdef CONFIG_USE_IRQ
wdenk71f95112003-06-15 22:40:42 +0000149#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
150#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenkda27dcf2002-09-10 19:19:06 +0000151#endif
152
153/*
154 * Physical Memory Map
155 */
wdenk71f95112003-06-15 22:40:42 +0000156#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
157#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
158#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
159#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
160#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
161#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
162#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
163#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
164#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
wdenkda27dcf2002-09-10 19:19:06 +0000165
wdenk71f95112003-06-15 22:40:42 +0000166#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
167#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
168#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
169#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
170#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkda27dcf2002-09-10 19:19:06 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_DRAM_BASE 0xa0000000
173#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkda27dcf2002-09-10 19:19:06 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkda27dcf2002-09-10 19:19:06 +0000176
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200177#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200178#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200179
wdenkda27dcf2002-09-10 19:19:06 +0000180#define FPGA_REGS_BASE_PHYSICAL 0x08000000
181
182/*
183 * GPIO settings
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_GPSR0_VAL 0x00008000
186#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
187#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
188#define CONFIG_SYS_GPCR0_VAL 0x00000000
189#define CONFIG_SYS_GPCR1_VAL 0x00000000
190#define CONFIG_SYS_GPCR2_VAL 0x00000000
191#define CONFIG_SYS_GPDR0_VAL 0x0060A800
192#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
193#define CONFIG_SYS_GPDR2_VAL 0x0001C000
194#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
195#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
196#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
197#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
198#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
199#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkda27dcf2002-09-10 19:19:06 +0000200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_PSSR_VAL 0x20
wdenkda27dcf2002-09-10 19:19:06 +0000202
Marek Vasut3c43ca22010-10-20 20:55:44 +0200203#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
204#define CONFIG_SYS_CKEN 0x0
205
wdenkda27dcf2002-09-10 19:19:06 +0000206/*
207 * Memory settings
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MSC0_VAL 0x23F223F2
210#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
211#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
212#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
213#define CONFIG_SYS_MDREFR_VAL 0x00018018
214#define CONFIG_SYS_MDMRS_VAL 0x00000000
wdenkda27dcf2002-09-10 19:19:06 +0000215
Marek Vasut3c43ca22010-10-20 20:55:44 +0200216#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
217#define CONFIG_SYS_SXCNFG_VAL 0x00000000
218
wdenkda27dcf2002-09-10 19:19:06 +0000219/*
220 * PCMCIA and CF Interfaces
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_MECR_VAL 0x00000000
223#define CONFIG_SYS_MCMEM0_VAL 0x00010504
224#define CONFIG_SYS_MCMEM1_VAL 0x00010504
225#define CONFIG_SYS_MCATT0_VAL 0x00010504
226#define CONFIG_SYS_MCATT1_VAL 0x00010504
227#define CONFIG_SYS_MCIO0_VAL 0x00004715
228#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkda27dcf2002-09-10 19:19:06 +0000229
wdenk71f95112003-06-15 22:40:42 +0000230#define _LED 0x08000010
231#define LED_BLANK 0x08000040
wdenkda27dcf2002-09-10 19:19:06 +0000232
233/*
234 * FLASH and environment organization
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
237#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkda27dcf2002-09-10 19:19:06 +0000238
239/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
241#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkda27dcf2002-09-10 19:19:06 +0000242
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200243/* NOTE: many default partitioning schemes assume the kernel starts at the
244 * second sector, not an environment. You have been warned!
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200247#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200248#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
249#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
250#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
wdenkda27dcf2002-09-10 19:19:06 +0000251
252
253/*
254 * FPGA Offsets
255 */
wdenk71f95112003-06-15 22:40:42 +0000256#define WHOAMI_OFFSET 0x00
257#define HEXLED_OFFSET 0x10
258#define BLANKLED_OFFSET 0x40
259#define DISCRETELED_OFFSET 0x40
260#define CNFG_SWITCHES_OFFSET 0x50
261#define USER_SWITCHES_OFFSET 0x60
262#define MISC_WR_OFFSET 0x80
263#define MISC_RD_OFFSET 0x90
264#define INT_MASK_OFFSET 0xC0
265#define INT_CLEAR_OFFSET 0xD0
266#define GP_OFFSET 0x100
wdenkda27dcf2002-09-10 19:19:06 +0000267
wdenk71f95112003-06-15 22:40:42 +0000268#endif /* __CONFIG_H */