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wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the LUBBOCK board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk71f95112003-06-15 22:40:42 +000021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkda27dcf2002-09-10 19:19:06 +000022 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkda27dcf2002-09-10 19:19:06 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
wdenk71f95112003-06-15 22:40:42 +000037#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
39#define CONFIG_LCD 1
wdenk63cfcbb2004-10-09 22:32:26 +000040#ifdef CONFIG_LCD
41#define CONFIG_SHARP_LM8V31
42#endif
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +010043#define CONFIG_MMC
wdenkc837dcb2004-01-20 23:12:12 +000044#define BOARD_LATE_INIT 1
Jean-Christophe PLAGNIOL-VILLARD10cdb8d2007-10-19 00:24:59 +020045#define CONFIG_DOS_PARTITION
Marek Vasut3c43ca22010-10-20 20:55:44 +020046#define CONFIG_SYS_TEXT_BASE 0x0
wdenk71f95112003-06-15 22:40:42 +000047#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenkda27dcf2002-09-10 19:19:06 +000048
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020049/* we will never enable dcache, because we have to setup MMU first */
50#define CONFIG_SYS_NO_DCACHE
51
wdenkda27dcf2002-09-10 19:19:06 +000052/*
53 * Size of malloc() pool
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkda27dcf2002-09-10 19:19:06 +000056
57/*
58 * Hardware drivers
59 */
Nishanth Menonac6b3622009-10-16 00:06:37 -050060#define CONFIG_NET_MULTI
61#define CONFIG_LAN91C96
wdenk45219c42003-05-12 21:50:16 +000062#define CONFIG_LAN91C96_BASE 0x0C000000
wdenkda27dcf2002-09-10 19:19:06 +000063
64/*
65 * select serial console configuration
66 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020067#define CONFIG_PXA_SERIAL
wdenk71f95112003-06-15 22:40:42 +000068#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
wdenkda27dcf2002-09-10 19:19:06 +000069
70/* allow to overwrite serial and ethaddr */
71#define CONFIG_ENV_OVERWRITE
72
wdenk71f95112003-06-15 22:40:42 +000073#define CONFIG_BAUDRATE 115200
wdenkda27dcf2002-09-10 19:19:06 +000074
wdenkda27dcf2002-09-10 19:19:06 +000075
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050076/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050077 * BOOTP options
78 */
79#define CONFIG_BOOTP_BOOTFILESIZE
80#define CONFIG_BOOTP_BOOTPATH
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83
84
85/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050086 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050090#define CONFIG_CMD_FAT
91
wdenkda27dcf2002-09-10 19:19:06 +000092
wdenk71f95112003-06-15 22:40:42 +000093#define CONFIG_BOOTDELAY 3
94#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
95#define CONFIG_NETMASK 255.255.0.0
96#define CONFIG_IPADDR 192.168.0.21
97#define CONFIG_SERVERIP 192.168.0.250
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +020098#define CONFIG_BOOTCOMMAND "bootm 80000"
wdenk71f95112003-06-15 22:40:42 +000099#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
100#define CONFIG_CMDLINE_TAG
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200101#define CONFIG_TIMESTAMP
wdenkda27dcf2002-09-10 19:19:06 +0000102
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500103#if defined(CONFIG_CMD_KGDB)
wdenk71f95112003-06-15 22:40:42 +0000104#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
105#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
wdenkda27dcf2002-09-10 19:19:06 +0000106#endif
107
108/*
109 * Miscellaneous configurable options
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_HUSH_PARSER 1
112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk71f95112003-06-15 22:40:42 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#ifdef CONFIG_SYS_HUSH_PARSER
116#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000117#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000119#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
124#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkda27dcf2002-09-10 19:19:06 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
127#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkda27dcf2002-09-10 19:19:06 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
wdenkda27dcf2002-09-10 19:19:06 +0000130
Micha Kalfon94a33122009-02-11 19:50:11 +0200131#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
wdenkda27dcf2002-09-10 19:19:06 +0000133
wdenk71f95112003-06-15 22:40:42 +0000134 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk71f95112003-06-15 22:40:42 +0000136
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100137#ifdef CONFIG_MMC
138#define CONFIG_PXA_MMC
139#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100141#endif
wdenkda27dcf2002-09-10 19:19:06 +0000142
143/*
144 * Stack sizes
145 *
146 * The stack sizes are set up in start.S using the settings below
147 */
wdenk71f95112003-06-15 22:40:42 +0000148#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenkda27dcf2002-09-10 19:19:06 +0000149#ifdef CONFIG_USE_IRQ
wdenk71f95112003-06-15 22:40:42 +0000150#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
151#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenkda27dcf2002-09-10 19:19:06 +0000152#endif
153
154/*
155 * Physical Memory Map
156 */
wdenk71f95112003-06-15 22:40:42 +0000157#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
158#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
159#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
160#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
161#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
162#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
163#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
164#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
165#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
wdenkda27dcf2002-09-10 19:19:06 +0000166
wdenk71f95112003-06-15 22:40:42 +0000167#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
168#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
169#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
170#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
171#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkda27dcf2002-09-10 19:19:06 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DRAM_BASE 0xa0000000
174#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkda27dcf2002-09-10 19:19:06 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkda27dcf2002-09-10 19:19:06 +0000177
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200178#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200179#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200180
wdenkda27dcf2002-09-10 19:19:06 +0000181#define FPGA_REGS_BASE_PHYSICAL 0x08000000
182
183/*
184 * GPIO settings
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_GPSR0_VAL 0x00008000
187#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
188#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
189#define CONFIG_SYS_GPCR0_VAL 0x00000000
190#define CONFIG_SYS_GPCR1_VAL 0x00000000
191#define CONFIG_SYS_GPCR2_VAL 0x00000000
192#define CONFIG_SYS_GPDR0_VAL 0x0060A800
193#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
194#define CONFIG_SYS_GPDR2_VAL 0x0001C000
195#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
196#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
197#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
198#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
199#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
200#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkda27dcf2002-09-10 19:19:06 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_PSSR_VAL 0x20
wdenkda27dcf2002-09-10 19:19:06 +0000203
Marek Vasut3c43ca22010-10-20 20:55:44 +0200204#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
205#define CONFIG_SYS_CKEN 0x0
206
wdenkda27dcf2002-09-10 19:19:06 +0000207/*
208 * Memory settings
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MSC0_VAL 0x23F223F2
211#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
212#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
213#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
214#define CONFIG_SYS_MDREFR_VAL 0x00018018
215#define CONFIG_SYS_MDMRS_VAL 0x00000000
wdenkda27dcf2002-09-10 19:19:06 +0000216
Marek Vasut3c43ca22010-10-20 20:55:44 +0200217#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
218#define CONFIG_SYS_SXCNFG_VAL 0x00000000
219
wdenkda27dcf2002-09-10 19:19:06 +0000220/*
221 * PCMCIA and CF Interfaces
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MECR_VAL 0x00000000
224#define CONFIG_SYS_MCMEM0_VAL 0x00010504
225#define CONFIG_SYS_MCMEM1_VAL 0x00010504
226#define CONFIG_SYS_MCATT0_VAL 0x00010504
227#define CONFIG_SYS_MCATT1_VAL 0x00010504
228#define CONFIG_SYS_MCIO0_VAL 0x00004715
229#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkda27dcf2002-09-10 19:19:06 +0000230
wdenk71f95112003-06-15 22:40:42 +0000231#define _LED 0x08000010
232#define LED_BLANK 0x08000040
wdenkda27dcf2002-09-10 19:19:06 +0000233
234/*
235 * FLASH and environment organization
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
238#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkda27dcf2002-09-10 19:19:06 +0000239
240/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
242#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkda27dcf2002-09-10 19:19:06 +0000243
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200244/* NOTE: many default partitioning schemes assume the kernel starts at the
245 * second sector, not an environment. You have been warned!
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200248#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200249#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
250#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
251#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
wdenkda27dcf2002-09-10 19:19:06 +0000252
253
254/*
255 * FPGA Offsets
256 */
wdenk71f95112003-06-15 22:40:42 +0000257#define WHOAMI_OFFSET 0x00
258#define HEXLED_OFFSET 0x10
259#define BLANKLED_OFFSET 0x40
260#define DISCRETELED_OFFSET 0x40
261#define CNFG_SWITCHES_OFFSET 0x50
262#define USER_SWITCHES_OFFSET 0x60
263#define MISC_WR_OFFSET 0x80
264#define MISC_RD_OFFSET 0x90
265#define INT_MASK_OFFSET 0xC0
266#define INT_CLEAR_OFFSET 0xD0
267#define GP_OFFSET 0x100
wdenkda27dcf2002-09-10 19:19:06 +0000268
wdenk71f95112003-06-15 22:40:42 +0000269#endif /* __CONFIG_H */