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Hideyuki Sano1a31ca42012-06-27 10:35:35 +09001/*
2 * Configuation settings for the bonito board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Hideyuki Sano1a31ca42012-06-27 10:35:35 +09007 */
8
9#ifndef __ARMADILLO_800EVA_H
10#define __ARMADILLO_800EVA_H
11
12#undef DEBUG
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090013#define CONFIG_R8A7740
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090014#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090015#define CONFIG_SH_GPIO_PFC
16
17#include <asm/arch/rmobile.h>
18
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090019#define CONFIG_CMD_DFL
20#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu09a3be02012-08-09 15:38:47 +090021
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090022#define BOARD_LATE_INIT
23
24#define CONFIG_BAUDRATE 115200
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090025#define CONFIG_BOOTARGS ""
26
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090027#undef CONFIG_SHOW_BOOT_PROGRESS
28
29#define CONFIG_ARCH_CPU_INIT
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090030#define CONFIG_BOARD_EARLY_INIT_F
31#define CONFIG_USE_ARCH_MEMSET
32#define CONFIG_USE_ARCH_MEMCPY
33#define CONFIG_TMU_TIMER
34#define CONFIG_SYS_DCACHE_OFF
35
36/* STACK */
37#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
38#define STACK_AREA_SIZE 0xC000
39#define LOW_LEVEL_MERAM_STACK \
40 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
41
42/* MEMORY */
43#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
44#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
45
46#define CONFIG_SYS_LONGHELP
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090047#define CONFIG_SYS_CBSIZE 256
48#define CONFIG_SYS_PBSIZE 256
49#define CONFIG_SYS_MAXARGS 16
50#define CONFIG_SYS_BARGSIZE 512
51#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
52
53/* SCIF */
54#define CONFIG_SCIF_CONSOLE
55#define CONFIG_CONS_SCIF1
56#define SCIF0_BASE 0xe6c40000
57#define SCIF1_BASE 0xe6c50000
58#define SCIF2_BASE 0xe6c60000
59#define SCIF4_BASE 0xe6c80000
60#define CONFIG_SCIF_A
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090061
62#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
63#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
64 504 * 1024 * 1024)
65#undef CONFIG_SYS_ALT_MEMTEST
66#undef CONFIG_SYS_MEMTEST_SCRATCH
67#undef CONFIG_SYS_LOADS_BAUD_CHANGE
68
69#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
70#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
71#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
72 64 * 1024 * 1024)
73#define CONFIG_NR_DRAM_BANKS 1
74
75#define CONFIG_SYS_MONITOR_BASE 0x00000000
76#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
77#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090078#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
79#define CONFIG_SYS_TEXT_BASE 0xE80C0000
80
81/* FLASH */
82#define CONFIG_SYS_NO_FLASH
83#define CONFIG_SYS_FLASH_CFI
84#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
85#define CONFIG_SYS_FLASH_BASE 0x00000000
86#define CONFIG_SYS_MAX_FLASH_SECT 512
87#define CONFIG_SYS_MAX_FLASH_BANKS 1
88#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
89
90#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
91#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
92#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
93#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
94
95/* ENV setting */
96#define CONFIG_ENV_IS_IN_FLASH
97#define CONFIG_ENV_OVERWRITE 1
98#define CONFIG_ENV_SECT_SIZE (128 * 1024)
99#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
100 CONFIG_SYS_MONITOR_LEN)
101#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
102#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
103#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
104
105/* SH Ether */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +0900106#define CONFIG_SH_ETHER
107#define CONFIG_SH_ETHER_USE_PORT 0
108#define CONFIG_SH_ETHER_PHY_ADDR 0x0
109#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
110#define CONFIG_SH_ETHER_SH7734_MII (0x01)
111#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
112#define CONFIG_PHYLIB
113#define CONFIG_PHY_SMSC
114#define CONFIG_BITBANGMII
115#define CONFIG_BITBANGMII_MULTI
116
117/* Board Clock */
118#define CONFIG_SYS_CLK_FREQ 50000000
Nobuhiro Iwamatsu717ceb62013-09-30 10:30:41 +0900119#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
120#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Hideyuki Sano1a31ca42012-06-27 10:35:35 +0900121#define CONFIG_SYS_TMU_CLK_DIV 4
Hideyuki Sano1a31ca42012-06-27 10:35:35 +0900122
123#endif /* __ARMADILLO_800EVA_H */