blob: 145833287e56e9150c7e066cf13ffd0fc608740b [file] [log] [blame]
Wang Huanc8a7d9d2014-09-05 13:52:45 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Wang Huanc8a7d9d2014-09-05 13:52:45 +080010#define CONFIG_LS102XA
11
Hongbo Zhangaeb901f2016-07-21 18:09:38 +080012#define CONFIG_ARMV7_PSCI_1_0
Wang Dongsheng340848b2015-06-04 12:01:09 +080013
Hongbo Zhang32886282016-07-21 18:09:39 +080014#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
15
Gong Qianyu18fb0e32015-10-26 19:47:42 +080016#define CONFIG_SYS_FSL_CLK
Wang Huanc8a7d9d2014-09-05 13:52:45 +080017
Wang Huanc8a7d9d2014-09-05 13:52:45 +080018#define CONFIG_SKIP_LOWLEVEL_INIT
19#define CONFIG_BOARD_EARLY_INIT_F
Tang Yuantian99e1bd42015-05-14 17:20:28 +080020#define CONFIG_DEEP_SLEEP
Wang Huanc8a7d9d2014-09-05 13:52:45 +080021
22/*
23 * Size of malloc() pool
24 */
25#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
29
30/*
Ramneek Mehresh10a28642015-05-29 14:47:21 +053031 * USB
32 */
33
34/*
35 * EHCI Support - disbaled by default as
36 * there is no signal coming out of soc on
37 * this board for this controller. However,
38 * the silicon still has this controller,
39 * and anyone can use this controller by
40 * taking signals out on their board.
41 */
42
43/*#define CONFIG_HAS_FSL_DR_USB*/
44
45#ifdef CONFIG_HAS_FSL_DR_USB
46#define CONFIG_USB_EHCI
47#define CONFIG_USB_EHCI_FSL
48#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
49#endif
50
51/* XHCI Support - enabled by default */
52#define CONFIG_HAS_FSL_XHCI_USB
53
54#ifdef CONFIG_HAS_FSL_XHCI_USB
55#define CONFIG_USB_XHCI_FSL
Ramneek Mehresh10a28642015-05-29 14:47:21 +053056#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
57#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
58#endif
59
Ramneek Mehresh10a28642015-05-29 14:47:21 +053060/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +080061 * Generic Timer Definitions
62 */
63#define GENERIC_TIMER_CLK 12500000
64
65#define CONFIG_SYS_CLK_FREQ 100000000
66#define CONFIG_DDR_CLK_FREQ 100000000
67
York Suna88cc3b2015-04-29 10:35:35 -070068#define DDR_SDRAM_CFG 0x470c0008
69#define DDR_CS0_BNDS 0x008000bf
70#define DDR_CS0_CONFIG 0x80014302
71#define DDR_TIMING_CFG_0 0x50550004
72#define DDR_TIMING_CFG_1 0xbcb38c56
73#define DDR_TIMING_CFG_2 0x0040d120
74#define DDR_TIMING_CFG_3 0x010e1000
75#define DDR_TIMING_CFG_4 0x00000001
76#define DDR_TIMING_CFG_5 0x03401400
77#define DDR_SDRAM_CFG_2 0x00401010
78#define DDR_SDRAM_MODE 0x00061c60
79#define DDR_SDRAM_MODE_2 0x00180000
80#define DDR_SDRAM_INTERVAL 0x18600618
81#define DDR_DDR_WRLVL_CNTL 0x8655f605
82#define DDR_DDR_WRLVL_CNTL_2 0x05060607
83#define DDR_DDR_WRLVL_CNTL_3 0x05050505
84#define DDR_DDR_CDR1 0x80040000
85#define DDR_DDR_CDR2 0x00000001
86#define DDR_SDRAM_CLK_CNTL 0x02000000
87#define DDR_DDR_ZQ_CNTL 0x89080600
88#define DDR_CS0_CONFIG_2 0
89#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian99e1bd42015-05-14 17:20:28 +080090#define SDRAM_CFG2_D_INIT 0x00000010
91#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
92#define SDRAM_CFG2_FRC_SR 0x80000000
93#define SDRAM_CFG_BI 0x00000001
York Suna88cc3b2015-04-29 10:35:35 -070094
Alison Wang8415bb62014-12-03 15:00:48 +080095#ifdef CONFIG_RAMBOOT_PBL
96#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
97#endif
98
99#ifdef CONFIG_SD_BOOT
Alison Wang947cee12015-10-15 17:54:40 +0800100#ifdef CONFIG_SD_BOOT_QSPI
101#define CONFIG_SYS_FSL_PBL_RCW \
102 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
103#else
104#define CONFIG_SYS_FSL_PBL_RCW \
105 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
106#endif
Alison Wang8415bb62014-12-03 15:00:48 +0800107#define CONFIG_SPL_FRAMEWORK
108#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
Sumit Garge7e720c2016-06-14 13:52:40 -0400109
110#ifdef CONFIG_SECURE_BOOT
Sumit Garge7e720c2016-06-14 13:52:40 -0400111/*
112 * HDR would be appended at end of image and copied to DDR along
113 * with U-Boot image.
114 */
Semen Protsenko693d4c92016-11-16 19:19:06 +0200115#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Sumit Garge7e720c2016-06-14 13:52:40 -0400116#endif /* ifdef CONFIG_SECURE_BOOT */
Alison Wang8415bb62014-12-03 15:00:48 +0800117
118#define CONFIG_SPL_TEXT_BASE 0x10000000
119#define CONFIG_SPL_MAX_SIZE 0x1a000
120#define CONFIG_SPL_STACK 0x1001d000
121#define CONFIG_SPL_PAD_TO 0x1c000
122#define CONFIG_SYS_TEXT_BASE 0x82000000
123
Tang Yuantian99e1bd42015-05-14 17:20:28 +0800124#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
125 CONFIG_SYS_MONITOR_LEN)
Alison Wang8415bb62014-12-03 15:00:48 +0800126#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
127#define CONFIG_SPL_BSS_START_ADDR 0x80100000
128#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Sumit Garge7e720c2016-06-14 13:52:40 -0400129
130#ifdef CONFIG_U_BOOT_HDR_SIZE
131/*
132 * HDR would be appended at end of image and copied to DDR along
133 * with U-Boot image. Here u-boot max. size is 512K. So if binary
134 * size increases then increase this size in case of secure boot as
135 * it uses raw u-boot image instead of fit image.
136 */
137#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
138#else
Alison Wang8415bb62014-12-03 15:00:48 +0800139#define CONFIG_SYS_MONITOR_LEN 0x80000
Sumit Garge7e720c2016-06-14 13:52:40 -0400140#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
Alison Wang8415bb62014-12-03 15:00:48 +0800141#endif
142
Alison Wangd612f0a2014-12-09 17:38:02 +0800143#ifdef CONFIG_QSPI_BOOT
144#define CONFIG_SYS_TEXT_BASE 0x40010000
Alison Wang947cee12015-10-15 17:54:40 +0800145#endif
146
147#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wangd612f0a2014-12-09 17:38:02 +0800148#define CONFIG_SYS_NO_FLASH
149#endif
150
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800151#ifndef CONFIG_SYS_TEXT_BASE
Alison Wang1c69a512015-04-21 16:04:38 +0800152#define CONFIG_SYS_TEXT_BASE 0x60100000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800153#endif
154
155#define CONFIG_NR_DRAM_BANKS 1
156#define PHYS_SDRAM 0x80000000
157#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
158
159#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
160#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
161
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530162#define CONFIG_FSL_CAAM /* Enable CAAM */
163
Alison Wang4c59ab92014-12-09 17:37:49 +0800164#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
165 !defined(CONFIG_QSPI_BOOT)
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800166#define CONFIG_U_QE
167#endif
168
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800169/*
170 * IFC Definitions
171 */
Alison Wang947cee12015-10-15 17:54:40 +0800172#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800173#define CONFIG_FSL_IFC
174#define CONFIG_SYS_FLASH_BASE 0x60000000
175#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
176
177#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
178#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
179 CSPR_PORT_SIZE_16 | \
180 CSPR_MSEL_NOR | \
181 CSPR_V)
182#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
183
184/* NOR Flash Timing Params */
185#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
186 CSOR_NOR_TRHZ_80)
187#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
188 FTIM0_NOR_TEADC(0x5) | \
189 FTIM0_NOR_TAVDS(0x0) | \
190 FTIM0_NOR_TEAHC(0x5))
191#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
192 FTIM1_NOR_TRAD_NOR(0x1A) | \
193 FTIM1_NOR_TSEQRAD_NOR(0x13))
194#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
195 FTIM2_NOR_TCH(0x4) | \
196 FTIM2_NOR_TWP(0x1c) | \
197 FTIM2_NOR_TWPH(0x0e))
198#define CONFIG_SYS_NOR_FTIM3 0
199
200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_CFI
202#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
203#define CONFIG_SYS_FLASH_QUIET_TEST
204#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
205
206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
208#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
209#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
210
211#define CONFIG_SYS_FLASH_EMPTY_INFO
212#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
213
214#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800215#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800216#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800217
218/* CPLD */
219
220#define CONFIG_SYS_CPLD_BASE 0x7fb00000
221#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
222
223#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
224#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
225 CSPR_PORT_SIZE_8 | \
226 CSPR_MSEL_GPCM | \
227 CSPR_V)
228#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
229#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
230 CSOR_NOR_NOR_MODE_AVD_NOR | \
231 CSOR_NOR_TRHZ_80)
232
233/* CPLD Timing parameters for IFC GPCM */
234#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
235 FTIM0_GPCM_TEADC(0xf) | \
236 FTIM0_GPCM_TEAHC(0xf))
237#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
238 FTIM1_GPCM_TRAD(0x3f))
239#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
240 FTIM2_GPCM_TCH(0xf) | \
241 FTIM2_GPCM_TWP(0xff))
242#define CONFIG_SYS_FPGA_FTIM3 0x0
243#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
244#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
245#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
246#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
247#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
248#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
249#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
250#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
251#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
252#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
253#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
254#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
255#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
256#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
257#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
258#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
259
260/*
261 * Serial Port
262 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800263#ifdef CONFIG_LPUART
Alison Wang55d53ab2015-01-04 15:30:59 +0800264#define CONFIG_LPUART_32B_REG
265#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800266#define CONFIG_CONS_INDEX 1
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800267#define CONFIG_SYS_NS16550_SERIAL
Bin Mengf833cd62016-01-13 19:38:59 -0800268#ifndef CONFIG_DM_SERIAL
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800269#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Mengf833cd62016-01-13 19:38:59 -0800270#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800271#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800272#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800273
274#define CONFIG_BAUDRATE 115200
275
276/*
277 * I2C
278 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800279#define CONFIG_SYS_I2C
280#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200281#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
282#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700283#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800284
Alison Wang5175a282014-10-17 15:26:35 +0800285/* EEPROM */
Alison Wang5175a282014-10-17 15:26:35 +0800286#define CONFIG_ID_EEPROM
287#define CONFIG_SYS_I2C_EEPROM_NXID
288#define CONFIG_SYS_EEPROM_BUS_NUM 1
289#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
290#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
291#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
292#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Alison Wang5175a282014-10-17 15:26:35 +0800293
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800294/*
295 * MMC
296 */
297#define CONFIG_MMC
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800298#define CONFIG_FSL_ESDHC
299#define CONFIG_GENERIC_MMC
300
Alison Wang8251ed22014-12-09 17:37:34 +0800301#define CONFIG_DOS_PARTITION
302
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530303/* SPI */
Alison Wang947cee12015-10-15 17:54:40 +0800304#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530305/* QSPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800306#define QSPI0_AMBA_BASE 0x40000000
307#define FSL_QSPI_FLASH_SIZE (1 << 24)
308#define FSL_QSPI_FLASH_NUM 2
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530309
Yao Yuan03d1d562015-09-15 18:28:20 +0800310/* DSPI */
Yao Yuan03d1d562015-09-15 18:28:20 +0800311#endif
312
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530313/* DM SPI */
314#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530315#define CONFIG_DM_SPI_FLASH
316#endif
Alison Wangd612f0a2014-12-09 17:38:02 +0800317
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800318/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800319 * Video
320 */
321#define CONFIG_FSL_DCU_FB
322
323#ifdef CONFIG_FSL_DCU_FB
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800324#define CONFIG_CMD_BMP
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800325#define CONFIG_VIDEO_LOGO
326#define CONFIG_VIDEO_BMP_LOGO
327
328#define CONFIG_FSL_DCU_SII9022A
329#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
330#define CONFIG_SYS_I2C_DVI_ADDR 0x39
331#endif
332
333/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800334 * eTSEC
335 */
336#define CONFIG_TSEC_ENET
337
338#ifdef CONFIG_TSEC_ENET
339#define CONFIG_MII
340#define CONFIG_MII_DEFAULT_TSEC 1
341#define CONFIG_TSEC1 1
342#define CONFIG_TSEC1_NAME "eTSEC1"
343#define CONFIG_TSEC2 1
344#define CONFIG_TSEC2_NAME "eTSEC2"
345#define CONFIG_TSEC3 1
346#define CONFIG_TSEC3_NAME "eTSEC3"
347
348#define TSEC1_PHY_ADDR 2
349#define TSEC2_PHY_ADDR 0
350#define TSEC3_PHY_ADDR 1
351
352#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
354#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
355
356#define TSEC1_PHYIDX 0
357#define TSEC2_PHYIDX 0
358#define TSEC3_PHYIDX 0
359
360#define CONFIG_ETHPRIME "eTSEC1"
361
362#define CONFIG_PHY_GIGE
363#define CONFIG_PHYLIB
364#define CONFIG_PHY_ATHEROS
365
366#define CONFIG_HAS_ETH0
367#define CONFIG_HAS_ETH1
368#define CONFIG_HAS_ETH2
369#endif
370
Minghuan Lianda419022014-10-31 13:43:44 +0800371/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400372#define CONFIG_PCIE1 /* PCIE controller 1 */
373#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Lianda419022014-10-31 13:43:44 +0800374#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
375#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
376
Minghuan Lian180b8682015-01-21 17:29:19 +0800377#define CONFIG_SYS_PCI_64BIT
378
379#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
380#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
381#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
382#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
383
384#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
385#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
386#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
387
388#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
389#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
390#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
391
392#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800393#define CONFIG_PCI_SCAN_SHOW
394#define CONFIG_CMD_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800395#endif
396
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800397#define CONFIG_CMDLINE_TAG
398#define CONFIG_CMDLINE_EDITING
Alison Wang8415bb62014-12-03 15:00:48 +0800399
Xiubo Li1a2826f2014-11-21 17:40:57 +0800400#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800401#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800402#define CONFIG_SMP_PEN_ADDR 0x01ee0200
403#define CONFIG_TIMER_CLK_FREQ 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800404
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800405#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800406#define HWCONFIG_BUFFER_SIZE 256
407
408#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800409
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800410
Alison Wang55d53ab2015-01-04 15:30:59 +0800411#ifdef CONFIG_LPUART
412#define CONFIG_EXTRA_ENV_SETTINGS \
413 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800414 "initrd_high=0xffffffff\0" \
415 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800416#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800417#define CONFIG_EXTRA_ENV_SETTINGS \
418 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800419 "initrd_high=0xffffffff\0" \
420 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800421#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800422
423/*
424 * Miscellaneous configurable options
425 */
426#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800427#define CONFIG_AUTO_COMPLETE
428#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
429#define CONFIG_SYS_PBSIZE \
430 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
431#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
432#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
433
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800434#define CONFIG_SYS_MEMTEST_START 0x80000000
435#define CONFIG_SYS_MEMTEST_END 0x9fffffff
436
437#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800438
Xiubo Li660673a2014-11-21 17:40:59 +0800439#define CONFIG_LS102XA_STREAM_ID
440
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800441/*
442 * Stack sizes
443 * The stack sizes are set up in start.S using the settings below
444 */
445#define CONFIG_STACKSIZE (30 * 1024)
446
447#define CONFIG_SYS_INIT_SP_OFFSET \
448 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
449#define CONFIG_SYS_INIT_SP_ADDR \
450 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
451
Alison Wang8415bb62014-12-03 15:00:48 +0800452#ifdef CONFIG_SPL_BUILD
453#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
454#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800455#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800456#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800457
Zhao Qiang713bf942015-09-16 16:20:42 +0800458#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800459
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800460/*
461 * Environment
462 */
463#define CONFIG_ENV_OVERWRITE
464
Alison Wang8415bb62014-12-03 15:00:48 +0800465#if defined(CONFIG_SD_BOOT)
466#define CONFIG_ENV_OFFSET 0x100000
467#define CONFIG_ENV_IS_IN_MMC
468#define CONFIG_SYS_MMC_ENV_DEV 0
469#define CONFIG_ENV_SIZE 0x20000
Alison Wangd612f0a2014-12-09 17:38:02 +0800470#elif defined(CONFIG_QSPI_BOOT)
471#define CONFIG_ENV_IS_IN_SPI_FLASH
472#define CONFIG_ENV_SIZE 0x2000
473#define CONFIG_ENV_OFFSET 0x100000
474#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8415bb62014-12-03 15:00:48 +0800475#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800476#define CONFIG_ENV_IS_IN_FLASH
477#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
478#define CONFIG_ENV_SIZE 0x20000
479#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang8415bb62014-12-03 15:00:48 +0800480#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800481
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530482#define CONFIG_MISC_INIT_R
483
484/* Hash command with SHA acceleration supported in hardware */
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530485#ifdef CONFIG_FSL_CAAM
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530486#define CONFIG_CMD_HASH
487#define CONFIG_SHA_HW_ACCEL
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530488#endif
489
490#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800491#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530492
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800493#endif