blob: ae58646d5e9bbb918d7e912942963d1bb88c55a3 [file] [log] [blame]
Wang Huanc8a7d9d2014-09-05 13:52:45 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Wang Huanc8a7d9d2014-09-05 13:52:45 +080010#define CONFIG_LS102XA
11
Wang Dongsheng340848b2015-06-04 12:01:09 +080012#define CONFIG_ARMV7_PSCI
13
Gong Qianyu18fb0e32015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Wang Huanc8a7d9d2014-09-05 13:52:45 +080015
16#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_BOARD_EARLY_INIT_F
Tang Yuantian99e1bd42015-05-14 17:20:28 +080021#define CONFIG_DEEP_SLEEP
22#ifdef CONFIG_DEEP_SLEEP
23#define CONFIG_SILENT_CONSOLE
24#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +080025
26/*
27 * Size of malloc() pool
28 */
29#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30
31#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
32#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
33
34/*
Ramneek Mehresh10a28642015-05-29 14:47:21 +053035 * USB
36 */
37
38/*
39 * EHCI Support - disbaled by default as
40 * there is no signal coming out of soc on
41 * this board for this controller. However,
42 * the silicon still has this controller,
43 * and anyone can use this controller by
44 * taking signals out on their board.
45 */
46
47/*#define CONFIG_HAS_FSL_DR_USB*/
48
49#ifdef CONFIG_HAS_FSL_DR_USB
50#define CONFIG_USB_EHCI
51#define CONFIG_USB_EHCI_FSL
52#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
53#endif
54
55/* XHCI Support - enabled by default */
56#define CONFIG_HAS_FSL_XHCI_USB
57
58#ifdef CONFIG_HAS_FSL_XHCI_USB
59#define CONFIG_USB_XHCI_FSL
60#define CONFIG_USB_XHCI_DWC3
61#define CONFIG_USB_XHCI
62#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
64#endif
65
66#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
67#define CONFIG_CMD_USB
68#define CONFIG_USB_STORAGE
69#define CONFIG_CMD_EXT2
70#endif
71
72/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +080073 * Generic Timer Definitions
74 */
75#define GENERIC_TIMER_CLK 12500000
76
77#define CONFIG_SYS_CLK_FREQ 100000000
78#define CONFIG_DDR_CLK_FREQ 100000000
79
York Suna88cc3b2015-04-29 10:35:35 -070080#define DDR_SDRAM_CFG 0x470c0008
81#define DDR_CS0_BNDS 0x008000bf
82#define DDR_CS0_CONFIG 0x80014302
83#define DDR_TIMING_CFG_0 0x50550004
84#define DDR_TIMING_CFG_1 0xbcb38c56
85#define DDR_TIMING_CFG_2 0x0040d120
86#define DDR_TIMING_CFG_3 0x010e1000
87#define DDR_TIMING_CFG_4 0x00000001
88#define DDR_TIMING_CFG_5 0x03401400
89#define DDR_SDRAM_CFG_2 0x00401010
90#define DDR_SDRAM_MODE 0x00061c60
91#define DDR_SDRAM_MODE_2 0x00180000
92#define DDR_SDRAM_INTERVAL 0x18600618
93#define DDR_DDR_WRLVL_CNTL 0x8655f605
94#define DDR_DDR_WRLVL_CNTL_2 0x05060607
95#define DDR_DDR_WRLVL_CNTL_3 0x05050505
96#define DDR_DDR_CDR1 0x80040000
97#define DDR_DDR_CDR2 0x00000001
98#define DDR_SDRAM_CLK_CNTL 0x02000000
99#define DDR_DDR_ZQ_CNTL 0x89080600
100#define DDR_CS0_CONFIG_2 0
101#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian99e1bd42015-05-14 17:20:28 +0800102#define SDRAM_CFG2_D_INIT 0x00000010
103#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
104#define SDRAM_CFG2_FRC_SR 0x80000000
105#define SDRAM_CFG_BI 0x00000001
York Suna88cc3b2015-04-29 10:35:35 -0700106
Alison Wang8415bb62014-12-03 15:00:48 +0800107#ifdef CONFIG_RAMBOOT_PBL
108#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
109#endif
110
111#ifdef CONFIG_SD_BOOT
Alison Wang947cee12015-10-15 17:54:40 +0800112#ifdef CONFIG_SD_BOOT_QSPI
113#define CONFIG_SYS_FSL_PBL_RCW \
114 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
115#else
116#define CONFIG_SYS_FSL_PBL_RCW \
117 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
118#endif
Alison Wang8415bb62014-12-03 15:00:48 +0800119#define CONFIG_SPL_FRAMEWORK
120#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
121#define CONFIG_SPL_LIBCOMMON_SUPPORT
122#define CONFIG_SPL_LIBGENERIC_SUPPORT
123#define CONFIG_SPL_ENV_SUPPORT
124#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
125#define CONFIG_SPL_I2C_SUPPORT
126#define CONFIG_SPL_WATCHDOG_SUPPORT
127#define CONFIG_SPL_SERIAL_SUPPORT
128#define CONFIG_SPL_MMC_SUPPORT
129#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
130#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
131
132#define CONFIG_SPL_TEXT_BASE 0x10000000
133#define CONFIG_SPL_MAX_SIZE 0x1a000
134#define CONFIG_SPL_STACK 0x1001d000
135#define CONFIG_SPL_PAD_TO 0x1c000
136#define CONFIG_SYS_TEXT_BASE 0x82000000
137
Tang Yuantian99e1bd42015-05-14 17:20:28 +0800138#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
139 CONFIG_SYS_MONITOR_LEN)
Alison Wang8415bb62014-12-03 15:00:48 +0800140#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
141#define CONFIG_SPL_BSS_START_ADDR 0x80100000
142#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
143#define CONFIG_SYS_MONITOR_LEN 0x80000
144#endif
145
Alison Wangd612f0a2014-12-09 17:38:02 +0800146#ifdef CONFIG_QSPI_BOOT
147#define CONFIG_SYS_TEXT_BASE 0x40010000
Alison Wang947cee12015-10-15 17:54:40 +0800148#endif
149
150#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wangd612f0a2014-12-09 17:38:02 +0800151#define CONFIG_SYS_NO_FLASH
152#endif
153
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800154#ifndef CONFIG_SYS_TEXT_BASE
Alison Wang1c69a512015-04-21 16:04:38 +0800155#define CONFIG_SYS_TEXT_BASE 0x60100000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800156#endif
157
158#define CONFIG_NR_DRAM_BANKS 1
159#define PHYS_SDRAM 0x80000000
160#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
161
162#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
163#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
164
165#define CONFIG_SYS_HAS_SERDES
166
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530167#define CONFIG_FSL_CAAM /* Enable CAAM */
168
Alison Wang4c59ab92014-12-09 17:37:49 +0800169#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
170 !defined(CONFIG_QSPI_BOOT)
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800171#define CONFIG_U_QE
172#endif
173
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800174/*
175 * IFC Definitions
176 */
Alison Wang947cee12015-10-15 17:54:40 +0800177#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800178#define CONFIG_FSL_IFC
179#define CONFIG_SYS_FLASH_BASE 0x60000000
180#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
181
182#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
183#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
184 CSPR_PORT_SIZE_16 | \
185 CSPR_MSEL_NOR | \
186 CSPR_V)
187#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
188
189/* NOR Flash Timing Params */
190#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
191 CSOR_NOR_TRHZ_80)
192#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
193 FTIM0_NOR_TEADC(0x5) | \
194 FTIM0_NOR_TAVDS(0x0) | \
195 FTIM0_NOR_TEAHC(0x5))
196#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
197 FTIM1_NOR_TRAD_NOR(0x1A) | \
198 FTIM1_NOR_TSEQRAD_NOR(0x13))
199#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
200 FTIM2_NOR_TCH(0x4) | \
201 FTIM2_NOR_TWP(0x1c) | \
202 FTIM2_NOR_TWPH(0x0e))
203#define CONFIG_SYS_NOR_FTIM3 0
204
205#define CONFIG_FLASH_CFI_DRIVER
206#define CONFIG_SYS_FLASH_CFI
207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
208#define CONFIG_SYS_FLASH_QUIET_TEST
209#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
210
211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
212#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
213#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
214#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
215
216#define CONFIG_SYS_FLASH_EMPTY_INFO
217#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
218
219#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800220#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800221#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800222
223/* CPLD */
224
225#define CONFIG_SYS_CPLD_BASE 0x7fb00000
226#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
227
228#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
229#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
230 CSPR_PORT_SIZE_8 | \
231 CSPR_MSEL_GPCM | \
232 CSPR_V)
233#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
234#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
235 CSOR_NOR_NOR_MODE_AVD_NOR | \
236 CSOR_NOR_TRHZ_80)
237
238/* CPLD Timing parameters for IFC GPCM */
239#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
240 FTIM0_GPCM_TEADC(0xf) | \
241 FTIM0_GPCM_TEAHC(0xf))
242#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
243 FTIM1_GPCM_TRAD(0x3f))
244#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
245 FTIM2_GPCM_TCH(0xf) | \
246 FTIM2_GPCM_TWP(0xff))
247#define CONFIG_SYS_FPGA_FTIM3 0x0
248#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
249#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
250#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
251#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
252#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
253#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
254#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
255#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
256#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
257#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
258#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
259#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
260#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
261#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
262#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
263#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
264
265/*
266 * Serial Port
267 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800268#ifdef CONFIG_LPUART
Alison Wang55d53ab2015-01-04 15:30:59 +0800269#define CONFIG_LPUART_32B_REG
270#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800271#define CONFIG_CONS_INDEX 1
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800272#define CONFIG_SYS_NS16550_SERIAL
Bin Mengf833cd62016-01-13 19:38:59 -0800273#ifndef CONFIG_DM_SERIAL
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800274#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Mengf833cd62016-01-13 19:38:59 -0800275#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800276#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800277#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800278
279#define CONFIG_BAUDRATE 115200
280
281/*
282 * I2C
283 */
284#define CONFIG_CMD_I2C
285#define CONFIG_SYS_I2C
286#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200287#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
288#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700289#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800290
Alison Wang5175a282014-10-17 15:26:35 +0800291/* EEPROM */
Alison Wang5175a282014-10-17 15:26:35 +0800292#define CONFIG_ID_EEPROM
293#define CONFIG_SYS_I2C_EEPROM_NXID
294#define CONFIG_SYS_EEPROM_BUS_NUM 1
295#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
296#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
297#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
298#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Alison Wang5175a282014-10-17 15:26:35 +0800299
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800300/*
301 * MMC
302 */
303#define CONFIG_MMC
304#define CONFIG_CMD_MMC
305#define CONFIG_FSL_ESDHC
306#define CONFIG_GENERIC_MMC
307
Alison Wang8251ed22014-12-09 17:37:34 +0800308#define CONFIG_CMD_FAT
309#define CONFIG_DOS_PARTITION
310
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530311/* SPI */
Alison Wang947cee12015-10-15 17:54:40 +0800312#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530313/* QSPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800314#define QSPI0_AMBA_BASE 0x40000000
315#define FSL_QSPI_FLASH_SIZE (1 << 24)
316#define FSL_QSPI_FLASH_NUM 2
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530317
Yao Yuan03d1d562015-09-15 18:28:20 +0800318/* DSPI */
Yao Yuan03d1d562015-09-15 18:28:20 +0800319#endif
320
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530321/* DM SPI */
322#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
323#define CONFIG_CMD_SF
324#define CONFIG_DM_SPI_FLASH
325#endif
Alison Wangd612f0a2014-12-09 17:38:02 +0800326
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800327/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800328 * Video
329 */
330#define CONFIG_FSL_DCU_FB
331
332#ifdef CONFIG_FSL_DCU_FB
333#define CONFIG_VIDEO
334#define CONFIG_CMD_BMP
335#define CONFIG_CFB_CONSOLE
336#define CONFIG_VGA_AS_SINGLE_DEVICE
337#define CONFIG_VIDEO_LOGO
338#define CONFIG_VIDEO_BMP_LOGO
339
340#define CONFIG_FSL_DCU_SII9022A
341#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
342#define CONFIG_SYS_I2C_DVI_ADDR 0x39
343#endif
344
345/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800346 * eTSEC
347 */
348#define CONFIG_TSEC_ENET
349
350#ifdef CONFIG_TSEC_ENET
351#define CONFIG_MII
352#define CONFIG_MII_DEFAULT_TSEC 1
353#define CONFIG_TSEC1 1
354#define CONFIG_TSEC1_NAME "eTSEC1"
355#define CONFIG_TSEC2 1
356#define CONFIG_TSEC2_NAME "eTSEC2"
357#define CONFIG_TSEC3 1
358#define CONFIG_TSEC3_NAME "eTSEC3"
359
360#define TSEC1_PHY_ADDR 2
361#define TSEC2_PHY_ADDR 0
362#define TSEC3_PHY_ADDR 1
363
364#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
365#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
366#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
367
368#define TSEC1_PHYIDX 0
369#define TSEC2_PHYIDX 0
370#define TSEC3_PHYIDX 0
371
372#define CONFIG_ETHPRIME "eTSEC1"
373
374#define CONFIG_PHY_GIGE
375#define CONFIG_PHYLIB
376#define CONFIG_PHY_ATHEROS
377
378#define CONFIG_HAS_ETH0
379#define CONFIG_HAS_ETH1
380#define CONFIG_HAS_ETH2
381#endif
382
Minghuan Lianda419022014-10-31 13:43:44 +0800383/* PCIe */
384#define CONFIG_PCI /* Enable PCI/PCIE */
385#define CONFIG_PCIE1 /* PCIE controler 1 */
386#define CONFIG_PCIE2 /* PCIE controler 2 */
387#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
388#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
389
Minghuan Lian180b8682015-01-21 17:29:19 +0800390#define CONFIG_SYS_PCI_64BIT
391
392#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
393#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
394#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
395#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
396
397#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
398#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
399#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
400
401#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
402#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
403#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
404
405#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800406#define CONFIG_PCI_PNP
Minghuan Lian180b8682015-01-21 17:29:19 +0800407#define CONFIG_PCI_SCAN_SHOW
408#define CONFIG_CMD_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800409#endif
410
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800411#define CONFIG_CMD_PING
412#define CONFIG_CMD_DHCP
413#define CONFIG_CMD_MII
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800414
415#define CONFIG_CMDLINE_TAG
416#define CONFIG_CMDLINE_EDITING
Alison Wang8415bb62014-12-03 15:00:48 +0800417
Alison Wang947cee12015-10-15 17:54:40 +0800418#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
419#undef CONFIG_CMD_IMLS
420#endif
421
Xiubo Li1a2826f2014-11-21 17:40:57 +0800422#define CONFIG_ARMV7_NONSEC
423#define CONFIG_ARMV7_VIRT
424#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800425#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800426#define CONFIG_SMP_PEN_ADDR 0x01ee0200
427#define CONFIG_TIMER_CLK_FREQ 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800428
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800429#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800430#define HWCONFIG_BUFFER_SIZE 256
431
432#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800433
434#define CONFIG_BOOTDELAY 3
435
Alison Wang55d53ab2015-01-04 15:30:59 +0800436#ifdef CONFIG_LPUART
437#define CONFIG_EXTRA_ENV_SETTINGS \
438 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800439 "initrd_high=0xffffffff\0" \
440 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800441#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800442#define CONFIG_EXTRA_ENV_SETTINGS \
443 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800444 "initrd_high=0xffffffff\0" \
445 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800446#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800447
448/*
449 * Miscellaneous configurable options
450 */
451#define CONFIG_SYS_LONGHELP /* undef to save memory */
452#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
453#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800454#define CONFIG_AUTO_COMPLETE
455#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
456#define CONFIG_SYS_PBSIZE \
457 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
458#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
459#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
460
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800461#define CONFIG_CMD_GREPENV
462#define CONFIG_CMD_MEMINFO
463#define CONFIG_CMD_MEMTEST
464#define CONFIG_SYS_MEMTEST_START 0x80000000
465#define CONFIG_SYS_MEMTEST_END 0x9fffffff
466
467#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800468
Xiubo Li660673a2014-11-21 17:40:59 +0800469#define CONFIG_LS102XA_STREAM_ID
470
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800471/*
472 * Stack sizes
473 * The stack sizes are set up in start.S using the settings below
474 */
475#define CONFIG_STACKSIZE (30 * 1024)
476
477#define CONFIG_SYS_INIT_SP_OFFSET \
478 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
479#define CONFIG_SYS_INIT_SP_ADDR \
480 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
481
Alison Wang8415bb62014-12-03 15:00:48 +0800482#ifdef CONFIG_SPL_BUILD
483#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
484#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800485#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800486#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800487
Zhao Qiang713bf942015-09-16 16:20:42 +0800488#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800489
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800490/*
491 * Environment
492 */
493#define CONFIG_ENV_OVERWRITE
494
Alison Wang8415bb62014-12-03 15:00:48 +0800495#if defined(CONFIG_SD_BOOT)
496#define CONFIG_ENV_OFFSET 0x100000
497#define CONFIG_ENV_IS_IN_MMC
498#define CONFIG_SYS_MMC_ENV_DEV 0
499#define CONFIG_ENV_SIZE 0x20000
Alison Wangd612f0a2014-12-09 17:38:02 +0800500#elif defined(CONFIG_QSPI_BOOT)
501#define CONFIG_ENV_IS_IN_SPI_FLASH
502#define CONFIG_ENV_SIZE 0x2000
503#define CONFIG_ENV_OFFSET 0x100000
504#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8415bb62014-12-03 15:00:48 +0800505#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800506#define CONFIG_ENV_IS_IN_FLASH
507#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
508#define CONFIG_ENV_SIZE 0x20000
509#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang8415bb62014-12-03 15:00:48 +0800510#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800511
512#define CONFIG_OF_LIBFDT
513#define CONFIG_OF_BOARD_SETUP
Scott Wood6b6db0d2015-08-31 21:05:49 -0500514#define CONFIG_OF_STDOUT_VIA_ALIAS
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800515#define CONFIG_CMD_BOOTZ
516
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530517#define CONFIG_MISC_INIT_R
518
519/* Hash command with SHA acceleration supported in hardware */
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530520#ifdef CONFIG_FSL_CAAM
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530521#define CONFIG_CMD_HASH
522#define CONFIG_SHA_HW_ACCEL
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530523#endif
524
525#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800526#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530527
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800528#endif