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Graeme Russd47ab0e2011-12-23 16:51:29 +11001/*
2 * (C) Copyright 2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Graeme Russd47ab0e2011-12-23 16:51:29 +11006 */
Bin Mengc17ca6b2015-08-13 00:29:10 -07007
Graeme Russd47ab0e2011-12-23 16:51:29 +11008#include <common.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +09009#include <linux/errno.h>
Simon Glassdb55bd72015-01-01 16:18:11 -070010#include <asm/mtrr.h>
Graeme Russd47ab0e2011-12-23 16:51:29 +110011
12DECLARE_GLOBAL_DATA_PTR;
13
Simon Glass5e989472013-02-28 19:26:10 +000014/* Get the top of usable RAM */
15__weak ulong board_get_usable_ram_top(ulong total_size)
Graeme Russa1d57b72011-12-23 21:14:22 +110016{
Simon Glass5e989472013-02-28 19:26:10 +000017 return gd->ram_size;
18}
19
Graeme Russa1d57b72011-12-23 21:14:22 +110020int init_cache_f_r(void)
21{
Simon Glassdb55bd72015-01-01 16:18:11 -070022#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
23 int ret;
24
25 ret = mtrr_commit(false);
Bin Meng3b621cc2015-01-22 11:29:41 +080026 /* If MTRR MSR is not implemented by the processor, just ignore it */
27 if (ret && ret != -ENOSYS)
Simon Glassdb55bd72015-01-01 16:18:11 -070028 return ret;
29#endif
Graeme Russa1d57b72011-12-23 21:14:22 +110030 /* Initialise the CPU cache(s) */
31 return init_cache();
32}