blob: b0ee0de1361741321348b8cffa2842e0ca8f5d2b [file] [log] [blame]
Shengzhou Liuc4d0e812013-11-22 17:39:11 +08001/*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
Shengzhou Liu254887a2014-02-21 13:16:19 +08008 * T2080/T2081 QDS board configuration file
Shengzhou Liuc4d0e812013-11-22 17:39:11 +08009 */
10
Shengzhou Liu254887a2014-02-21 13:16:19 +080011#ifndef __T208xQDS_H
12#define __T208xQDS_H
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080013
Shengzhou Liufb536872014-07-23 15:54:16 +080014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080016#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17#define CONFIG_MMC
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080018#define CONFIG_USB_EHCI
Shengzhou Liu254887a2014-02-21 13:16:19 +080019#if defined(CONFIG_PPC_T2080)
20#define CONFIG_T2080QDS
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080021#define CONFIG_FSL_SATA_V2
22#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
23#define CONFIG_SRIO1 /* SRIO port 1 */
24#define CONFIG_SRIO2 /* SRIO port 2 */
Shengzhou Liu254887a2014-02-21 13:16:19 +080025#elif defined(CONFIG_PPC_T2081)
26#define CONFIG_T2081QDS
27#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080028
29/* High Level Configuration Options */
30#define CONFIG_PHYS_64BIT
31#define CONFIG_BOOKE
32#define CONFIG_E500 /* BOOKE e500 family */
33#define CONFIG_E500MC /* BOOKE e500mc family */
34#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080035#define CONFIG_MP /* support multiple processors */
36#define CONFIG_ENABLE_36BIT_PHYS
37
38#ifdef CONFIG_PHYS_64BIT
39#define CONFIG_ADDR_MAP 1
40#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
41#endif
42
43#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
44#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
45#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053046#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080047#define CONFIG_FSL_LAW /* Use common FSL init code */
48#define CONFIG_ENV_OVERWRITE
49
50#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090051#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080052#if defined(CONFIG_PPC_T2080)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090053#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080054#elif defined(CONFIG_PPC_T2081)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090055#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080056#endif
Shengzhou Liub19e2882014-04-18 16:43:39 +080057
Shengzhou Liub19e2882014-04-18 16:43:39 +080058#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
59#define CONFIG_SPL_ENV_SUPPORT
60#define CONFIG_SPL_SERIAL_SUPPORT
61#define CONFIG_SPL_FLUSH_IMAGE
62#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
63#define CONFIG_SPL_LIBGENERIC_SUPPORT
64#define CONFIG_SPL_LIBCOMMON_SUPPORT
65#define CONFIG_SPL_I2C_SUPPORT
66#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
67#define CONFIG_FSL_LAW /* Use common FSL init code */
68#define CONFIG_SYS_TEXT_BASE 0x00201000
69#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
70#define CONFIG_SPL_PAD_TO 0x40000
71#define CONFIG_SPL_MAX_SIZE 0x28000
72#define RESET_VECTOR_OFFSET 0x27FFC
73#define BOOT_PAGE_OFFSET 0x27000
74#ifdef CONFIG_SPL_BUILD
75#define CONFIG_SPL_SKIP_RELOCATE
76#define CONFIG_SPL_COMMON_INIT_DDR
77#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
78#define CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080079#endif
80
Shengzhou Liub19e2882014-04-18 16:43:39 +080081#ifdef CONFIG_NAND
82#define CONFIG_SPL_NAND_SUPPORT
83#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
84#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
85#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
86#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
87#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
88#define CONFIG_SPL_NAND_BOOT
89#endif
90
91#ifdef CONFIG_SPIFLASH
92#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
93#define CONFIG_SPL_SPI_SUPPORT
94#define CONFIG_SPL_SPI_FLASH_SUPPORT
95#define CONFIG_SPL_SPI_FLASH_MINIMAL
96#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
97#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
98#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
99#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
100#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
101#ifndef CONFIG_SPL_BUILD
102#define CONFIG_SYS_MPC85XX_NO_RESETVEC
103#endif
104#define CONFIG_SPL_SPI_BOOT
105#endif
106
107#ifdef CONFIG_SDCARD
108#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
109#define CONFIG_SPL_MMC_SUPPORT
110#define CONFIG_SPL_MMC_MINIMAL
111#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
112#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
113#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
114#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
115#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
116#ifndef CONFIG_SPL_BUILD
117#define CONFIG_SYS_MPC85XX_NO_RESETVEC
118#endif
119#define CONFIG_SPL_MMC_BOOT
120#endif
121
122#endif /* CONFIG_RAMBOOT_PBL */
123
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800124#define CONFIG_SRIO_PCIE_BOOT_MASTER
125#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
126/* Set 1M boot space */
127#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
128#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
129 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
130#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
131#define CONFIG_SYS_NO_FLASH
132#endif
133
134#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530135#define CONFIG_SYS_TEXT_BASE 0xeff40000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800136#endif
137
138#ifndef CONFIG_RESET_VECTOR_ADDRESS
139#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
140#endif
141
142/*
143 * These can be toggled for performance analysis, otherwise use default.
144 */
145#define CONFIG_SYS_CACHE_STASHING
146#define CONFIG_BTB /* toggle branch predition */
147#define CONFIG_DDR_ECC
148#ifdef CONFIG_DDR_ECC
149#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
150#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
151#endif
152
Shengzhou Liub19e2882014-04-18 16:43:39 +0800153#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800154#define CONFIG_FLASH_CFI_DRIVER
155#define CONFIG_SYS_FLASH_CFI
156#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
157#endif
158
159#if defined(CONFIG_SPIFLASH)
160#define CONFIG_SYS_EXTRA_ENV_RELOC
161#define CONFIG_ENV_IS_IN_SPI_FLASH
162#define CONFIG_ENV_SPI_BUS 0
163#define CONFIG_ENV_SPI_CS 0
164#define CONFIG_ENV_SPI_MAX_HZ 10000000
165#define CONFIG_ENV_SPI_MODE 0
166#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
167#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
168#define CONFIG_ENV_SECT_SIZE 0x10000
169#elif defined(CONFIG_SDCARD)
170#define CONFIG_SYS_EXTRA_ENV_RELOC
171#define CONFIG_ENV_IS_IN_MMC
172#define CONFIG_SYS_MMC_ENV_DEV 0
173#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liub19e2882014-04-18 16:43:39 +0800174#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800175#elif defined(CONFIG_NAND)
176#define CONFIG_SYS_EXTRA_ENV_RELOC
177#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800178#define CONFIG_ENV_SIZE 0x2000
179#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800180#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
181#define CONFIG_ENV_IS_IN_REMOTE
182#define CONFIG_ENV_ADDR 0xffe20000
183#define CONFIG_ENV_SIZE 0x2000
184#elif defined(CONFIG_ENV_IS_NOWHERE)
185#define CONFIG_ENV_SIZE 0x2000
186#else
187#define CONFIG_ENV_IS_IN_FLASH
188#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE 0x2000
190#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
191#endif
192
193#ifndef __ASSEMBLY__
194unsigned long get_board_sys_clk(void);
195unsigned long get_board_ddr_clk(void);
196#endif
197
198#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
199#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
200
201/*
202 * Config the L3 Cache as L3 SRAM
203 */
Shengzhou Liub19e2882014-04-18 16:43:39 +0800204#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
205#define CONFIG_SYS_L3_SIZE (512 << 10)
206#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
207#ifdef CONFIG_RAMBOOT_PBL
208#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
209#endif
210#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
211#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
212#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
213#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800214
215#define CONFIG_SYS_DCSRBAR 0xf0000000
216#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
217
218/* EEPROM */
219#define CONFIG_ID_EEPROM
220#define CONFIG_SYS_I2C_EEPROM_NXID
221#define CONFIG_SYS_EEPROM_BUS_NUM 0
222#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
223#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
224
225/*
226 * DDR Setup
227 */
228#define CONFIG_VERY_BIG_RAM
229#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
230#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liu40483e12014-05-20 12:08:20 +0800231#define CONFIG_DIMM_SLOTS_PER_CTLR 2
232#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
233#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800234#define CONFIG_DDR_SPD
235#define CONFIG_SYS_FSL_DDR3
York Suned9e4e42014-10-27 11:31:32 -0700236#define CONFIG_FSL_DDR_INTERACTIVE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800237#define CONFIG_SYS_SPD_BUS_NUM 0
238#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
239#define SPD_EEPROM_ADDRESS1 0x51
240#define SPD_EEPROM_ADDRESS2 0x52
241#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
242#define CTRL_INTLV_PREFERED cacheline
243
244/*
245 * IFC Definitions
246 */
247#define CONFIG_SYS_FLASH_BASE 0xe0000000
248#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
249#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
250#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
251 + 0x8000000) | \
252 CSPR_PORT_SIZE_16 | \
253 CSPR_MSEL_NOR | \
254 CSPR_V)
255#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
256#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
257 CSPR_PORT_SIZE_16 | \
258 CSPR_MSEL_NOR | \
259 CSPR_V)
260#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
261/* NOR Flash Timing Params */
262#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
263
264#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
265 FTIM0_NOR_TEADC(0x5) | \
266 FTIM0_NOR_TEAHC(0x5))
267#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
268 FTIM1_NOR_TRAD_NOR(0x1A) |\
269 FTIM1_NOR_TSEQRAD_NOR(0x13))
270#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
271 FTIM2_NOR_TCH(0x4) | \
272 FTIM2_NOR_TWPH(0x0E) | \
273 FTIM2_NOR_TWP(0x1c))
274#define CONFIG_SYS_NOR_FTIM3 0x0
275
276#define CONFIG_SYS_FLASH_QUIET_TEST
277#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
278
279#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
280#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
281#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
282#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
283
284#define CONFIG_SYS_FLASH_EMPTY_INFO
285#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
286 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
287
288#define CONFIG_FSL_QIXIS /* use common QIXIS code */
289#define QIXIS_BASE 0xffdf0000
290#define QIXIS_LBMAP_SWITCH 6
291#define QIXIS_LBMAP_MASK 0x0f
292#define QIXIS_LBMAP_SHIFT 0
293#define QIXIS_LBMAP_DFLTBANK 0x00
294#define QIXIS_LBMAP_ALTBANK 0x04
295#define QIXIS_RST_CTL_RESET 0x83
296#define QIXIS_RST_FORCE_MEM 0x1
297#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
298#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
299#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
300#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
301
302#define CONFIG_SYS_CSPR3_EXT (0xf)
303#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
304 | CSPR_PORT_SIZE_8 \
305 | CSPR_MSEL_GPCM \
306 | CSPR_V)
307#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
308#define CONFIG_SYS_CSOR3 0x0
309/* QIXIS Timing parameters for IFC CS3 */
310#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
311 FTIM0_GPCM_TEADC(0x0e) | \
312 FTIM0_GPCM_TEAHC(0x0e))
313#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
314 FTIM1_GPCM_TRAD(0x3f))
315#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shengzhou Liu6b7679c2014-03-06 15:07:39 +0800316 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800317 FTIM2_GPCM_TWP(0x1f))
318#define CONFIG_SYS_CS3_FTIM3 0x0
319
320/* NAND Flash on IFC */
321#define CONFIG_NAND_FSL_IFC
322#define CONFIG_SYS_NAND_BASE 0xff800000
323#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
324
325#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
326#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
327 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
328 | CSPR_MSEL_NAND /* MSEL = NAND */ \
329 | CSPR_V)
330#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
331
332#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
333 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
334 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
335 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
336 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
337 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
338 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
339
340#define CONFIG_SYS_NAND_ONFI_DETECTION
341
342/* ONFI NAND Flash mode0 Timing Params */
343#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
344 FTIM0_NAND_TWP(0x18) | \
345 FTIM0_NAND_TWCHT(0x07) | \
346 FTIM0_NAND_TWH(0x0a))
347#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
348 FTIM1_NAND_TWBE(0x39) | \
349 FTIM1_NAND_TRR(0x0e) | \
350 FTIM1_NAND_TRP(0x18))
351#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
352 FTIM2_NAND_TREH(0x0a) | \
353 FTIM2_NAND_TWHRE(0x1e))
354#define CONFIG_SYS_NAND_FTIM3 0x0
355
356#define CONFIG_SYS_NAND_DDR_LAW 11
357#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
358#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800359#define CONFIG_CMD_NAND
360#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
361
362#if defined(CONFIG_NAND)
363#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
364#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
365#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
366#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
367#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
368#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
369#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
370#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800371#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
372#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
373#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
374#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
375#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
376#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
377#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
378#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
379#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
380#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800381#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
382#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
383#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
384#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
385#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
386#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
387#else
388#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
389#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
390#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
391#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
392#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
393#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
394#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
395#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800396#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
397#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
398#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
399#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
400#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
401#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
402#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
403#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800404#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
405#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
406#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
407#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
408#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
409#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
410#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
411#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
412#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800413
414#if defined(CONFIG_RAMBOOT_PBL)
415#define CONFIG_SYS_RAMBOOT
416#endif
417
Shengzhou Liub19e2882014-04-18 16:43:39 +0800418#ifdef CONFIG_SPL_BUILD
419#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
420#else
421#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
422#endif
423
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800424#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
425#define CONFIG_MISC_INIT_R
426#define CONFIG_HWCONFIG
427
428/* define to use L1 as initial stack */
429#define CONFIG_L1_INIT_RAM
430#define CONFIG_SYS_INIT_RAM_LOCK
431#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
432#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
433#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
434/* The assembler doesn't like typecast */
435#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
436 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
437 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
438#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
439#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
440 GENERATED_GBL_DATA_SIZE)
441#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530442#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800443#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
444
445/*
446 * Serial Port
447 */
448#define CONFIG_CONS_INDEX 1
449#define CONFIG_SYS_NS16550
450#define CONFIG_SYS_NS16550_SERIAL
451#define CONFIG_SYS_NS16550_REG_SIZE 1
452#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
453#define CONFIG_SYS_BAUDRATE_TABLE \
454 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
455#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
456#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
457#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
458#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
459
460/* Use the HUSH parser */
461#define CONFIG_SYS_HUSH_PARSER
462#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
463
464/* pass open firmware flat tree */
465#define CONFIG_OF_LIBFDT
466#define CONFIG_OF_BOARD_SETUP
467#define CONFIG_OF_STDOUT_VIA_ALIAS
468
469/* new uImage format support */
470#define CONFIG_FIT
471#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
472
473/*
474 * I2C
475 */
476#define CONFIG_SYS_I2C
477#define CONFIG_SYS_I2C_FSL
478#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
479#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
480#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
481#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
482#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
483#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
484#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
485#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
486#define CONFIG_SYS_FSL_I2C_SPEED 100000
487#define CONFIG_SYS_FSL_I2C2_SPEED 100000
488#define CONFIG_SYS_FSL_I2C3_SPEED 100000
489#define CONFIG_SYS_FSL_I2C4_SPEED 100000
490#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
491#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
492#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
493#define I2C_MUX_CH_DEFAULT 0x8
494
Ying Zhang3ad27372014-10-31 18:06:18 +0800495#define I2C_MUX_CH_VOL_MONITOR 0xa
496
497/* Voltage monitor on channel 2*/
498#define I2C_VOL_MONITOR_ADDR 0x40
499#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
500#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
501#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
502
503#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
504#ifndef CONFIG_SPL_BUILD
505#define CONFIG_VID
506#endif
507#define CONFIG_VOL_MONITOR_IR36021_SET
508#define CONFIG_VOL_MONITOR_IR36021_READ
509/* The lowest and highest voltage allowed for T208xQDS */
510#define VDD_MV_MIN 819
511#define VDD_MV_MAX 1212
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800512
513/*
514 * RapidIO
515 */
516#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
517#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
518#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
519#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
520#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
521#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
522/*
523 * for slave u-boot IMAGE instored in master memory space,
524 * PHYS must be aligned based on the SIZE
525 */
Liu Gange4911812014-05-15 14:30:34 +0800526#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
527#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
528#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
529#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800530/*
531 * for slave UCODE and ENV instored in master memory space,
532 * PHYS must be aligned based on the SIZE
533 */
Liu Gange4911812014-05-15 14:30:34 +0800534#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800535#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
536#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
537
538/* slave core release by master*/
539#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
540#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
541
542/*
543 * SRIO_PCIE_BOOT - SLAVE
544 */
545#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
546#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
547#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
548 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
549#endif
550
551/*
552 * eSPI - Enhanced SPI
553 */
554#ifdef CONFIG_SPI_FLASH
555#define CONFIG_FSL_ESPI
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800556#define CONFIG_SPI_FLASH_STMICRO
Shengzhou Liu09c20462014-05-21 13:26:17 +0800557#ifndef CONFIG_SPL_BUILD
Shengzhou Liub19e2882014-04-18 16:43:39 +0800558#define CONFIG_SPI_FLASH_SST
Shengzhou Liu254887a2014-02-21 13:16:19 +0800559#define CONFIG_SPI_FLASH_EON
560#endif
561
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800562#define CONFIG_CMD_SF
Shengzhou Liub19e2882014-04-18 16:43:39 +0800563#define CONFIG_SPI_FLASH_BAR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800564#define CONFIG_SF_DEFAULT_SPEED 10000000
565#define CONFIG_SF_DEFAULT_MODE 0
566#endif
567
568/*
569 * General PCI
570 * Memory space is mapped 1-1, but I/O space must start from 0.
571 */
572#define CONFIG_PCI /* Enable PCI/PCIE */
573#define CONFIG_PCIE1 /* PCIE controler 1 */
574#define CONFIG_PCIE2 /* PCIE controler 2 */
575#define CONFIG_PCIE3 /* PCIE controler 3 */
576#define CONFIG_PCIE4 /* PCIE controler 4 */
Zhao Qiang5066e622015-03-26 16:13:09 +0800577#define CONFIG_FSL_PCIE_RESET
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800578#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
579#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
580/* controller 1, direct to uli, tgtid 3, Base address 20000 */
581#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
582#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
583#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
584#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
585#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
586#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
587#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
588#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
589
590/* controller 2, Slot 2, tgtid 2, Base address 201000 */
591#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
592#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
593#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
594#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
595#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
596#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
597#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
598#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
599
600/* controller 3, Slot 1, tgtid 1, Base address 202000 */
601#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
602#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
603#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
604#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
605#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
606#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
607#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
608#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
609
610/* controller 4, Base address 203000 */
611#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
612#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
613#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
614#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
615#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
616#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
617#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
618
619#ifdef CONFIG_PCI
620#define CONFIG_PCI_INDIRECT_BRIDGE
Shengzhou Liu254887a2014-02-21 13:16:19 +0800621#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800622#define CONFIG_E1000
623#define CONFIG_PCI_PNP /* do pci plug-and-play */
624#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
625#define CONFIG_DOS_PARTITION
626#endif
627
628/* Qman/Bman */
629#ifndef CONFIG_NOBQFMAN
630#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
631#define CONFIG_SYS_BMAN_NUM_PORTALS 18
632#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
633#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
634#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500635#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
636#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
637#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
638#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
639#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
640 CONFIG_SYS_BMAN_CENA_SIZE)
641#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
642#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800643#define CONFIG_SYS_QMAN_NUM_PORTALS 18
644#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
645#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
646#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500647#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
648#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
649#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
650#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
651#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
652 CONFIG_SYS_QMAN_CENA_SIZE)
653#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
654#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800655
656#define CONFIG_SYS_DPAA_FMAN
657#define CONFIG_SYS_DPAA_PME
658#define CONFIG_SYS_PMAN
659#define CONFIG_SYS_DPAA_DCE
660#define CONFIG_SYS_DPAA_RMAN /* RMan */
661#define CONFIG_SYS_INTERLAKEN
662
663/* Default address of microcode for the Linux Fman driver */
664#if defined(CONFIG_SPIFLASH)
665/*
666 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
667 * env, so we got 0x110000.
668 */
669#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800670#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800671#elif defined(CONFIG_SDCARD)
672/*
673 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liub19e2882014-04-18 16:43:39 +0800674 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
675 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800676 */
677#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liub19e2882014-04-18 16:43:39 +0800678#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800679#elif defined(CONFIG_NAND)
680#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800681#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800682#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
683/*
684 * Slave has no ucode locally, it can fetch this from remote. When implementing
685 * in two corenet boards, slave's ucode could be stored in master's memory
686 * space, the address can be mapped from slave TLB->slave LAW->
687 * slave SRIO or PCIE outbound window->master inbound window->
688 * master LAW->the ucode address in master's memory space.
689 */
690#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800691#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800692#else
693#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800694#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800695#endif
696#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
697#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
698#endif /* CONFIG_NOBQFMAN */
699
700#ifdef CONFIG_SYS_DPAA_FMAN
701#define CONFIG_FMAN_ENET
702#define CONFIG_PHYLIB_10G
703#define CONFIG_PHY_VITESSE
704#define CONFIG_PHY_REALTEK
705#define CONFIG_PHY_TERANETICS
706#define RGMII_PHY1_ADDR 0x1
707#define RGMII_PHY2_ADDR 0x2
708#define FM1_10GEC1_PHY_ADDR 0x3
709#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
710#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
711#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
712#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
713#endif
714
715#ifdef CONFIG_FMAN_ENET
716#define CONFIG_MII /* MII PHY management */
717#define CONFIG_ETHPRIME "FM1@DTSEC3"
718#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
719#endif
720
721/*
722 * SATA
723 */
724#ifdef CONFIG_FSL_SATA_V2
725#define CONFIG_LIBATA
726#define CONFIG_FSL_SATA
727#define CONFIG_SYS_SATA_MAX_DEVICE 2
728#define CONFIG_SATA1
729#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
730#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
731#define CONFIG_SATA2
732#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
733#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
734#define CONFIG_LBA48
735#define CONFIG_CMD_SATA
736#define CONFIG_DOS_PARTITION
737#define CONFIG_CMD_EXT2
738#endif
739
740/*
741 * USB
742 */
743#ifdef CONFIG_USB_EHCI
744#define CONFIG_CMD_USB
745#define CONFIG_USB_STORAGE
746#define CONFIG_USB_EHCI_FSL
747#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
748#define CONFIG_CMD_EXT2
749#define CONFIG_HAS_FSL_DR_USB
750#endif
751
752/*
753 * SDHC
754 */
755#ifdef CONFIG_MMC
756#define CONFIG_CMD_MMC
757#define CONFIG_FSL_ESDHC
Yangbo Lu3285e6c2015-04-22 13:57:56 +0800758#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800759#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
760#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
761#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
762#define CONFIG_GENERIC_MMC
763#define CONFIG_CMD_EXT2
764#define CONFIG_CMD_FAT
765#define CONFIG_DOS_PARTITION
Yangbo Lub46cf1b2015-04-22 13:57:21 +0800766#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800767#endif
768
Shengzhou Liu9941cf72014-04-02 14:28:34 +0800769
770/*
771 * Dynamic MTD Partition support with mtdparts
772 */
773#ifndef CONFIG_SYS_NO_FLASH
774#define CONFIG_MTD_DEVICE
775#define CONFIG_MTD_PARTITIONS
776#define CONFIG_CMD_MTDPARTS
777#define CONFIG_FLASH_CFI_MTD
778#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
779 "spi0=spife110000.0"
780#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
781 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
782 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
783 "1m(uboot),5m(kernel),128k(dtb),-(user)"
784#endif
785
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800786/*
787 * Environment
788 */
789#define CONFIG_LOADS_ECHO /* echo on for serial download */
790#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
791
792/*
793 * Command line configuration.
794 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800795#define CONFIG_CMD_DHCP
796#define CONFIG_CMD_ELF
797#define CONFIG_CMD_ERRATA
798#define CONFIG_CMD_GREPENV
799#define CONFIG_CMD_IRQ
800#define CONFIG_CMD_I2C
801#define CONFIG_CMD_MII
802#define CONFIG_CMD_PING
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800803#define CONFIG_CMD_REGINFO
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800804
805#ifdef CONFIG_PCI
806#define CONFIG_CMD_PCI
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800807#endif
808
Ruchika Gupta737537e2014-10-15 11:35:31 +0530809/* Hash command with SHA acceleration supported in hardware */
810#ifdef CONFIG_FSL_CAAM
811#define CONFIG_CMD_HASH
812#define CONFIG_SHA_HW_ACCEL
813#endif
814
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800815/*
816 * Miscellaneous configurable options
817 */
818#define CONFIG_SYS_LONGHELP /* undef to save memory */
819#define CONFIG_CMDLINE_EDITING /* Command-line editing */
820#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
821#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800822#ifdef CONFIG_CMD_KGDB
823#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
824#else
825#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
826#endif
827#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
828#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
829#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800830
831/*
832 * For booting Linux, the board info and command line data
833 * have to be in the first 64 MB of memory, since this is
834 * the maximum mapped by the Linux kernel during initialization.
835 */
836#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
837#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
838
839#ifdef CONFIG_CMD_KGDB
840#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
841#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
842#endif
843
844/*
845 * Environment Configuration
846 */
847#define CONFIG_ROOTPATH "/opt/nfsroot"
848#define CONFIG_BOOTFILE "uImage"
849#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
850
851/* default location for tftp and bootm */
852#define CONFIG_LOADADDR 1000000
853#define CONFIG_BAUDRATE 115200
854#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
855#define __USB_PHY_TYPE utmi
856
857#define CONFIG_EXTRA_ENV_SETTINGS \
858 "hwconfig=fsl_ddr:" \
859 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
860 "bank_intlv=auto;" \
861 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
862 "netdev=eth0\0" \
863 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
864 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
865 "tftpflash=tftpboot $loadaddr $uboot && " \
866 "protect off $ubootaddr +$filesize && " \
867 "erase $ubootaddr +$filesize && " \
868 "cp.b $loadaddr $ubootaddr $filesize && " \
869 "protect on $ubootaddr +$filesize && " \
870 "cmp.b $loadaddr $ubootaddr $filesize\0" \
871 "consoledev=ttyS0\0" \
872 "ramdiskaddr=2000000\0" \
873 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
874 "fdtaddr=c00000\0" \
875 "fdtfile=t2080qds/t2080qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500876 "bdev=sda3\0"
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800877
878/*
879 * For emulation this causes u-boot to jump to the start of the
880 * proof point app code automatically
881 */
882#define CONFIG_PROOF_POINTS \
883 "setenv bootargs root=/dev/$bdev rw " \
884 "console=$consoledev,$baudrate $othbootargs;" \
885 "cpu 1 release 0x29000000 - - -;" \
886 "cpu 2 release 0x29000000 - - -;" \
887 "cpu 3 release 0x29000000 - - -;" \
888 "cpu 4 release 0x29000000 - - -;" \
889 "cpu 5 release 0x29000000 - - -;" \
890 "cpu 6 release 0x29000000 - - -;" \
891 "cpu 7 release 0x29000000 - - -;" \
892 "go 0x29000000"
893
894#define CONFIG_HVBOOT \
895 "setenv bootargs config-addr=0x60000000; " \
896 "bootm 0x01000000 - 0x00f00000"
897
898#define CONFIG_ALU \
899 "setenv bootargs root=/dev/$bdev rw " \
900 "console=$consoledev,$baudrate $othbootargs;" \
901 "cpu 1 release 0x01000000 - - -;" \
902 "cpu 2 release 0x01000000 - - -;" \
903 "cpu 3 release 0x01000000 - - -;" \
904 "cpu 4 release 0x01000000 - - -;" \
905 "cpu 5 release 0x01000000 - - -;" \
906 "cpu 6 release 0x01000000 - - -;" \
907 "cpu 7 release 0x01000000 - - -;" \
908 "go 0x01000000"
909
910#define CONFIG_LINUX \
911 "setenv bootargs root=/dev/ram rw " \
912 "console=$consoledev,$baudrate $othbootargs;" \
913 "setenv ramdiskaddr 0x02000000;" \
914 "setenv fdtaddr 0x00c00000;" \
915 "setenv loadaddr 0x1000000;" \
916 "bootm $loadaddr $ramdiskaddr $fdtaddr"
917
918#define CONFIG_HDBOOT \
919 "setenv bootargs root=/dev/$bdev rw " \
920 "console=$consoledev,$baudrate $othbootargs;" \
921 "tftp $loadaddr $bootfile;" \
922 "tftp $fdtaddr $fdtfile;" \
923 "bootm $loadaddr - $fdtaddr"
924
925#define CONFIG_NFSBOOTCOMMAND \
926 "setenv bootargs root=/dev/nfs rw " \
927 "nfsroot=$serverip:$rootpath " \
928 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
929 "console=$consoledev,$baudrate $othbootargs;" \
930 "tftp $loadaddr $bootfile;" \
931 "tftp $fdtaddr $fdtfile;" \
932 "bootm $loadaddr - $fdtaddr"
933
934#define CONFIG_RAMBOOTCOMMAND \
935 "setenv bootargs root=/dev/ram rw " \
936 "console=$consoledev,$baudrate $othbootargs;" \
937 "tftp $ramdiskaddr $ramdiskfile;" \
938 "tftp $loadaddr $bootfile;" \
939 "tftp $fdtaddr $fdtfile;" \
940 "bootm $loadaddr $ramdiskaddr $fdtaddr"
941
942#define CONFIG_BOOTCOMMAND CONFIG_LINUX
943
944#ifdef CONFIG_SECURE_BOOT
945#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530946#define CONFIG_CMD_BLOB
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800947#undef CONFIG_CMD_USB
948#endif
949
Shengzhou Liu254887a2014-02-21 13:16:19 +0800950#endif /* __T208xQDS_H */