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Shengzhou Liuc4d0e812013-11-22 17:39:11 +08001/*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
Shengzhou Liu254887a2014-02-21 13:16:19 +08008 * T2080/T2081 QDS board configuration file
Shengzhou Liuc4d0e812013-11-22 17:39:11 +08009 */
10
Shengzhou Liu254887a2014-02-21 13:16:19 +080011#ifndef __T208xQDS_H
12#define __T208xQDS_H
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080013
Shengzhou Liufb536872014-07-23 15:54:16 +080014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080016#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17#define CONFIG_MMC
18#define CONFIG_SPI_FLASH
19#define CONFIG_USB_EHCI
Shengzhou Liu254887a2014-02-21 13:16:19 +080020#if defined(CONFIG_PPC_T2080)
21#define CONFIG_T2080QDS
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080022#define CONFIG_FSL_SATA_V2
23#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
24#define CONFIG_SRIO1 /* SRIO port 1 */
25#define CONFIG_SRIO2 /* SRIO port 2 */
Shengzhou Liu254887a2014-02-21 13:16:19 +080026#elif defined(CONFIG_PPC_T2081)
27#define CONFIG_T2081QDS
28#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080029
30/* High Level Configuration Options */
31#define CONFIG_PHYS_64BIT
32#define CONFIG_BOOKE
33#define CONFIG_E500 /* BOOKE e500 family */
34#define CONFIG_E500MC /* BOOKE e500mc family */
35#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080036#define CONFIG_MP /* support multiple processors */
37#define CONFIG_ENABLE_36BIT_PHYS
38
39#ifdef CONFIG_PHYS_64BIT
40#define CONFIG_ADDR_MAP 1
41#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
42#endif
43
44#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
46#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053047#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080048#define CONFIG_FSL_LAW /* Use common FSL init code */
49#define CONFIG_ENV_OVERWRITE
50
51#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090052#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080053#if defined(CONFIG_PPC_T2080)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090054#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080055#elif defined(CONFIG_PPC_T2081)
Masahiro Yamadae4536f82014-03-11 11:05:16 +090056#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
Shengzhou Liu254887a2014-02-21 13:16:19 +080057#endif
Shengzhou Liub19e2882014-04-18 16:43:39 +080058
Shengzhou Liub19e2882014-04-18 16:43:39 +080059#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60#define CONFIG_SPL_ENV_SUPPORT
61#define CONFIG_SPL_SERIAL_SUPPORT
62#define CONFIG_SPL_FLUSH_IMAGE
63#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
64#define CONFIG_SPL_LIBGENERIC_SUPPORT
65#define CONFIG_SPL_LIBCOMMON_SUPPORT
66#define CONFIG_SPL_I2C_SUPPORT
67#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
68#define CONFIG_FSL_LAW /* Use common FSL init code */
69#define CONFIG_SYS_TEXT_BASE 0x00201000
70#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
71#define CONFIG_SPL_PAD_TO 0x40000
72#define CONFIG_SPL_MAX_SIZE 0x28000
73#define RESET_VECTOR_OFFSET 0x27FFC
74#define BOOT_PAGE_OFFSET 0x27000
75#ifdef CONFIG_SPL_BUILD
76#define CONFIG_SPL_SKIP_RELOCATE
77#define CONFIG_SPL_COMMON_INIT_DDR
78#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
79#define CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080080#endif
81
Shengzhou Liub19e2882014-04-18 16:43:39 +080082#ifdef CONFIG_NAND
83#define CONFIG_SPL_NAND_SUPPORT
84#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
85#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
86#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
87#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
88#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
89#define CONFIG_SPL_NAND_BOOT
90#endif
91
92#ifdef CONFIG_SPIFLASH
93#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
94#define CONFIG_SPL_SPI_SUPPORT
95#define CONFIG_SPL_SPI_FLASH_SUPPORT
96#define CONFIG_SPL_SPI_FLASH_MINIMAL
97#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
98#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
99#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
100#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
101#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
102#ifndef CONFIG_SPL_BUILD
103#define CONFIG_SYS_MPC85XX_NO_RESETVEC
104#endif
105#define CONFIG_SPL_SPI_BOOT
106#endif
107
108#ifdef CONFIG_SDCARD
109#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
110#define CONFIG_SPL_MMC_SUPPORT
111#define CONFIG_SPL_MMC_MINIMAL
112#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
113#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
114#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
115#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
116#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
117#ifndef CONFIG_SPL_BUILD
118#define CONFIG_SYS_MPC85XX_NO_RESETVEC
119#endif
120#define CONFIG_SPL_MMC_BOOT
121#endif
122
123#endif /* CONFIG_RAMBOOT_PBL */
124
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800125#define CONFIG_SRIO_PCIE_BOOT_MASTER
126#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
127/* Set 1M boot space */
128#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
129#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
130 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
131#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
132#define CONFIG_SYS_NO_FLASH
133#endif
134
135#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530136#define CONFIG_SYS_TEXT_BASE 0xeff40000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800137#endif
138
139#ifndef CONFIG_RESET_VECTOR_ADDRESS
140#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
141#endif
142
143/*
144 * These can be toggled for performance analysis, otherwise use default.
145 */
146#define CONFIG_SYS_CACHE_STASHING
147#define CONFIG_BTB /* toggle branch predition */
148#define CONFIG_DDR_ECC
149#ifdef CONFIG_DDR_ECC
150#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
151#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
152#endif
153
Shengzhou Liub19e2882014-04-18 16:43:39 +0800154#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800155#define CONFIG_FLASH_CFI_DRIVER
156#define CONFIG_SYS_FLASH_CFI
157#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
158#endif
159
160#if defined(CONFIG_SPIFLASH)
161#define CONFIG_SYS_EXTRA_ENV_RELOC
162#define CONFIG_ENV_IS_IN_SPI_FLASH
163#define CONFIG_ENV_SPI_BUS 0
164#define CONFIG_ENV_SPI_CS 0
165#define CONFIG_ENV_SPI_MAX_HZ 10000000
166#define CONFIG_ENV_SPI_MODE 0
167#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
168#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
169#define CONFIG_ENV_SECT_SIZE 0x10000
170#elif defined(CONFIG_SDCARD)
171#define CONFIG_SYS_EXTRA_ENV_RELOC
172#define CONFIG_ENV_IS_IN_MMC
173#define CONFIG_SYS_MMC_ENV_DEV 0
174#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liub19e2882014-04-18 16:43:39 +0800175#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800176#elif defined(CONFIG_NAND)
177#define CONFIG_SYS_EXTRA_ENV_RELOC
178#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800179#define CONFIG_ENV_SIZE 0x2000
180#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800181#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
182#define CONFIG_ENV_IS_IN_REMOTE
183#define CONFIG_ENV_ADDR 0xffe20000
184#define CONFIG_ENV_SIZE 0x2000
185#elif defined(CONFIG_ENV_IS_NOWHERE)
186#define CONFIG_ENV_SIZE 0x2000
187#else
188#define CONFIG_ENV_IS_IN_FLASH
189#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
190#define CONFIG_ENV_SIZE 0x2000
191#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
192#endif
193
194#ifndef __ASSEMBLY__
195unsigned long get_board_sys_clk(void);
196unsigned long get_board_ddr_clk(void);
197#endif
198
199#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
200#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
201
202/*
203 * Config the L3 Cache as L3 SRAM
204 */
Shengzhou Liub19e2882014-04-18 16:43:39 +0800205#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
206#define CONFIG_SYS_L3_SIZE (512 << 10)
207#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
208#ifdef CONFIG_RAMBOOT_PBL
209#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
210#endif
211#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
212#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
213#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
214#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800215
216#define CONFIG_SYS_DCSRBAR 0xf0000000
217#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
218
219/* EEPROM */
220#define CONFIG_ID_EEPROM
221#define CONFIG_SYS_I2C_EEPROM_NXID
222#define CONFIG_SYS_EEPROM_BUS_NUM 0
223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
224#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
225
226/*
227 * DDR Setup
228 */
229#define CONFIG_VERY_BIG_RAM
230#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
231#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liu40483e12014-05-20 12:08:20 +0800232#define CONFIG_DIMM_SLOTS_PER_CTLR 2
233#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
234#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800235#define CONFIG_DDR_SPD
236#define CONFIG_SYS_FSL_DDR3
York Suned9e4e42014-10-27 11:31:32 -0700237#define CONFIG_FSL_DDR_INTERACTIVE
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800238#define CONFIG_SYS_SPD_BUS_NUM 0
239#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
240#define SPD_EEPROM_ADDRESS1 0x51
241#define SPD_EEPROM_ADDRESS2 0x52
242#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
243#define CTRL_INTLV_PREFERED cacheline
244
245/*
246 * IFC Definitions
247 */
248#define CONFIG_SYS_FLASH_BASE 0xe0000000
249#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
250#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
251#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
252 + 0x8000000) | \
253 CSPR_PORT_SIZE_16 | \
254 CSPR_MSEL_NOR | \
255 CSPR_V)
256#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
257#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
258 CSPR_PORT_SIZE_16 | \
259 CSPR_MSEL_NOR | \
260 CSPR_V)
261#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
262/* NOR Flash Timing Params */
263#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
264
265#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
266 FTIM0_NOR_TEADC(0x5) | \
267 FTIM0_NOR_TEAHC(0x5))
268#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
269 FTIM1_NOR_TRAD_NOR(0x1A) |\
270 FTIM1_NOR_TSEQRAD_NOR(0x13))
271#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
272 FTIM2_NOR_TCH(0x4) | \
273 FTIM2_NOR_TWPH(0x0E) | \
274 FTIM2_NOR_TWP(0x1c))
275#define CONFIG_SYS_NOR_FTIM3 0x0
276
277#define CONFIG_SYS_FLASH_QUIET_TEST
278#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
279
280#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
281#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
282#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
283#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
284
285#define CONFIG_SYS_FLASH_EMPTY_INFO
286#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
287 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
288
289#define CONFIG_FSL_QIXIS /* use common QIXIS code */
290#define QIXIS_BASE 0xffdf0000
291#define QIXIS_LBMAP_SWITCH 6
292#define QIXIS_LBMAP_MASK 0x0f
293#define QIXIS_LBMAP_SHIFT 0
294#define QIXIS_LBMAP_DFLTBANK 0x00
295#define QIXIS_LBMAP_ALTBANK 0x04
296#define QIXIS_RST_CTL_RESET 0x83
297#define QIXIS_RST_FORCE_MEM 0x1
298#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
299#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
300#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
301#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
302
303#define CONFIG_SYS_CSPR3_EXT (0xf)
304#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
305 | CSPR_PORT_SIZE_8 \
306 | CSPR_MSEL_GPCM \
307 | CSPR_V)
308#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
309#define CONFIG_SYS_CSOR3 0x0
310/* QIXIS Timing parameters for IFC CS3 */
311#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
312 FTIM0_GPCM_TEADC(0x0e) | \
313 FTIM0_GPCM_TEAHC(0x0e))
314#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
315 FTIM1_GPCM_TRAD(0x3f))
316#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shengzhou Liu6b7679c2014-03-06 15:07:39 +0800317 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800318 FTIM2_GPCM_TWP(0x1f))
319#define CONFIG_SYS_CS3_FTIM3 0x0
320
321/* NAND Flash on IFC */
322#define CONFIG_NAND_FSL_IFC
323#define CONFIG_SYS_NAND_BASE 0xff800000
324#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
325
326#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
327#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
328 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
329 | CSPR_MSEL_NAND /* MSEL = NAND */ \
330 | CSPR_V)
331#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
332
333#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
334 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
335 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
336 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
337 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
338 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
339 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
340
341#define CONFIG_SYS_NAND_ONFI_DETECTION
342
343/* ONFI NAND Flash mode0 Timing Params */
344#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
345 FTIM0_NAND_TWP(0x18) | \
346 FTIM0_NAND_TWCHT(0x07) | \
347 FTIM0_NAND_TWH(0x0a))
348#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
349 FTIM1_NAND_TWBE(0x39) | \
350 FTIM1_NAND_TRR(0x0e) | \
351 FTIM1_NAND_TRP(0x18))
352#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
353 FTIM2_NAND_TREH(0x0a) | \
354 FTIM2_NAND_TWHRE(0x1e))
355#define CONFIG_SYS_NAND_FTIM3 0x0
356
357#define CONFIG_SYS_NAND_DDR_LAW 11
358#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
359#define CONFIG_SYS_MAX_NAND_DEVICE 1
360#define CONFIG_MTD_NAND_VERIFY_WRITE
361#define CONFIG_CMD_NAND
362#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
363
364#if defined(CONFIG_NAND)
365#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
366#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
367#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
368#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
369#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
370#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
371#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
372#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800373#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
374#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
375#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
376#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
377#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
378#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
379#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
380#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
381#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
382#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800383#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
384#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
385#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
386#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
387#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
388#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
389#else
390#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
391#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
392#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
393#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
394#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
395#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
396#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
397#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liu22cbf962014-03-13 10:19:00 +0800398#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
399#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
400#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
401#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
402#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
403#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
404#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
405#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800406#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
407#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
408#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
409#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
410#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
411#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
412#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
413#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
414#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800415
416#if defined(CONFIG_RAMBOOT_PBL)
417#define CONFIG_SYS_RAMBOOT
418#endif
419
Shengzhou Liub19e2882014-04-18 16:43:39 +0800420#ifdef CONFIG_SPL_BUILD
421#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
422#else
423#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
424#endif
425
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800426#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
427#define CONFIG_MISC_INIT_R
428#define CONFIG_HWCONFIG
429
430/* define to use L1 as initial stack */
431#define CONFIG_L1_INIT_RAM
432#define CONFIG_SYS_INIT_RAM_LOCK
433#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
434#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
435#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
436/* The assembler doesn't like typecast */
437#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
438 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
439 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
440#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
441#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
442 GENERATED_GBL_DATA_SIZE)
443#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530444#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800445#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
446
447/*
448 * Serial Port
449 */
450#define CONFIG_CONS_INDEX 1
451#define CONFIG_SYS_NS16550
452#define CONFIG_SYS_NS16550_SERIAL
453#define CONFIG_SYS_NS16550_REG_SIZE 1
454#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
455#define CONFIG_SYS_BAUDRATE_TABLE \
456 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
457#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
458#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
459#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
460#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
461
462/* Use the HUSH parser */
463#define CONFIG_SYS_HUSH_PARSER
464#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
465
466/* pass open firmware flat tree */
467#define CONFIG_OF_LIBFDT
468#define CONFIG_OF_BOARD_SETUP
469#define CONFIG_OF_STDOUT_VIA_ALIAS
470
471/* new uImage format support */
472#define CONFIG_FIT
473#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
474
475/*
476 * I2C
477 */
478#define CONFIG_SYS_I2C
479#define CONFIG_SYS_I2C_FSL
480#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
481#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
482#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
483#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
484#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
485#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
486#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
487#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
488#define CONFIG_SYS_FSL_I2C_SPEED 100000
489#define CONFIG_SYS_FSL_I2C2_SPEED 100000
490#define CONFIG_SYS_FSL_I2C3_SPEED 100000
491#define CONFIG_SYS_FSL_I2C4_SPEED 100000
492#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
493#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
494#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
495#define I2C_MUX_CH_DEFAULT 0x8
496
Ying Zhang3ad27372014-10-31 18:06:18 +0800497#define I2C_MUX_CH_VOL_MONITOR 0xa
498
499/* Voltage monitor on channel 2*/
500#define I2C_VOL_MONITOR_ADDR 0x40
501#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
502#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
503#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
504
505#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
506#ifndef CONFIG_SPL_BUILD
507#define CONFIG_VID
508#endif
509#define CONFIG_VOL_MONITOR_IR36021_SET
510#define CONFIG_VOL_MONITOR_IR36021_READ
511/* The lowest and highest voltage allowed for T208xQDS */
512#define VDD_MV_MIN 819
513#define VDD_MV_MAX 1212
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800514
515/*
516 * RapidIO
517 */
518#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
519#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
520#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
521#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
522#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
523#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
524/*
525 * for slave u-boot IMAGE instored in master memory space,
526 * PHYS must be aligned based on the SIZE
527 */
Liu Gange4911812014-05-15 14:30:34 +0800528#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
529#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
530#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
531#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800532/*
533 * for slave UCODE and ENV instored in master memory space,
534 * PHYS must be aligned based on the SIZE
535 */
Liu Gange4911812014-05-15 14:30:34 +0800536#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800537#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
538#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
539
540/* slave core release by master*/
541#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
542#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
543
544/*
545 * SRIO_PCIE_BOOT - SLAVE
546 */
547#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
548#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
549#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
550 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
551#endif
552
553/*
554 * eSPI - Enhanced SPI
555 */
556#ifdef CONFIG_SPI_FLASH
557#define CONFIG_FSL_ESPI
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800558#define CONFIG_SPI_FLASH_STMICRO
Shengzhou Liu09c20462014-05-21 13:26:17 +0800559#ifndef CONFIG_SPL_BUILD
Shengzhou Liub19e2882014-04-18 16:43:39 +0800560#define CONFIG_SPI_FLASH_SST
Shengzhou Liu254887a2014-02-21 13:16:19 +0800561#define CONFIG_SPI_FLASH_EON
562#endif
563
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800564#define CONFIG_CMD_SF
Shengzhou Liub19e2882014-04-18 16:43:39 +0800565#define CONFIG_SPI_FLASH_BAR
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800566#define CONFIG_SF_DEFAULT_SPEED 10000000
567#define CONFIG_SF_DEFAULT_MODE 0
568#endif
569
570/*
571 * General PCI
572 * Memory space is mapped 1-1, but I/O space must start from 0.
573 */
574#define CONFIG_PCI /* Enable PCI/PCIE */
575#define CONFIG_PCIE1 /* PCIE controler 1 */
576#define CONFIG_PCIE2 /* PCIE controler 2 */
577#define CONFIG_PCIE3 /* PCIE controler 3 */
578#define CONFIG_PCIE4 /* PCIE controler 4 */
579#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
580#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
581/* controller 1, direct to uli, tgtid 3, Base address 20000 */
582#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
583#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
584#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
585#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
586#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
587#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
588#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
589#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
590
591/* controller 2, Slot 2, tgtid 2, Base address 201000 */
592#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
593#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
594#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
595#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
596#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
597#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
598#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
599#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
600
601/* controller 3, Slot 1, tgtid 1, Base address 202000 */
602#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
603#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
604#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
605#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
606#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
607#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
608#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
609#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
610
611/* controller 4, Base address 203000 */
612#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
613#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
614#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
615#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
616#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
617#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
618#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
619
620#ifdef CONFIG_PCI
621#define CONFIG_PCI_INDIRECT_BRIDGE
Shengzhou Liu254887a2014-02-21 13:16:19 +0800622#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800623#define CONFIG_NET_MULTI
624#define CONFIG_E1000
625#define CONFIG_PCI_PNP /* do pci plug-and-play */
626#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
627#define CONFIG_DOS_PARTITION
628#endif
629
630/* Qman/Bman */
631#ifndef CONFIG_NOBQFMAN
632#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
633#define CONFIG_SYS_BMAN_NUM_PORTALS 18
634#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
635#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
636#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500637#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
638#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
639#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
640#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
641#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
642 CONFIG_SYS_BMAN_CENA_SIZE)
643#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
644#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800645#define CONFIG_SYS_QMAN_NUM_PORTALS 18
646#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
647#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
648#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500649#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
650#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
651#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
652#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
653#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
654 CONFIG_SYS_QMAN_CENA_SIZE)
655#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
656#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800657
658#define CONFIG_SYS_DPAA_FMAN
659#define CONFIG_SYS_DPAA_PME
660#define CONFIG_SYS_PMAN
661#define CONFIG_SYS_DPAA_DCE
662#define CONFIG_SYS_DPAA_RMAN /* RMan */
663#define CONFIG_SYS_INTERLAKEN
664
665/* Default address of microcode for the Linux Fman driver */
666#if defined(CONFIG_SPIFLASH)
667/*
668 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
669 * env, so we got 0x110000.
670 */
671#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800672#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800673#elif defined(CONFIG_SDCARD)
674/*
675 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liub19e2882014-04-18 16:43:39 +0800676 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
677 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800678 */
679#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liub19e2882014-04-18 16:43:39 +0800680#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800681#elif defined(CONFIG_NAND)
682#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liub19e2882014-04-18 16:43:39 +0800683#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800684#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
685/*
686 * Slave has no ucode locally, it can fetch this from remote. When implementing
687 * in two corenet boards, slave's ucode could be stored in master's memory
688 * space, the address can be mapped from slave TLB->slave LAW->
689 * slave SRIO or PCIE outbound window->master inbound window->
690 * master LAW->the ucode address in master's memory space.
691 */
692#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800693#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800694#else
695#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800696#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800697#endif
698#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
699#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
700#endif /* CONFIG_NOBQFMAN */
701
702#ifdef CONFIG_SYS_DPAA_FMAN
703#define CONFIG_FMAN_ENET
704#define CONFIG_PHYLIB_10G
705#define CONFIG_PHY_VITESSE
706#define CONFIG_PHY_REALTEK
707#define CONFIG_PHY_TERANETICS
708#define RGMII_PHY1_ADDR 0x1
709#define RGMII_PHY2_ADDR 0x2
710#define FM1_10GEC1_PHY_ADDR 0x3
711#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
712#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
713#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
714#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
715#endif
716
717#ifdef CONFIG_FMAN_ENET
718#define CONFIG_MII /* MII PHY management */
719#define CONFIG_ETHPRIME "FM1@DTSEC3"
720#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
721#endif
722
723/*
724 * SATA
725 */
726#ifdef CONFIG_FSL_SATA_V2
727#define CONFIG_LIBATA
728#define CONFIG_FSL_SATA
729#define CONFIG_SYS_SATA_MAX_DEVICE 2
730#define CONFIG_SATA1
731#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
732#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
733#define CONFIG_SATA2
734#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
735#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
736#define CONFIG_LBA48
737#define CONFIG_CMD_SATA
738#define CONFIG_DOS_PARTITION
739#define CONFIG_CMD_EXT2
740#endif
741
742/*
743 * USB
744 */
745#ifdef CONFIG_USB_EHCI
746#define CONFIG_CMD_USB
747#define CONFIG_USB_STORAGE
748#define CONFIG_USB_EHCI_FSL
749#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
750#define CONFIG_CMD_EXT2
751#define CONFIG_HAS_FSL_DR_USB
752#endif
753
754/*
755 * SDHC
756 */
757#ifdef CONFIG_MMC
758#define CONFIG_CMD_MMC
759#define CONFIG_FSL_ESDHC
760#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
761#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
762#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
763#define CONFIG_GENERIC_MMC
764#define CONFIG_CMD_EXT2
765#define CONFIG_CMD_FAT
766#define CONFIG_DOS_PARTITION
767#endif
768
Shengzhou Liu9941cf72014-04-02 14:28:34 +0800769
770/*
771 * Dynamic MTD Partition support with mtdparts
772 */
773#ifndef CONFIG_SYS_NO_FLASH
774#define CONFIG_MTD_DEVICE
775#define CONFIG_MTD_PARTITIONS
776#define CONFIG_CMD_MTDPARTS
777#define CONFIG_FLASH_CFI_MTD
778#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
779 "spi0=spife110000.0"
780#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
781 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
782 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
783 "1m(uboot),5m(kernel),128k(dtb),-(user)"
784#endif
785
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800786/*
787 * Environment
788 */
789#define CONFIG_LOADS_ECHO /* echo on for serial download */
790#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
791
792/*
793 * Command line configuration.
794 */
795#include <config_cmd_default.h>
796
797#define CONFIG_CMD_DHCP
798#define CONFIG_CMD_ELF
799#define CONFIG_CMD_ERRATA
800#define CONFIG_CMD_GREPENV
801#define CONFIG_CMD_IRQ
802#define CONFIG_CMD_I2C
803#define CONFIG_CMD_MII
804#define CONFIG_CMD_PING
805#define CONFIG_CMD_SETEXPR
806#define CONFIG_CMD_REGINFO
807#define CONFIG_CMD_BDI
808
809#ifdef CONFIG_PCI
810#define CONFIG_CMD_PCI
811#define CONFIG_CMD_NET
812#endif
813
Ruchika Gupta737537e2014-10-15 11:35:31 +0530814/* Hash command with SHA acceleration supported in hardware */
815#ifdef CONFIG_FSL_CAAM
816#define CONFIG_CMD_HASH
817#define CONFIG_SHA_HW_ACCEL
818#endif
819
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800820/*
821 * Miscellaneous configurable options
822 */
823#define CONFIG_SYS_LONGHELP /* undef to save memory */
824#define CONFIG_CMDLINE_EDITING /* Command-line editing */
825#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
826#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800827#ifdef CONFIG_CMD_KGDB
828#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
829#else
830#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
831#endif
832#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
833#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
834#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800835
836/*
837 * For booting Linux, the board info and command line data
838 * have to be in the first 64 MB of memory, since this is
839 * the maximum mapped by the Linux kernel during initialization.
840 */
841#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
842#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
843
844#ifdef CONFIG_CMD_KGDB
845#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
846#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
847#endif
848
849/*
850 * Environment Configuration
851 */
852#define CONFIG_ROOTPATH "/opt/nfsroot"
853#define CONFIG_BOOTFILE "uImage"
854#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
855
856/* default location for tftp and bootm */
857#define CONFIG_LOADADDR 1000000
858#define CONFIG_BAUDRATE 115200
859#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
860#define __USB_PHY_TYPE utmi
861
862#define CONFIG_EXTRA_ENV_SETTINGS \
863 "hwconfig=fsl_ddr:" \
864 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
865 "bank_intlv=auto;" \
866 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
867 "netdev=eth0\0" \
868 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
869 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
870 "tftpflash=tftpboot $loadaddr $uboot && " \
871 "protect off $ubootaddr +$filesize && " \
872 "erase $ubootaddr +$filesize && " \
873 "cp.b $loadaddr $ubootaddr $filesize && " \
874 "protect on $ubootaddr +$filesize && " \
875 "cmp.b $loadaddr $ubootaddr $filesize\0" \
876 "consoledev=ttyS0\0" \
877 "ramdiskaddr=2000000\0" \
878 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
879 "fdtaddr=c00000\0" \
880 "fdtfile=t2080qds/t2080qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500881 "bdev=sda3\0"
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800882
883/*
884 * For emulation this causes u-boot to jump to the start of the
885 * proof point app code automatically
886 */
887#define CONFIG_PROOF_POINTS \
888 "setenv bootargs root=/dev/$bdev rw " \
889 "console=$consoledev,$baudrate $othbootargs;" \
890 "cpu 1 release 0x29000000 - - -;" \
891 "cpu 2 release 0x29000000 - - -;" \
892 "cpu 3 release 0x29000000 - - -;" \
893 "cpu 4 release 0x29000000 - - -;" \
894 "cpu 5 release 0x29000000 - - -;" \
895 "cpu 6 release 0x29000000 - - -;" \
896 "cpu 7 release 0x29000000 - - -;" \
897 "go 0x29000000"
898
899#define CONFIG_HVBOOT \
900 "setenv bootargs config-addr=0x60000000; " \
901 "bootm 0x01000000 - 0x00f00000"
902
903#define CONFIG_ALU \
904 "setenv bootargs root=/dev/$bdev rw " \
905 "console=$consoledev,$baudrate $othbootargs;" \
906 "cpu 1 release 0x01000000 - - -;" \
907 "cpu 2 release 0x01000000 - - -;" \
908 "cpu 3 release 0x01000000 - - -;" \
909 "cpu 4 release 0x01000000 - - -;" \
910 "cpu 5 release 0x01000000 - - -;" \
911 "cpu 6 release 0x01000000 - - -;" \
912 "cpu 7 release 0x01000000 - - -;" \
913 "go 0x01000000"
914
915#define CONFIG_LINUX \
916 "setenv bootargs root=/dev/ram rw " \
917 "console=$consoledev,$baudrate $othbootargs;" \
918 "setenv ramdiskaddr 0x02000000;" \
919 "setenv fdtaddr 0x00c00000;" \
920 "setenv loadaddr 0x1000000;" \
921 "bootm $loadaddr $ramdiskaddr $fdtaddr"
922
923#define CONFIG_HDBOOT \
924 "setenv bootargs root=/dev/$bdev rw " \
925 "console=$consoledev,$baudrate $othbootargs;" \
926 "tftp $loadaddr $bootfile;" \
927 "tftp $fdtaddr $fdtfile;" \
928 "bootm $loadaddr - $fdtaddr"
929
930#define CONFIG_NFSBOOTCOMMAND \
931 "setenv bootargs root=/dev/nfs rw " \
932 "nfsroot=$serverip:$rootpath " \
933 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
934 "console=$consoledev,$baudrate $othbootargs;" \
935 "tftp $loadaddr $bootfile;" \
936 "tftp $fdtaddr $fdtfile;" \
937 "bootm $loadaddr - $fdtaddr"
938
939#define CONFIG_RAMBOOTCOMMAND \
940 "setenv bootargs root=/dev/ram rw " \
941 "console=$consoledev,$baudrate $othbootargs;" \
942 "tftp $ramdiskaddr $ramdiskfile;" \
943 "tftp $loadaddr $bootfile;" \
944 "tftp $fdtaddr $fdtfile;" \
945 "bootm $loadaddr $ramdiskaddr $fdtaddr"
946
947#define CONFIG_BOOTCOMMAND CONFIG_LINUX
948
949#ifdef CONFIG_SECURE_BOOT
950#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530951#define CONFIG_CMD_BLOB
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800952#undef CONFIG_CMD_USB
953#endif
954
Shengzhou Liu254887a2014-02-21 13:16:19 +0800955#endif /* __T208xQDS_H */