Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 2 | /* |
| 3 | * include/configs/blanche.h |
| 4 | * This file is blanche board configuration. |
| 5 | * |
| 6 | * Copyright (C) 2016 Renesas Electronics Corporation |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __BLANCHE_H |
| 10 | #define __BLANCHE_H |
| 11 | |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 12 | #include "rcar-gen2-common.h" |
| 13 | |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 14 | /* STACK */ |
Marek Vasut | e9c891f | 2018-04-30 14:10:36 +0200 | [diff] [blame] | 15 | #define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 |
| 16 | #define STACK_AREA_SIZE 0x00100000 |
| 17 | #define LOW_LEVEL_MERAM_STACK \ |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 18 | (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
| 19 | |
| 20 | /* MEMORY */ |
| 21 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 |
| 22 | #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) |
| 23 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) |
| 24 | |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 25 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
| 26 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 27 | |
| 28 | /* FLASH */ |
Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 29 | #if !defined(CONFIG_MTD_NOR_FLASH) |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 30 | #define CONFIG_SH_QSPI_BASE 0xE6B10000 |
| 31 | #else |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 32 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 33 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 34 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
| 35 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
| 36 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ |
| 37 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| 38 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 39 | #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } |
| 40 | #define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } |
| 41 | |
| 42 | #define CONFIG_SYS_FLASH_ERASE_TOUT 3000 |
| 43 | #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 |
| 44 | #define CONFIG_SYS_FLASH_LOCK_TOUT 3000 |
| 45 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 46 | #undef CONFIG_CMD_SF |
| 47 | #undef CONFIG_CMD_SPI |
| 48 | #endif |
| 49 | |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 50 | /* Board Clock */ |
| 51 | #define RMOBILE_XTAL_CLK 20000000u |
| 52 | #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 53 | |
| 54 | /* ENV setting */ |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 55 | |
masakazu.mochizuki.wd@hitachi.com | 6f107e4 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 56 | #endif /* __BLANCHE_H */ |