blob: 8ff82d3489a1560a1db8717ed3c1ef806ce0ad22 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +09002/*
3 * include/configs/blanche.h
4 * This file is blanche board configuration.
5 *
6 * Copyright (C) 2016 Renesas Electronics Corporation
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +09007 */
8
9#ifndef __BLANCHE_H
10#define __BLANCHE_H
11
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090012#include "rcar-gen2-common.h"
13
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090014/* STACK */
15#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
16#define STACK_AREA_SIZE 0xC000
17#define LOW_LEVEL_MERAM_STACK \
18 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
19
20/* MEMORY */
21#define RCAR_GEN2_SDRAM_BASE 0x40000000
22#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
23#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
24
25/* SCIF */
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090026#define CONFIG_CONS_SCIF0
27
28#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
29#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
30
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090031#undef CONFIG_SYS_MEMTEST_SCRATCH
32#undef CONFIG_SYS_LOADS_BAUD_CHANGE
33
34/* FLASH */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090035#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090036#define CONFIG_SH_QSPI_BASE 0xE6B10000
37#else
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090038#define CONFIG_SYS_FLASH_CFI
39#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
40#define CONFIG_FLASH_CFI_DRIVER
41#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
42#define CONFIG_FLASH_SHOW_PROGRESS 45
43#define CONFIG_SYS_FLASH_BASE 0x00000000
44#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
45#define CONFIG_SYS_MAX_FLASH_SECT 1024
46#define CONFIG_SYS_MAX_FLASH_BANKS 1
47#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
48#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
49
50#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
51#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
52#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
53#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090054#undef CONFIG_CMD_SF
55#undef CONFIG_CMD_SPI
56#endif
57
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090058
59/* Board Clock */
60#define RMOBILE_XTAL_CLK 20000000u
61#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
62#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
63#define CONFIG_SYS_TMU_CLK_DIV 4
64
65/* ENV setting */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090066#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090067#else
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090068#undef CONFIG_ENV_ADDR
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090069#define CONFIG_ENV_SECT_SIZE (256 * 1024)
70#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
71#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
72#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
73#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
74#endif
75
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090076/* Module stop status bits */
77/* INTC-RT */
78#define CONFIG_SMSTP0_ENA 0x00400000
79/* SDHI0 */
80#define CONFIG_SMSTP3_ENA 0x00004000
81/* INTC-SYS, IRQC */
82#define CONFIG_SMSTP4_ENA 0x00000180
83/* SCIF0 */
84#define CONFIG_SMSTP7_ENA 0x00200000
85/* QSPI */
86#define CONFIG_SMSTP9_ENA 0x00020000
87/* SYS-DMAC0 */
88#define CONFIG_RMSTP2_ENA 0x00080000
89
90/* SDHI */
91#define CONFIG_SH_SDHI_FREQ 97500000
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090092
93#endif /* __BLANCHE_H */