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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------------+ */
2/* */
Josh Boyer31773492009-08-07 13:53:20 -04003/* This source code is dual-licensed. You may use it under the terms */
4/* of the GNU General Public License version 2, or under the license */
5/* below. */
6/* */
wdenkfe8c2802002-11-03 00:38:21 +00007/* This source code has been made available to you by IBM on an AS-IS */
8/* basis. Anyone receiving this source is licensed under IBM */
9/* copyrights to use it in any way he or she deems fit, including */
10/* copying it, modifying it, compiling it, and redistributing it either */
11/* with or without modifications. No license under IBM patents or */
12/* patent applications is to be implied by the copyright license. */
13/* */
14/* Any user of this software should understand that IBM cannot provide */
15/* technical support for this software and will not be responsible for */
16/* any consequences resulting from the use of this software. */
17/* */
18/* Any person who transfers this source code or any derivative work */
19/* must include the IBM copyright notice, this paragraph, and the */
20/* preceding two paragraphs in the transferred software. */
21/* */
22/* COPYRIGHT I B M CORPORATION 1995 */
23/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
24/*------------------------------------------------------------------------------- */
25
26/*----------------------------------------------------------------------------- */
27/* Function: ext_bus_cntlr_init */
28/* Description: Initializes the External Bus Controller for the external */
29/* peripherals. IMPORTANT: For pass1 this code must run from */
30/* cache since you can not reliably change a peripheral banks */
31/* timing register (pbxap) while running code from that bank. */
32/* For ex., since we are running from ROM on bank 0, we can NOT */
33/* execute the code that modifies bank 0 timings from ROM, so */
34/* we run it from cache. */
35/* */
36/*----------------------------------------------------------------------------- */
37#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020038#include <asm/ppc4xx.h>
wdenkfe8c2802002-11-03 00:38:21 +000039
40#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
41
42#include <ppc_asm.tmpl>
43#include <ppc_defs.h>
44
45#include <asm/cache.h>
46#include <asm/mmu.h>
47
48
wdenk8bde7f72003-06-27 21:31:46 +000049 .globl ext_bus_cntlr_init
wdenkfe8c2802002-11-03 00:38:21 +000050ext_bus_cntlr_init:
wdenk8bde7f72003-06-27 21:31:46 +000051 mflr r4 /* save link register */
52 bl ..getAddr
wdenkfe8c2802002-11-03 00:38:21 +000053..getAddr:
wdenk8bde7f72003-06-27 21:31:46 +000054 mflr r3 /* get address of ..getAddr */
55 mtlr r4 /* restore link register */
56 addi r4,0,14 /* set ctr to 10; used to prefetch */
57 mtctr r4 /* 10 cache lines to fit this function */
58 /* in cache (gives us 8x10=80 instrctns) */
wdenkfe8c2802002-11-03 00:38:21 +000059..ebcloop:
wdenk8bde7f72003-06-27 21:31:46 +000060 icbt r0,r3 /* prefetch cache line for addr in r3 */
61 addi r3,r3,32 /* move to next cache line */
62 bdnz ..ebcloop /* continue for 10 cache lines */
wdenkfe8c2802002-11-03 00:38:21 +000063
wdenk8bde7f72003-06-27 21:31:46 +000064 /*------------------------------------------------------------------- */
65 /* Delay to ensure all accesses to ROM are complete before changing */
wdenkfe8c2802002-11-03 00:38:21 +000066 /* bank 0 timings. 200usec should be enough. */
wdenk8bde7f72003-06-27 21:31:46 +000067 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
68 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000069 addis r3,0,0x0
wdenk8bde7f72003-06-27 21:31:46 +000070 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
71 mtctr r3
wdenkfe8c2802002-11-03 00:38:21 +000072..spinlp:
wdenk8bde7f72003-06-27 21:31:46 +000073 bdnz ..spinlp /* spin loop */
wdenkfe8c2802002-11-03 00:38:21 +000074
wdenk8bde7f72003-06-27 21:31:46 +000075 /*----------------------------------------------------------------------- */
76 /* Memory Bank 0 (Flash) initialization (from openbios) */
77 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000078
Stefan Roesed1c3b272009-09-09 16:25:29 +020079 addi r4,0,PB1AP
80 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +000081 addis r4,0,CS0_AP@h
82 ori r4,r4,CS0_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +020083 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +000084
Stefan Roesed1c3b272009-09-09 16:25:29 +020085 addi r4,0,PB0CR
86 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +000087 addis r4,0,CS0_CR@h
88 ori r4,r4,CS0_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +020089 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +000090
wdenk8bde7f72003-06-27 21:31:46 +000091 /*----------------------------------------------------------------------- */
92 /* Memory Bank 1 (NVRAM/RTC) initialization */
93 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000094
Stefan Roesed1c3b272009-09-09 16:25:29 +020095 addi r4,0,PB1AP
96 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +000097 addis r4,0,CS1_AP@h
98 ori r4,r4,CS1_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +020099 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000100
Stefan Roesed1c3b272009-09-09 16:25:29 +0200101 addi r4,0,PB1CR
102 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000103 addis r4,0,CS1_CR@h
104 ori r4,r4,CS1_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000106
wdenk8bde7f72003-06-27 21:31:46 +0000107 /*----------------------------------------------------------------------- */
108 /* Memory Bank 2 (A/D converter) initialization */
109 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000110
Stefan Roesed1c3b272009-09-09 16:25:29 +0200111 addi r4,0,PB2AP
112 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000113 addis r4,0,CS2_AP@h
114 ori r4,r4,CS2_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200115 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000116
Stefan Roesed1c3b272009-09-09 16:25:29 +0200117 addi r4,0,PB2CR
118 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000119 addis r4,0,CS2_CR@h
120 ori r4,r4,CS2_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200121 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000122
wdenk8bde7f72003-06-27 21:31:46 +0000123 /*----------------------------------------------------------------------- */
124 /* Memory Bank 3 (Ethernet PHY Reset) initialization */
125 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000126
Stefan Roesed1c3b272009-09-09 16:25:29 +0200127 addi r4,0,PB3AP
128 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000129 addis r4,0,CS3_AP@h
130 ori r4,r4,CS3_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200131 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000132
Stefan Roesed1c3b272009-09-09 16:25:29 +0200133 addi r4,0,PB3CR
134 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000135 addis r4,0,CS3_CR@h
136 ori r4,r4,CS3_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200137 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000138
wdenk8bde7f72003-06-27 21:31:46 +0000139 /*----------------------------------------------------------------------- */
140 /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
141 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000142
Stefan Roesed1c3b272009-09-09 16:25:29 +0200143 addi r4,0,PB4AP
144 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000145 addis r4,0,CS4_AP@h
146 ori r4,r4,CS4_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200147 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000148
Stefan Roesed1c3b272009-09-09 16:25:29 +0200149 addi r4,0,PB4CR
150 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000151 addis r4,0,CS4_CR@h
152 ori r4,r4,CS4_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200153 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000154
wdenk8bde7f72003-06-27 21:31:46 +0000155 /*----------------------------------------------------------------------- */
156 /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
157 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000158
Stefan Roesed1c3b272009-09-09 16:25:29 +0200159 addi r4,0,PB5AP
160 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000161 addis r4,0,CS5_AP@h
162 ori r4,r4,CS5_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200163 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000164
Stefan Roesed1c3b272009-09-09 16:25:29 +0200165 addi r4,0,PB5CR
166 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000167 addis r4,0,CS5_CR@h
168 ori r4,r4,CS5_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200169 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000170
wdenk8bde7f72003-06-27 21:31:46 +0000171 /*----------------------------------------------------------------------- */
172 /* Memory Bank 6 (CPU LED0) initialization */
173 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000174
Stefan Roesed1c3b272009-09-09 16:25:29 +0200175 addi r4,0,PB6AP
176 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000177 addis r4,0,CS6_AP@h
178 ori r4,r4,CS6_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200179 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000180
Stefan Roesed1c3b272009-09-09 16:25:29 +0200181 addi r4,0,PB6CR
182 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000183 addis r4,0,CS6_CR@h
184 ori r4,r4,CS5_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200185 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000186
wdenk8bde7f72003-06-27 21:31:46 +0000187 /*----------------------------------------------------------------------- */
188 /* Memory Bank 7 (CPU LED1) initialization */
189 /*----------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000190
Stefan Roesed1c3b272009-09-09 16:25:29 +0200191 addi r4,0,PB7AP
192 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000193 addis r4,0,CS7_AP@h
194 ori r4,r4,CS7_AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200195 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000196
Stefan Roesed1c3b272009-09-09 16:25:29 +0200197 addi r4,0,PB7CR
198 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000199 addis r4,0,CS7_CR@h
200 ori r4,r4,CS7_CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200201 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000202
203/* addis r4,r0,FPGA_BRDC@h */
wdenk8bde7f72003-06-27 21:31:46 +0000204/* ori r4,r4,FPGA_BRDC@l */
205/* lbz r3,0(r4) /###*get FPGA board control reg */
206/* eieio */
207/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */
wdenkfe8c2802002-11-03 00:38:21 +0000208/* stb r3,0(r4) */
209
210 nop /* pass2 DCR errata #8 */
wdenk8bde7f72003-06-27 21:31:46 +0000211 blr
wdenkfe8c2802002-11-03 00:38:21 +0000212
213/*----------------------------------------------------------------------------- */
214/* Function: sdram_init */
215/* Description: Configures SDRAM memory banks on ERIC. */
216/* We do manually init our SDRAM. */
217/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
218/* It is assumed that a 32MB 12x8(2) SDRAM is used. */
219/*----------------------------------------------------------------------------- */
wdenk8bde7f72003-06-27 21:31:46 +0000220 .globl sdram_init
wdenkfe8c2802002-11-03 00:38:21 +0000221
222sdram_init:
223
224 mflr r31
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#ifdef CONFIG_SYS_SDRAM_MANUALLY
wdenk8bde7f72003-06-27 21:31:46 +0000227 /*------------------------------------------------------------------- */
228 /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
229 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000230
Stefan Roese95b602b2009-09-24 13:59:57 +0200231 addi r4,0,SDRAM0_B0CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200232 mtdcr SDRAM0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000233 addis r4,0,MB0CF@h
234 ori r4,r4,MB0CF@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200235 mtdcr SDRAM0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000236
wdenk8bde7f72003-06-27 21:31:46 +0000237 /*------------------------------------------------------------------- */
238 /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
239 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000240
Stefan Roese95b602b2009-09-24 13:59:57 +0200241 addi r4,0,SDRAM0_B1CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200242 mtdcr SDRAM0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000243 addis r4,0,MB1CF@h
244 ori r4,r4,MB1CF@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200245 mtdcr SDRAM0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000246
wdenk8bde7f72003-06-27 21:31:46 +0000247 /*------------------------------------------------------------------- */
248 /* Set MB2CF for bank 2. off */
249 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000250
Stefan Roese95b602b2009-09-24 13:59:57 +0200251 addi r4,0,SDRAM0_B2CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200252 mtdcr SDRAM0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000253 addis r4,0,MB2CF@h
254 ori r4,r4,MB2CF@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200255 mtdcr SDRAM0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000256
wdenk8bde7f72003-06-27 21:31:46 +0000257 /*------------------------------------------------------------------- */
258 /* Set MB3CF for bank 3. off */
259 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000260
Stefan Roese95b602b2009-09-24 13:59:57 +0200261 addi r4,0,SDRAM0_B3CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200262 mtdcr SDRAM0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000263 addis r4,0,MB3CF@h
264 ori r4,r4,MB3CF@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200265 mtdcr SDRAM0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000266
wdenk8bde7f72003-06-27 21:31:46 +0000267 /*------------------------------------------------------------------- */
268 /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
269 /* To set the appropriate timings, we need to know the SDRAM speed. */
wdenkfe8c2802002-11-03 00:38:21 +0000270 /* We can use the PLB speed since the SDRAM speed is the same as */
271 /* the PLB speed. The PLB speed is the FBK divider times the */
272 /* 405GP reference clock, which on the Walnut board is 33Mhz. */
273 /* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
274 /* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
275 /* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
276 /* maybe 133Mhz. */
wdenk8bde7f72003-06-27 21:31:46 +0000277 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000278
Stefan Roesed1c3b272009-09-09 16:25:29 +0200279 mfdcr r5,CPC0_PSR /* determine FBK divider */
wdenk8bde7f72003-06-27 21:31:46 +0000280 /* via STRAP reg to calc PLB speed. */
281 /* SDRAM speed is the same as the PLB */
282 /* speed. */
283 rlwinm r4,r5,4,0x3 /* get FBK divide bits */
wdenkfe8c2802002-11-03 00:38:21 +0000284
285..chk_66:
wdenk8bde7f72003-06-27 21:31:46 +0000286 cmpi %cr0,0,r4,0x1
287 bne ..chk_100
wdenkfe8c2802002-11-03 00:38:21 +0000288 addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */
289 ori r6,r6,SDTR_66@l
290 addis r7,0,RTR_66 /* RTR value for 66Mhz */
wdenk8bde7f72003-06-27 21:31:46 +0000291 b ..sdram_ok
wdenkfe8c2802002-11-03 00:38:21 +0000292..chk_100:
wdenk8bde7f72003-06-27 21:31:46 +0000293 cmpi %cr0,0,r4,0x2
294 bne ..chk_133
295 addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
296 ori r6,r6,SDTR_100@l
297 addis r7,0,RTR_100 /* RTR value for 100Mhz */
298 b ..sdram_ok
wdenkfe8c2802002-11-03 00:38:21 +0000299..chk_133:
wdenk8bde7f72003-06-27 21:31:46 +0000300 addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
301 ori r6,r6,0x4015
302 addis r7,0,0x07F0 /* RTR value for 133Mhz */
wdenkfe8c2802002-11-03 00:38:21 +0000303
304..sdram_ok:
wdenk8bde7f72003-06-27 21:31:46 +0000305 /*------------------------------------------------------------------- */
306 /* Set SDTR1 */
307 /*------------------------------------------------------------------- */
Stefan Roese95b602b2009-09-24 13:59:57 +0200308 addi r4,0,SDRAM0_TR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200309 mtdcr SDRAM0_CFGADDR,r4
310 mtdcr SDRAM0_CFGDATA,r6
wdenkfe8c2802002-11-03 00:38:21 +0000311
wdenk8bde7f72003-06-27 21:31:46 +0000312 /*------------------------------------------------------------------- */
313 /* Set RTR */
314 /*------------------------------------------------------------------- */
Stefan Roese95b602b2009-09-24 13:59:57 +0200315 addi r4,0,SDRAM0_RTR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200316 mtdcr SDRAM0_CFGADDR,r4
317 mtdcr SDRAM0_CFGDATA,r7
wdenkfe8c2802002-11-03 00:38:21 +0000318
wdenk8bde7f72003-06-27 21:31:46 +0000319 /*------------------------------------------------------------------- */
320 /* Delay to ensure 200usec have elapsed since reset. Assume worst */
321 /* case that the core is running 200Mhz: */
322 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
323 /*------------------------------------------------------------------- */
324 addis r3,0,0x0000
325 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
326 mtctr r3
wdenkfe8c2802002-11-03 00:38:21 +0000327..spinlp2:
wdenk8bde7f72003-06-27 21:31:46 +0000328 bdnz ..spinlp2 /* spin loop */
wdenkfe8c2802002-11-03 00:38:21 +0000329
wdenk8bde7f72003-06-27 21:31:46 +0000330 /*------------------------------------------------------------------- */
331 /* Set memory controller options reg, MCOPT1. */
wdenkfe8c2802002-11-03 00:38:21 +0000332 /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
333 /* read/prefetch. */
wdenk8bde7f72003-06-27 21:31:46 +0000334 /*------------------------------------------------------------------- */
Stefan Roese95b602b2009-09-24 13:59:57 +0200335 addi r4,0,SDRAM0_CFG
Stefan Roesed1c3b272009-09-09 16:25:29 +0200336 mtdcr SDRAM0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000337 addis r4,0,0x8080 /* set DC_EN=1 */
338 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200339 mtdcr SDRAM0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000340
wdenk8bde7f72003-06-27 21:31:46 +0000341 /*------------------------------------------------------------------- */
342 /* Delay to ensure 10msec have elapsed since reset. This is */
343 /* required for the MPC952 to stabalize. Assume worst */
344 /* case that the core is running 200Mhz: */
345 /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
346 /* This delay should occur before accessing SDRAM. */
347 /*------------------------------------------------------------------- */
348 addis r3,0,0x001E
349 ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
350 mtctr r3
wdenkfe8c2802002-11-03 00:38:21 +0000351..spinlp3:
wdenk8bde7f72003-06-27 21:31:46 +0000352 bdnz ..spinlp3 /* spin loop */
wdenkfe8c2802002-11-03 00:38:21 +0000353
354#else
355/*fixme: do SDRAM Autoconfig from EEPROM here */
356
357#endif
wdenk8bde7f72003-06-27 21:31:46 +0000358 mtlr r31 /* restore lr */
359 blr