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Dirk Behmead9bc8e2009-01-28 21:39:58 +01001/*
2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * Author :
6 * Manikandan Pillai <mani.pillai@ti.com>
7 *
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#include <common.h>
Ben Warren736fead2009-07-20 22:01:11 -070031#include <netdev.h>
Dirk Behmead9bc8e2009-01-28 21:39:58 +010032#include <asm/io.h>
33#include <asm/arch/mem.h>
34#include <asm/arch/mux.h>
35#include <asm/arch/sys_proto.h>
36#include <i2c.h>
37#include <asm/mach-types.h>
38#include "evm.h"
39
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +053040static u8 omap3_evm_version;
41
42u8 get_omap3_evm_rev(void)
43{
44 return omap3_evm_version;
45}
46
47static void omap3_evm_get_revision(void)
48{
49 unsigned int smsc_id;
50
51 /* Ethernet PHY ID is stored at ID_REV register */
52 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
53 printf("Read back SMSC id 0x%x\n", smsc_id);
54
55 switch (smsc_id) {
56 /* SMSC9115 chipset */
57 case 0x01150000:
58 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
59 break;
60 /* SMSC 9220 chipset */
61 case 0x92200000:
62 default:
63 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
64 }
65}
66
Tom Rix58911512009-04-01 22:02:20 -050067/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +010068 * Routine: board_init
69 * Description: Early hardware init.
Tom Rix58911512009-04-01 22:02:20 -050070 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +010071int board_init(void)
72{
73 DECLARE_GLOBAL_DATA_PTR;
74
75 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
76 /* board id for Linux */
77 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
78 /* boot param addr */
79 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
80
81 return 0;
82}
83
Tom Rix58911512009-04-01 22:02:20 -050084/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +010085 * Routine: misc_init_r
86 * Description: Init ethernet (done here so udelay works)
Tom Rix58911512009-04-01 22:02:20 -050087 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +010088int misc_init_r(void)
89{
90
91#ifdef CONFIG_DRIVER_OMAP34XX_I2C
92 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
93#endif
94
95#if defined(CONFIG_CMD_NET)
96 setup_net_chip();
97#endif
98
Dirk Behmee6a6a702009-03-12 19:30:50 +010099 dieid_num_r();
100
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100101 return 0;
102}
103
Tom Rix58911512009-04-01 22:02:20 -0500104/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100105 * Routine: set_muxconf_regs
106 * Description: Setting up the configuration Mux registers specific to the
107 * hardware. Many pins need to be moved from protect to primary
108 * mode.
Tom Rix58911512009-04-01 22:02:20 -0500109 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100110void set_muxconf_regs(void)
111{
112 MUX_EVM();
113}
114
Tom Rix58911512009-04-01 22:02:20 -0500115/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100116 * Routine: setup_net_chip
117 * Description: Setting up the configuration GPMC registers specific to the
118 * Ethernet hardware.
Tom Rix58911512009-04-01 22:02:20 -0500119 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100120static void setup_net_chip(void)
121{
Dirk Behme97a099e2009-08-08 09:30:21 +0200122 struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
Dirk Behme97a099e2009-08-08 09:30:21 +0200123 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100124
125 /* Configure GPMC registers */
Dirk Behme89411352009-08-08 09:30:22 +0200126 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
127 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
128 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
129 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
130 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
131 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
132 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100133
134 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
135 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
136 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
137 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
138 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
139 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
140 &ctrl_base->gpmc_nadv_ale);
141
142 /* Make GPIO 64 as output pin */
143 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
144
145 /* Now send a pulse on the GPIO pin */
146 writel(GPIO0, &gpio3_base->setdataout);
147 udelay(1);
148 writel(GPIO0, &gpio3_base->cleardataout);
149 udelay(1);
150 writel(GPIO0, &gpio3_base->setdataout);
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +0530151
152 /* determine omap3evm revision */
153 omap3_evm_get_revision();
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100154}
Ben Warren736fead2009-07-20 22:01:11 -0700155
156int board_eth_init(bd_t *bis)
157{
158 int rc = 0;
159#ifdef CONFIG_SMC911X
160 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
161#endif
162 return rc;
163}