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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * Written by Peter Figuli <peposh@etc.sk>, 2003.
20 *
21 * 2003/13/06 Initial MP10 Support copied from wepep250
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
28#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
29#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
30#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
31
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +020032#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +000033#define CONFIG_IMX_SERIAL1
34/*
35 * Select serial console configuration
36 */
37
wdenk281e00a2004-08-01 22:48:16 +000038/*
Jon Loeliger079a1362007-07-10 10:12:10 -050039 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
Jon Loeliger079a1362007-07-10 10:12:10 -050046/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050047 * Command line configuration.
wdenk281e00a2004-08-01 22:48:16 +000048 */
Jon Loeliger46da1e92007-07-04 22:33:30 -050049#include <config_cmd_default.h>
wdenk281e00a2004-08-01 22:48:16 +000050
Jon Loeliger46da1e92007-07-04 22:33:30 -050051#define CONFIG_CMD_NET
52#define CONFIG_CMD_PING
53#define CONFIG_CMD_DHCP
54
Jon Loeliger46da1e92007-07-04 22:33:30 -050055#undef CONFIG_CMD_CONSOLE
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020056#undef CONFIG_CMD_LOADS
57#undef CONFIG_CMD_SOURCE
Jon Loeliger46da1e92007-07-04 22:33:30 -050058
wdenk281e00a2004-08-01 22:48:16 +000059/*
60 * Boot options. Setting delay to -1 stops autostart count down.
61 * NOTE: Sending parameters to kernel depends on kernel version and
62 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
63 * parameters at all! Do not get confused by them so.
64 */
65#define CONFIG_BOOTDELAY -1
66#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
67#define CONFIG_BOOTCOMMAND "bootm 10040000"
68#define CONFIG_SHOW_BOOT_PROGRESS
69#define CONFIG_ETHADDR 80:81:82:83:84:85
70#define CONFIG_NETMASK 255.255.255.0
71#define CONFIG_IPADDR 10.10.10.9
72#define CONFIG_SERVERIP 10.10.10.10
73
74/*
75 * General options for u-boot. Modify to save memory foot print
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_LONGHELP /* undef saves memory */
78#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
79#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
80#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
81#define CONFIG_SYS_MAXARGS 16 /* max command args */
82#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk281e00a2004-08-01 22:48:16 +000083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
85#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk281e00a2004-08-01 22:48:16 +000086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
88#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk281e00a2004-08-01 22:48:16 +000089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk281e00a2004-08-01 22:48:16 +000091#define CONFIG_BAUDRATE 115200
92/*
93 * Definitions related to passing arguments to kernel.
94 */
95#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
96#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
97#define CONFIG_INITRD_TAG 1 /* send initrd params */
wdenk281e00a2004-08-01 22:48:16 +000098
wdenk281e00a2004-08-01 22:48:16 +000099/*
100 * Malloc pool need to host env + 128 Kb reserve for other allocations.
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk281e00a2004-08-01 22:48:16 +0000103
wdenk281e00a2004-08-01 22:48:16 +0000104#define CONFIG_STACKSIZE (120<<10) /* stack size */
105
106#ifdef CONFIG_USE_IRQ
107#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
108#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
109#endif
110
111/* SDRAM Setup Values
1120x910a8300 Precharge Command CAS 3
1130x910a8200 Precharge Command CAS 2
114
1150xa10a8300 AutoRefresh Command CAS 3
1160xa10a8200 Set AutoRefresh Command CAS 2 */
117
118#define PRECHARGE_CMD 0x910a8200
119#define AUTOREFRESH_CMD 0xa10a8200
wdenk281e00a2004-08-01 22:48:16 +0000120
121/*
122 * SDRAM Memory Map
123 */
124/* SH FIXME */
125#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
126#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
127#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
128
Torsten Koschorrek386393c2011-07-14 23:16:51 +0000129#define CONFIG_SYS_TEXT_BASE 0x10000000
130
131#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
132#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
133
wdenk281e00a2004-08-01 22:48:16 +0000134/*
wdenk281e00a2004-08-01 22:48:16 +0000135 * Configuration for FLASH memory for the Synertronixx board
136 */
137
138/* #define SCB9328_FLASH_32M */
139
140/* 32MB */
141#ifdef SCB9328_FLASH_32M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
143#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000144#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
145#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
146#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
147#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
148#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
149#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
150#else
151
152/* 16MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
154#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000155#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
156#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
157#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
158#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
159#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
160#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
161#endif /* SCB9328_FLASH_32M */
162
163/* This should be defined if CFI FLASH device is present. Actually benefit
164 is not so clear to me. In other words we can provide more informations
165 to user, but this expects more complex flash handling we do not provide
166 now.*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#undef CONFIG_SYS_FLASH_CFI
wdenk281e00a2004-08-01 22:48:16 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
170#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
wdenk281e00a2004-08-01 22:48:16 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
wdenk281e00a2004-08-01 22:48:16 +0000173
174/*
175 * This is setting for JFFS2 support in u-boot.
176 * Right now there is no gain for user, but later on booting kernel might be
177 * possible. Consider using XIP kernel running from flash to save RAM
178 * footprint.
Jon Loeliger079a1362007-07-10 10:12:10 -0500179 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk281e00a2004-08-01 22:48:16 +0000180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_JFFS2_FIRST_BANK 0
182#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
183#define CONFIG_SYS_JFFS2_NUM_BANKS 1
wdenk281e00a2004-08-01 22:48:16 +0000184
185/*
186 * Environment setup. Definitions of monitor location and size with
187 * definition of environment setup ends up in 2 possibilities.
188 * 1. Embeded environment - in u-boot code is space for environment
189 * 2. Environment is read from predefined sector of flash
190 * Right now we support 2. possiblity, but expecting no env placed
191 * on mentioned address right now. This also needs to provide whole
192 * sector for it - for us 256Kb is really waste of memory. U-boot uses
193 * default env. and until kernel parameters could be sent to kernel
194 * env. has no sense to us.
195 */
196
197/* Setup for PA23 which is Reset Default PA23 but has to become
198 CS5 */
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_GPR_A_VAL 0x00800000
201#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
wdenk281e00a2004-08-01 22:48:16 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_MONITOR_BASE 0x10000000
204#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200205#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200206#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
207#define CONFIG_ENV_SIZE 0x20000
wdenk281e00a2004-08-01 22:48:16 +0000208
209#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
210
211/*
212 * CSxU_VAL:
213 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
214 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
215 *
216 * CSxL_VAL:
217 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
218 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
219 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CS0U_VAL 0x000F2000
222#define CONFIG_SYS_CS0L_VAL 0x11110d01
223#define CONFIG_SYS_CS1U_VAL 0x000F0a00
224#define CONFIG_SYS_CS1L_VAL 0x11110601
225#define CONFIG_SYS_CS2U_VAL 0x0
226#define CONFIG_SYS_CS2L_VAL 0x0
wdenk281e00a2004-08-01 22:48:16 +0000227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
229#define CONFIG_SYS_CS3L_VAL 0x00000303
wdenk281e00a2004-08-01 22:48:16 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_CS4U_VAL 0x000F0a00
232#define CONFIG_SYS_CS4L_VAL 0x11110301
wdenk281e00a2004-08-01 22:48:16 +0000233
234/* CNC == 3 too long
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
wdenk281e00a2004-08-01 22:48:16 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237/* #define CONFIG_SYS_CS5U_VAL 0x00008400
wdenk281e00a2004-08-01 22:48:16 +0000238 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
239 kaum langsamer ist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240/* #define CONFIG_SYS_CS5U_VAL 0x00009400
241 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
wdenk281e00a2004-08-01 22:48:16 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CS5U_VAL 0x00008400
244#define CONFIG_SYS_CS5L_VAL 0x00000D03
wdenk281e00a2004-08-01 22:48:16 +0000245
Remy Bohmer60f61e62009-05-02 21:49:18 +0200246#define CONFIG_NET_MULTI 1
wdenk281e00a2004-08-01 22:48:16 +0000247#define CONFIG_DRIVER_DM9000 1
wdenk281e00a2004-08-01 22:48:16 +0000248#define CONFIG_DM9000_BASE 0x16000000
249#define DM9000_IO CONFIG_DM9000_BASE
250#define DM9000_DATA (CONFIG_DM9000_BASE+4)
wdenk281e00a2004-08-01 22:48:16 +0000251
252/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
253 f_ref=16,777MHz
254
255 0x002a141f: 191,9944MHz
256 0x040b2007: 144MHz
257 0x042a141f: 96MHz
258 0x0811140d: 64MHz
259 0x040e200e: 150MHz
260 0x00321431: 200MHz
261
262 0x08001800: 64MHz mit 16er Quarz
263 0x04001800: 96MHz mit 16er Quarz
264 0x04002400: 144MHz mit 16er Quarz
265
266 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
267 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
268
269#define CPU200
270
271#ifdef CPU200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_MPCTL0_VAL 0x00321431
wdenk281e00a2004-08-01 22:48:16 +0000273#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
wdenk281e00a2004-08-01 22:48:16 +0000275#endif
276
277/* #define BUS64 */
278#define BUS72
279
280#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SPCTL0_VAL 0x04002400
wdenk281e00a2004-08-01 22:48:16 +0000282#endif
283
284#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SPCTL0_VAL 0x04001800
wdenk281e00a2004-08-01 22:48:16 +0000286#endif
287
288#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_SPCTL0_VAL 0x08001800
wdenk281e00a2004-08-01 22:48:16 +0000290#endif
291
292/* Das ist der BCLK Divider, der aus der System PLL
293 BCLK und HCLK erzeugt:
294 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
295 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
296 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
297 0x2f001003 : 192MHz/5=38,4MHz
298 0x2f000003 : 64MHz/1
299 Bit 22: SPLL Restart
300 Bit 21: MPLL Restart */
301
302#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_CSCR_VAL 0x2f030003
wdenk281e00a2004-08-01 22:48:16 +0000304#endif
305
306#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_CSCR_VAL 0x2f030403
wdenk281e00a2004-08-01 22:48:16 +0000308#endif
309
310/*
311 * Well this has to be defined, but on the other hand it is used differently
312 * one may expect. For instance loadb command do not cares :-)
313 * So advice is - do not relay on this...
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk281e00a2004-08-01 22:48:16 +0000316
317#define MHZ16QUARZINUSE
318
319#ifdef MHZ16QUARZINUSE
320#define CONFIG_SYSPLL_CLK_FREQ 16000000
321#else
322#define CONFIG_SYSPLL_CLK_FREQ 16780000
323#endif
324
325#define CONFIG_SYS_CLK_FREQ 16780000
326
327/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_FMCR_VAL 0x00000001
wdenk281e00a2004-08-01 22:48:16 +0000329
330/* Bit[0:3] contain PERCLK1DIV for UART 1
331 0x000b00b ->b<- -> 192MHz/12=16MHz
332 0x000b00b ->8<- -> 144MHz/09=16MHz
333 0x000b00b ->3<- -> 64MHz/4=16MHz */
334
335#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PCDR_VAL 0x000b00b5
wdenk281e00a2004-08-01 22:48:16 +0000337#endif
338
339#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCDR_VAL 0x000b00b3
wdenk281e00a2004-08-01 22:48:16 +0000341#endif
342
343#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_PCDR_VAL 0x000b00b8
wdenk281e00a2004-08-01 22:48:16 +0000345#endif
346
347#endif /* __CONFIG_H */