blob: bd43e1dc9aaf02407a402f8e448fb176c385bf60 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000043
44#define CONFIG_BAUDRATE 9600
45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
46
wdenkc6097192002-11-03 00:24:07 +000047#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000048#undef CONFIG_BOOTCOMMAND
49
50#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000051
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
53#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
54
55#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000056#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000057#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020058#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
59
60#define CONFIG_NET_MULTI 1
61#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000062
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050063/*
64 * BOOTP options
65 */
66#define CONFIG_BOOTP_SUBNETMASK
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_DNS
71#define CONFIG_BOOTP_DNS2
72#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000073
wdenkc6097192002-11-03 00:24:07 +000074
Jon Loeliger49cf7e82007-07-05 19:52:35 -050075/*
76 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#define CONFIG_CMD_DHCP
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_IRQ
83#define CONFIG_CMD_IDE
84#define CONFIG_CMD_FAT
85#define CONFIG_CMD_ELF
86#define CONFIG_CMD_MII
87#define CONFIG_CMD_EEPROM
88
wdenkc6097192002-11-03 00:24:07 +000089
90#define CONFIG_MAC_PARTITION
91#define CONFIG_DOS_PARTITION
92
stroesea20b27a2004-12-16 18:05:42 +000093#define CONFIG_SUPPORT_VFAT
94
wdenkc837dcb2004-01-20 23:12:12 +000095#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000096
wdenkc837dcb2004-01-20 23:12:12 +000097#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000098
99/*
100 * Miscellaneous configurable options
101 */
102#define CFG_LONGHELP /* undef to save memory */
103#define CFG_PROMPT "=> " /* Monitor Command Prompt */
104
105#undef CFG_HUSH_PARSER /* use "hush" command parser */
106#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000107#define CFG_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000108#endif
109
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500110#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000111#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000112#else
wdenkc837dcb2004-01-20 23:12:12 +0000113#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000114#endif
115#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
116#define CFG_MAXARGS 16 /* max number of command args */
117#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
118
wdenkc837dcb2004-01-20 23:12:12 +0000119#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000120
wdenkc837dcb2004-01-20 23:12:12 +0000121#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000122
123#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
124#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
125
wdenkc837dcb2004-01-20 23:12:12 +0000126#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
127#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
128#define CFG_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000129
130/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000131#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000132 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
133 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000134
135#define CFG_LOAD_ADDR 0x100000 /* default load address */
136#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
137
wdenkc837dcb2004-01-20 23:12:12 +0000138#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000139
stroesea20b27a2004-12-16 18:05:42 +0000140#define CONFIG_LOOPW 1 /* enable loopw command */
141
wdenkc6097192002-11-03 00:24:07 +0000142#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
143
144/*-----------------------------------------------------------------------
145 * PCI stuff
146 *-----------------------------------------------------------------------
147 */
stroesea20b27a2004-12-16 18:05:42 +0000148#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
149#define PCI_HOST_FORCE 1 /* configure as pci host */
150#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000151
stroesea20b27a2004-12-16 18:05:42 +0000152#define CONFIG_PCI /* include pci support */
153#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
154#define CONFIG_PCI_PNP /* do pci plug-and-play */
155 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000156
stroesea20b27a2004-12-16 18:05:42 +0000157#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000158
stroesea20b27a2004-12-16 18:05:42 +0000159#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000160
stroesea20b27a2004-12-16 18:05:42 +0000161#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
162
163#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
164#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
165#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
166#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
Stefan Roese2076d0a2006-01-18 20:03:15 +0100167#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
168#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
stroesea20b27a2004-12-16 18:05:42 +0000169#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
170#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
171#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
172#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000173
174/*-----------------------------------------------------------------------
175 * IDE/ATA stuff
176 *-----------------------------------------------------------------------
177 */
wdenkc837dcb2004-01-20 23:12:12 +0000178#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
179#undef CONFIG_IDE_LED /* no led for ide supported */
180#undef CONFIG_IDE_RESET /* no reset for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000181
wdenkc837dcb2004-01-20 23:12:12 +0000182#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
183#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000184
wdenkc837dcb2004-01-20 23:12:12 +0000185#define CFG_ATA_BASE_ADDR 0xF0100000
186#define CFG_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000187
188#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000189#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
wdenkc6097192002-11-03 00:24:07 +0000190#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
191
192/*-----------------------------------------------------------------------
193 * Start addresses for the final memory configuration
194 * (Set up by the startup code)
195 * Please note that CFG_SDRAM_BASE _must_ start at 0
196 */
197#define CFG_SDRAM_BASE 0x00000000
198#define CFG_FLASH_BASE 0xFFFD0000
199#define CFG_MONITOR_BASE CFG_FLASH_BASE
200#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
201#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
202
203/*
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
207 */
208#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
209/*-----------------------------------------------------------------------
210 * FLASH organization
211 */
212#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
213#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
214
215#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217
wdenkc837dcb2004-01-20 23:12:12 +0000218#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
219#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
220#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000221/*
222 * The following defines are added for buggy IOP480 byte interface.
223 * All other boards should use the standard values (CPCI405 etc.)
224 */
wdenkc837dcb2004-01-20 23:12:12 +0000225#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
226#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
227#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000228
wdenkc837dcb2004-01-20 23:12:12 +0000229#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000230
stroesea20b27a2004-12-16 18:05:42 +0000231#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
232#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
233#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
234
wdenkc6097192002-11-03 00:24:07 +0000235#if 1 /* Use NVRAM for environment variables */
236/*-----------------------------------------------------------------------
237 * NVRAM organization
238 */
239#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
wdenkc6097192002-11-03 00:24:07 +0000240#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
241#define CFG_ENV_ADDR \
242 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000243
244#else /* Use EEPROM for environment variables */
245
stroesea20b27a2004-12-16 18:05:42 +0000246#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
247#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
248#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000249 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000250#endif
251
252/*-----------------------------------------------------------------------
253 * I2C EEPROM (CAT24WC08) for environment
254 */
255#define CONFIG_HARD_I2C /* I2c with hardware support */
256#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
257#define CFG_I2C_SLAVE 0x7F
258
259#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000260#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
261/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000262#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
263#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
264 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000265 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000266#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
267#define CFG_EEPROM_PAGE_WRITE_ENABLE
268
wdenkc6097192002-11-03 00:24:07 +0000269/*
270 * Init Memory Controller:
271 *
272 * BR0/1 and OR0/1 (FLASH)
273 */
274
275#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
276#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
277
278/*-----------------------------------------------------------------------
279 * External Bus Controller (EBC) Setup
280 */
281
wdenkc837dcb2004-01-20 23:12:12 +0000282/* Memory Bank 0 (Flash Bank 0) initialization */
283#define CFG_EBC_PB0AP 0x92015480
284#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000285
wdenkc837dcb2004-01-20 23:12:12 +0000286/* Memory Bank 1 (Flash Bank 1) initialization */
287#define CFG_EBC_PB1AP 0x92015480
288#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000289
wdenkc837dcb2004-01-20 23:12:12 +0000290/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
291#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
292#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000293
wdenkc837dcb2004-01-20 23:12:12 +0000294/* Memory Bank 3 (CompactFlash IDE) initialization */
295#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
296#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000297
wdenkc837dcb2004-01-20 23:12:12 +0000298/* Memory Bank 4 (NVRAM) initialization */
299#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
300#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000301
wdenkc837dcb2004-01-20 23:12:12 +0000302/* Memory Bank 5 (Quart) initialization */
303#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
304#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000305
306/*-----------------------------------------------------------------------
307 * FPGA stuff
308 */
309
310/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000311#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
312#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
313#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
314#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
315#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000316
317/*-----------------------------------------------------------------------
318 * Definitions for initial stack pointer and data area (in data cache)
319 */
320#if 1 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000321#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000322
wdenkc837dcb2004-01-20 23:12:12 +0000323#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
wdenkc6097192002-11-03 00:24:07 +0000324#else
wdenkc837dcb2004-01-20 23:12:12 +0000325#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
wdenkc6097192002-11-03 00:24:07 +0000326#endif
wdenkc837dcb2004-01-20 23:12:12 +0000327#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenkc6097192002-11-03 00:24:07 +0000328#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
329#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000330#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000331
332
333/*
334 * Internal Definitions
335 *
336 * Boot Flags
337 */
338#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
339#define BOOTFLAG_WARM 0x02 /* Software reboot */
340
341#endif /* __CONFIG_H */