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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
2 * i2c driver for Freescale mx31
3 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stefano Babic1d549ad2011-01-20 07:50:44 +000026#include <asm/io.h>
Sascha Hauercdace062008-03-26 20:40:49 +010027
Michal Simeka4a549b2008-07-14 19:45:35 +020028#if defined(CONFIG_HARD_I2C)
Sascha Hauercdace062008-03-26 20:40:49 +010029
Liu Hui-R64343127cec12011-01-03 22:27:39 +000030#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010031#include <asm/arch/imx-regs.h>
Sascha Hauercdace062008-03-26 20:40:49 +010032
33#define IADR 0x00
34#define IFDR 0x04
35#define I2CR 0x08
36#define I2SR 0x0c
37#define I2DR 0x10
38
39#define I2CR_IEN (1 << 7)
40#define I2CR_IIEN (1 << 6)
41#define I2CR_MSTA (1 << 5)
42#define I2CR_MTX (1 << 4)
43#define I2CR_TX_NO_AK (1 << 3)
44#define I2CR_RSTA (1 << 2)
45
46#define I2SR_ICF (1 << 7)
47#define I2SR_IBB (1 << 5)
48#define I2SR_IIF (1 << 1)
49#define I2SR_RX_NO_AK (1 << 0)
50
Liu Hui-R64343127cec12011-01-03 22:27:39 +000051#if defined(CONFIG_SYS_I2C_MX31_PORT1)
Sascha Hauercdace062008-03-26 20:40:49 +010052#define I2C_BASE 0x43f80000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010053#define I2C_CLK_OFFSET 26
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
Sascha Hauercdace062008-03-26 20:40:49 +010055#define I2C_BASE 0x43f98000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010056#define I2C_CLK_OFFSET 28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
Sascha Hauercdace062008-03-26 20:40:49 +010058#define I2C_BASE 0x43f84000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010059#define I2C_CLK_OFFSET 30
Liu Hui-R64343127cec12011-01-03 22:27:39 +000060#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
61#define I2C_BASE I2C1_BASE_ADDR
62#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
63#define I2C_BASE I2C2_BASE_ADDR
Stefano Babic04220612011-01-19 22:46:26 +000064#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
65#define I2C_BASE I2C_BASE_ADDR
Sascha Hauercdace062008-03-26 20:40:49 +010066#else
Stefano Babic04220612011-01-19 22:46:26 +000067#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
Sascha Hauercdace062008-03-26 20:40:49 +010068#endif
69
Stefano Babic81687212011-01-20 07:51:31 +000070#define I2C_MAX_TIMEOUT 10000
71#define I2C_MAX_RETRIES 3
Sascha Hauercdace062008-03-26 20:40:49 +010072
73static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
74 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
75 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
76
Stefano Babic1d549ad2011-01-20 07:50:44 +000077static inline void i2c_reset(void)
78{
79 writew(0, I2C_BASE + I2CR); /* Reset module */
80 writew(0, I2C_BASE + I2SR);
81 writew(I2CR_IEN, I2C_BASE + I2CR);
82}
83
Sascha Hauercdace062008-03-26 20:40:49 +010084void i2c_init(int speed, int unused)
85{
Liu Hui-R64343127cec12011-01-03 22:27:39 +000086 int freq;
Sascha Hauercdace062008-03-26 20:40:49 +010087 int i;
88
Liu Hui-R64343127cec12011-01-03 22:27:39 +000089#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +000090 struct clock_control_regs *sc_regs =
91 (struct clock_control_regs *)CCM_BASE;
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010092 /* start the required I2C clock */
Stefano Babic1d549ad2011-01-20 07:50:44 +000093 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
94 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +000095#endif
Stefano Babic30032712011-08-30 00:51:14 +000096 freq = mxc_get_clock(MXC_IPG_PERCLK);
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010097
Sascha Hauercdace062008-03-26 20:40:49 +010098 for (i = 0; i < 0x1f; i++)
99 if (freq / div[i] <= speed)
100 break;
101
Stefano Babic1d549ad2011-01-20 07:50:44 +0000102 debug("%s: speed: %d\n", __func__, speed);
Sascha Hauercdace062008-03-26 20:40:49 +0100103
Stefano Babic1d549ad2011-01-20 07:50:44 +0000104 writew(i, I2C_BASE + IFDR);
105 i2c_reset();
Sascha Hauercdace062008-03-26 20:40:49 +0100106}
107
Stefano Babic81687212011-01-20 07:51:31 +0000108static int wait_idle(void)
109{
110 int timeout = I2C_MAX_TIMEOUT;
111
112 while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) {
113 writew(0, I2C_BASE + I2SR);
114 udelay(1);
115 }
116 return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB));
117}
118
Sascha Hauercdace062008-03-26 20:40:49 +0100119static int wait_busy(void)
120{
Stefano Babic81687212011-01-20 07:51:31 +0000121 int timeout = I2C_MAX_TIMEOUT;
Sascha Hauercdace062008-03-26 20:40:49 +0100122
Stefano Babic81687212011-01-20 07:51:31 +0000123 while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
Sascha Hauercdace062008-03-26 20:40:49 +0100124 udelay(1);
Stefano Babic1d549ad2011-01-20 07:50:44 +0000125 writew(0, I2C_BASE + I2SR); /* clear interrupt */
Sascha Hauercdace062008-03-26 20:40:49 +0100126
127 return timeout;
128}
129
Stefano Babic81687212011-01-20 07:51:31 +0000130static int wait_complete(void)
131{
132 int timeout = I2C_MAX_TIMEOUT;
133
134 while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) {
135 writew(0, I2C_BASE + I2SR);
136 udelay(1);
137 }
138 udelay(200);
139
140 writew(0, I2C_BASE + I2SR); /* clear interrupt */
141
142 return timeout;
143}
144
145
Sascha Hauercdace062008-03-26 20:40:49 +0100146static int tx_byte(u8 byte)
147{
Stefano Babic1d549ad2011-01-20 07:50:44 +0000148 writew(byte, I2C_BASE + I2DR);
Sascha Hauercdace062008-03-26 20:40:49 +0100149
Stefano Babic81687212011-01-20 07:51:31 +0000150 if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
Sascha Hauercdace062008-03-26 20:40:49 +0100151 return -1;
152 return 0;
153}
154
Stefano Babic81687212011-01-20 07:51:31 +0000155static int rx_byte(int last)
Sascha Hauercdace062008-03-26 20:40:49 +0100156{
Stefano Babic81687212011-01-20 07:51:31 +0000157 if (!wait_complete())
Sascha Hauercdace062008-03-26 20:40:49 +0100158 return -1;
159
Stefano Babic81687212011-01-20 07:51:31 +0000160 if (last)
161 writew(I2CR_IEN, I2C_BASE + I2CR);
162
Stefano Babic1d549ad2011-01-20 07:50:44 +0000163 return readw(I2C_BASE + I2DR);
Sascha Hauercdace062008-03-26 20:40:49 +0100164}
165
166int i2c_probe(uchar chip)
167{
168 int ret;
169
Stefano Babic1d549ad2011-01-20 07:50:44 +0000170 writew(0, I2C_BASE + I2CR); /* Reset module */
171 writew(I2CR_IEN, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100172
Stefano Babic1d549ad2011-01-20 07:50:44 +0000173 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100174 ret = tx_byte(chip << 1);
Stefano Babic1d549ad2011-01-20 07:50:44 +0000175 writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100176
177 return ret;
178}
179
180static int i2c_addr(uchar chip, uint addr, int alen)
181{
Stefano Babic81687212011-01-20 07:51:31 +0000182 int i, retry = 0;
183 for (retry = 0; retry < 3; retry++) {
184 if (wait_idle())
185 break;
186 i2c_reset();
187 for (i = 0; i < I2C_MAX_TIMEOUT; i++)
188 udelay(1);
189 }
190 if (retry >= I2C_MAX_RETRIES) {
191 debug("%s:bus is busy(%x)\n",
192 __func__, readw(I2C_BASE + I2SR));
Sascha Hauercdace062008-03-26 20:40:49 +0100193 return -1;
Stefano Babic81687212011-01-20 07:51:31 +0000194 }
195 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100196
Stefano Babic81687212011-01-20 07:51:31 +0000197 if (!wait_busy()) {
198 debug("%s:trigger start fail(%x)\n",
199 __func__, readw(I2C_BASE + I2SR));
200 return -1;
201 }
202
203 if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
204 debug("%s:chip address cycle fail(%x)\n",
205 __func__, readw(I2C_BASE + I2SR));
206 return -1;
207 }
Sascha Hauercdace062008-03-26 20:40:49 +0100208 while (alen--)
Stefano Babic81687212011-01-20 07:51:31 +0000209 if (tx_byte((addr >> (alen * 8)) & 0xff) ||
210 (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
211 debug("%s:device address cycle fail(%x)\n",
212 __func__, readw(I2C_BASE + I2SR));
Sascha Hauercdace062008-03-26 20:40:49 +0100213 return -1;
Stefano Babic81687212011-01-20 07:51:31 +0000214 }
Sascha Hauercdace062008-03-26 20:40:49 +0100215 return 0;
216}
217
218int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
219{
Stefano Babic81687212011-01-20 07:51:31 +0000220 int timeout = I2C_MAX_TIMEOUT;
Sascha Hauercdace062008-03-26 20:40:49 +0100221 int ret;
222
Stefano Babic1d549ad2011-01-20 07:50:44 +0000223 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
224 __func__, chip, addr, alen, len);
Sascha Hauercdace062008-03-26 20:40:49 +0100225
226 if (i2c_addr(chip, addr, alen)) {
227 printf("i2c_addr failed\n");
228 return -1;
229 }
230
Stefano Babic1d549ad2011-01-20 07:50:44 +0000231 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100232
233 if (tx_byte(chip << 1 | 1))
234 return -1;
235
Stefano Babic1d549ad2011-01-20 07:50:44 +0000236 writew(I2CR_IEN | I2CR_MSTA |
237 ((len == 1) ? I2CR_TX_NO_AK : 0),
238 I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100239
Stefano Babic1d549ad2011-01-20 07:50:44 +0000240 ret = readw(I2C_BASE + I2DR);
Sascha Hauercdace062008-03-26 20:40:49 +0100241
242 while (len--) {
Stefano Babic81687212011-01-20 07:51:31 +0000243 ret = rx_byte(len == 0);
244 if (ret < 0)
Sascha Hauercdace062008-03-26 20:40:49 +0100245 return -1;
246 *buf++ = ret;
247 if (len <= 1)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000248 writew(I2CR_IEN | I2CR_MSTA |
249 I2CR_TX_NO_AK,
250 I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100251 }
252
Stefano Babic1d549ad2011-01-20 07:50:44 +0000253 writew(I2CR_IEN, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100254
Stefano Babic1d549ad2011-01-20 07:50:44 +0000255 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
Sascha Hauercdace062008-03-26 20:40:49 +0100256 udelay(1);
257
258 return 0;
259}
260
261int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
262{
Stefano Babic1d549ad2011-01-20 07:50:44 +0000263 int timeout = I2C_MAX_TIMEOUT;
264 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
265 __func__, chip, addr, alen, len);
Sascha Hauercdace062008-03-26 20:40:49 +0100266
267 if (i2c_addr(chip, addr, alen))
268 return -1;
269
270 while (len--)
271 if (tx_byte(*buf++))
272 return -1;
273
Stefano Babic1d549ad2011-01-20 07:50:44 +0000274 writew(I2CR_IEN, I2C_BASE + I2CR);
Sascha Hauercdace062008-03-26 20:40:49 +0100275
Stefano Babic1d549ad2011-01-20 07:50:44 +0000276 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
Sascha Hauercdace062008-03-26 20:40:49 +0100277 udelay(1);
278
279 return 0;
280}
281
282#endif /* CONFIG_HARD_I2C */