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Mike Frysingercb4b5e82008-10-12 23:08:03 -04001/*
2 * U-boot - Configuration file for BF537 PNAV board
3 */
4
5#ifndef __CONFIG_BF537_PNAV_H__
6#define __CONFIG_BF537_PNAV_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingercb4b5e82008-10-12 23:08:03 -04009
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingercb4b5e82008-10-12 23:08:03 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 24576000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x3b7
49#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Mike Frysinger4c95ff62010-10-01 19:42:08 -040055#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercb4b5e82008-10-12 23:08:03 -040056#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
65#define CONFIG_RMII
Mike Frysingercb4b5e82008-10-12 23:08:03 -040066#endif
67#define CONFIG_HOSTNAME bf537-pnav
68/* Uncomment next line to use fixed MAC address */
69/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
Masahiro Yamadac42f56d2014-04-18 19:09:49 +090070#define CONFIG_LIB_RAND
Mike Frysingercb4b5e82008-10-12 23:08:03 -040071
72/*
73 * Flash Settings
74 */
75#define CONFIG_FLASH_CFI_DRIVER
76#define CONFIG_SYS_FLASH_BASE 0x20000000
77#define CONFIG_SYS_FLASH_CFI
78#define CONFIG_SYS_MAX_FLASH_BANKS 1
79#define CONFIG_SYS_MAX_FLASH_SECT 71
80
81
82/*
83 * SPI Settings
84 */
85#define CONFIG_BFIN_SPI
86#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040087#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercb4b5e82008-10-12 23:08:03 -040088#define CONFIG_SPI_FLASH
89#define CONFIG_SPI_FLASH_STMICRO
90
91
92/*
93 * Env Storage Settings
94 */
95#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysinger76d82182009-07-21 22:17:36 -040096#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercb4b5e82008-10-12 23:08:03 -040097#define CONFIG_ENV_IS_IN_SPI_FLASH
98#define CONFIG_ENV_OFFSET 0x4000
99#else
100#define ENV_IS_EMBEDDED
101#define CONFIG_ENV_IS_IN_FLASH 1
102#define CONFIG_ENV_ADDR 0x20004000
103#define CONFIG_ENV_OFFSET 0x4000
104#endif
105#define CONFIG_ENV_SIZE 0x1000
106#define CONFIG_ENV_SECT_SIZE 0x2000
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400107#ifdef ENV_IS_EMBEDDED
108/* WARNING - the following is hand-optimized to fit within
109 * the sector before the environment sector. If it throws
110 * an error during compilation remove an object here to get
111 * it linked after the configuration sector.
112 */
113# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900114 arch/blackfin/lib/built-in.o (.text*); \
115 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400116 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500117 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400118#endif
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400119
120
121/*
122 * NAND Settings
123 */
124#define CONFIG_NAND_PLAT
125
126#define CONFIG_SYS_NAND_BASE 0x20100000
127#define CONFIG_SYS_MAX_NAND_DEVICE 1
128
129#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
130#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400131#define BFIN_NAND_WRITE(addr, cmd) \
132 do { \
133 bfin_write8(addr, cmd); \
134 SSYNC(); \
135 } while (0)
136
137#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
138#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400139#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400140
141
142/*
143 * I2C settings
144 */
Scott Jiangc4697032014-11-13 15:30:55 +0800145#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800146#define CONFIG_SYS_I2C_ADI
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400147
148
149/*
150 * Misc Settings
151 */
152#define CONFIG_BAUDRATE 115200
153#define CONFIG_MISC_INIT_R
154#define CONFIG_RTC_BFIN
155#define CONFIG_UART_CONSOLE 0
156
157/* JFFS Partition offset set */
158#define CONFIG_SYS_JFFS2_FIRST_BANK 0
159#define CONFIG_SYS_JFFS2_NUM_BANKS 1
160/* 512k reserved for u-boot */
161#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
162
163#define CONFIG_BOOTCOMMAND "run nandboot"
164#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
165
166
167/*
168 * Pull in common ADI header for remaining command/environment setup
169 */
170#include <configs/bfin_adi_common.h>
171
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400172#endif